CN109037351A - A kind of Transient Voltage Suppressor and preparation method thereof - Google Patents
A kind of Transient Voltage Suppressor and preparation method thereof Download PDFInfo
- Publication number
- CN109037351A CN109037351A CN201810891020.0A CN201810891020A CN109037351A CN 109037351 A CN109037351 A CN 109037351A CN 201810891020 A CN201810891020 A CN 201810891020A CN 109037351 A CN109037351 A CN 109037351A
- Authority
- CN
- China
- Prior art keywords
- injection
- district
- conduction type
- sub
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000001052 transient effect Effects 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 248
- 239000007924 injection Substances 0.000 claims abstract description 248
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000000034 method Methods 0.000 claims description 44
- 230000008569 process Effects 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 229940090044 injection Drugs 0.000 description 179
- 150000002500 ions Chemical class 0.000 description 33
- 238000005530 etching Methods 0.000 description 22
- 238000001312 dry etching Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 12
- -1 Can Chemical class 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a kind of Transient Voltage Suppressors and preparation method thereof, which comprises provides substrate；Groove is formed over the substrate；The injection sub-district of multiple first conduction types and the second conduction type is alternatively formed in the substrate area of the trenched side-wall and bottom, wherein, what is formed in the substrate area of the channel bottom is the injection sub-district of the first conduction type, and what is formed in the top of the substrate area of the trenched side-wall is the injection sub-district of the second conduction type；Side wall is formed on the trenched side-wall；Form first electrode and second electrode；Wherein, the first electrode is formed in the groove and is electrically connected with the injection sub-district for the first conduction type for being located at the channel bottom, and the second electrode is electrically connected with the injection sub-district of second conduction type at the top for the substrate area for being located at the trenched side-wall.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically a kind of Transient Voltage Suppressor and preparation method thereof.
Background technique
Transient Voltage Suppressor be it is a kind of be used to protect sensitive semiconductor device, make its destroy from transient voltage surge and
Specially designed solid-state semiconductor device, it has clamp coefficient is small, small in size, response is fast, leakage current is small and reliability is high etc.
Advantage, thus be widely used on voltage transient and carrying out surge protection.With power MOS pipe (metal-oxid-
Semiconductor, Metal-oxide-semicondutor) for, currently used Transient Voltage Suppressor is made in the grid of device
On the liner of pole, play the role of discharge prevention grid oxic horizon.Due to the current generally planar structure of Transient Voltage Suppressor,
More diodes of connecting just are had to increase the protection voltage of Transient Voltage Suppressor for certain devices or circuit
To realize partial pressure, this is inevitable for the waste of area, while being also unfavorable for the layout of device or circuit.
Summary of the invention
The embodiment of the invention provides a kind of Transient Voltage Suppressor and preparation method thereof, may be implemented do not increasing device
Increase protection voltage, high reliablity under the premise of area, and performance is stablized.
In a first aspect, the present invention provides a kind of Transient Voltage Suppressors, comprising: the substrate with a groove；It is formed in
The injection sub-district of multiple alternate first conduction types and the second conduction type of the trenched side-wall and the substrate area of bottom,
Wherein, what is formed in the corresponding substrate area of the channel bottom is the injection sub-district of the first conduction type, in the groove
What is formed in the top of the corresponding substrate area of side wall is the injection sub-district of the second conduction type；It is formed on the trenched side-wall
Side wall；First electrode, the first electrode are formed in the groove and the first conduction type positioned at the channel bottom
Injection sub-district electrical connection；And second electrode, the second electrode and the second conduction type positioned at the upper surface of substrate
Inject sub-district electrical connection.
Second aspect, the present invention provides a kind of production methods of Transient Voltage Suppressor, which comprises provides lining
Bottom；Groove is formed over the substrate；It is conductive that multiple first are alternatively formed in the substrate area of the trenched side-wall and bottom
The injection sub-district of type and the second conduction type, wherein what is formed in the corresponding substrate area of the channel bottom is first
The injection sub-district of conduction type, what is formed in the top of the corresponding substrate area of the trenched side-wall is the second conduction type
Inject sub-district；Side wall is formed on the trenched side-wall；Form first electrode and second electrode；Wherein, the first electrode shape
Be electrically connected with the injection sub-district for the first conduction type for being located at the channel bottom in groove described in Cheng Yu, the second electrode and
Positioned at the injection sub-district electrical connection of second conduction type at the top of the substrate area of the trenched side-wall.
The embodiment of the present invention is by forming the groove and being formed in the substrate area of the trenched side-wall and bottom
The mode of the injection sub-district of multiple alternate first conduction types and the second conduction type, and then form the transient voltage and inhibit
If desired device increases the protection voltage of Transient Voltage Suppressor, it is only necessary to which the depth for increasing groove increases the injection of Doped ions i.e.
Can, do not need the area for increasing device, while yet convenient device or the layout of circuit.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow diagram of the manufacturing method for the Transient Voltage Suppressor that one embodiment of the invention provides；
Fig. 2 is the schematic diagram of the section structure for the Transient Voltage Suppressor that one embodiment of the invention provides；
Fig. 3 to Figure 16 is the cross-section structure signal of the forming process for the Transient Voltage Suppressor that one embodiment of the invention provides
Figure；
Figure 17 be another embodiment of the present invention provides Transient Voltage Suppressor the schematic diagram of the section structure；
In description of symbols: 1, substrate；2, groove；3, injection region；31, the first injection sub-district；32, the second injection
Area；4, dielectric layer；51, oxide layer；52, side wall；61, first electrode；62, second electrode；7, mask layer.
Specific embodiment
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Please refer to Fig. 1 and Fig. 2, a kind of production method of Transient Voltage Suppressor, comprising:
Step S01: substrate 1 is provided；
Step S02: groove 2 is formed on the substrate 1；
Step S03: multiple first conduction types are alternatively formed in 1 region of substrate of 2 side wall of groove and bottom
Inject the injection sub-district 32 of sub-district 31 and the second conduction type, wherein the shape in corresponding 1 region of substrate in 2 bottom of groove
At be the first conduction type injection sub-district 31, interior formation is at the top of corresponding 1 region of substrate of 2 side wall of groove
The injection sub-district 32 of two conduction types；
Step S04: side wall 52 is formed on 2 side wall of groove；
Step S05: first electrode 61 and second electrode 62 are formed；Wherein, the first electrode 61 is formed in the groove 2
It is interior be electrically connected with the injection sub-district 31 of the first conduction type that is being located at 2 bottom of groove, the second electrode 62 with positioned at institute
The injection sub-district 32 for stating the second conduction type at the top of 1 region of substrate of 2 side wall of groove is electrically connected.
It is appreciated that by forming the groove 2 and being formed in 1 region of substrate of 2 side wall of groove and bottom
The mode of the injection sub-district 32 of the injection sub-district 31 and the second conduction type of multiple alternate first conduction types, and then form institute
Transient Voltage Suppressor is stated, the protection voltage of Transient Voltage Suppressor is if desired increased, it is only necessary to increase the depth of groove 2, increase
The injection of Doped ions does not need the area for increasing device, while yet convenient device or the layout of circuit.
With reference to the accompanying drawings, the method for the above-mentioned formation Transient Voltage Suppressor is elaborated.
Special to illustrate herein for convenience of subsequent description: first conduction type can be N-type, then, described second leads
Electric type is p-type, conversely, first conduction type may be p-type, correspondingly, second conduction type is N-type.?
In next embodiment, retouched so that first conduction type is N-type and second conduction type is p-type as an example
It states, but is defined not to this.
Attached drawing 3 is please referred to, step S01 is executed: substrate 1 is provided；Specifically, the substrate 1 presses down as the transient voltage
The carrier of device processed primarily serves the effect of support.In the present embodiment, it is silicon substrate 1 that the substrate 1, which is material, and silicon is
Most common, cheap and stable performance semiconductor material, in other embodiments, the material of the substrate 1 can also be silicon
Substrate, germanium substrate or germanium silicon substrate etc..In the present embodiment, the substrate 1 is free of Doped ions, in other embodiments
In, also substrate can be lightly doped for p-type or N-type in the substrate 1.
Attached drawing 4 is please referred to, step S02 is executed: forming groove 2 on the substrate 1, the groove 2 is formed in the lining
The upper surface at bottom 1, specifically, the process for forming the groove 2 can be with are as follows: etching barrier layer is formed on the substrate 1, and (figure is not
Show), photoresist layer (not shown) is then formed on etching barrier layer, later using the mask plate with 2 figure of groove
The photoresist layer is exposed, then is developed, the photoresist layer with 2 figure of groove is obtained.It is described to have
The photoresist layer of 2 figure of groove is exposure mask, using lithographic methods such as reactive ion etching methods, etches and is formed on etching barrier layer
The figure opening (not shown) of the groove 2.Then it using the etching barrier layer being open with 2 figure of groove as exposure mask, adopts
With the methods of wet etching or dry etching, 1 region of the substrate for the barrier layer covering that is not etched is removed, and then in the lining
The groove 2 is formed in bottom 1, the width of the groove 2 is usually between 1-2um.Hereafter the methods of chemical cleaning can be used
Remove photoresist layer and etching barrier layer.It in above process, can also be in photoresist layer and etching resistance in order to guarantee exposure accuracy
Anti-reflecting layer is formed between barrier.
Attached drawing 5 is please referred to, step S03 is executed: being alternatively formed in 1 region of substrate of 2 side wall of groove and bottom more
The injection sub-district 31 of a first conduction type and the injection sub-district 32 of the second conduction type, wherein the lining in 2 bottom of groove
What is formed in 1 region of bottom is the injection sub-district 31 of the first conduction type, the shape in the top of the substrate area of the trenched side-wall
At be the second conduction type injection sub-district 32.In the present embodiment, the multiple injection sub-district includes the first of N+1
Sub-district 31 and N number of second injection sub-district 32 are injected, the first injection sub-district 31 is injection of first conduction type
Area 31, the second injection sub-district 32 are the injection sub-district 32 of second conduction type, and N is positive odd number；
Attached drawing 13 is arrived please with reference to attached drawing 6, more specifically, forms the N+1 first injection sub-district 31 and N number of second
The step of injecting sub-district 32 includes: to do the first injection in 2 side wall of groove, in the substrate 1 of 2 side wall of groove and bottom
The injection region 3 of the first conduction type is formed in region；The injection of n times second is done in the injection region 3, and described each time doing
One layer of dielectric layer 4 is formed in 2 bottom of groove before second injection, the second injection is made to accumulate the dielectric layer 4 formed every time
For mask, the injection sub-district 31 of the multiple first conduction type and the injection sub-district 32 of the second conduction type are gradually formed,
In, ionic conduction type when doing the second injection for the first time is opposite with the ionic conduction type for doing first injection and ion is infused
Enter the ion implantation dosage that dosage is higher than first injection, the 3 region transoid of injection region that 2 side wall of groove is exposed
At the second conduction type；In the case where N is not 1, second to the second of n-th ion concentration when injecting is done relative to doing
Second injection for the first time successively increases and the conduction type with previous second injection is on the contrary, with respectively by the groove 2
It is opposite after conduction type transoid Cheng Yuqian mono- time second injection in 3 region of injection region that side wall exposes, wherein first note
Entering with second injection is inclination injection；Remove the N layer dielectric layer 4 in the groove 2.It is appreciated that by repeating institute
The second injection is stated, the injection sub-district 31 and of concatenated first conduction type of multiple alternatings can be formed in the injection region 3
The injection sub-district 32 of two conduction types, and then multiple concatenated diodes are formed in the injection region 3, if desired increase transient state
The protection voltage of voltage suppressor, it is only necessary to increase the depth of the groove 2, increase the number of second injection, be not required to
While additionally increasing the area of device, also convenient device or the layout of circuit.More specifically, the injection of first injection
Ion is phosphonium ion, in other embodiments, the injection ion of first injection can also for other pentavalents such as arsenic or antimony from
Son.The injection ion for doing second injection for the first time is boron ion, in other embodiments, can also for indium, gallium etc. other
Trivalent ion；It is envisioned that injecting conduction type and the first time institute of ion if doing second of second injection
State the second injection on the contrary, it, which injects ion, to be phosphonium ion, can also be other pentavalent ions such as arsenic or antimony, then doing the
To inject the conduction type of ion opposite and with the with doing second described second for the conduction type of the second injection ion three times
The ionic conduction type of primary second injection is identical, repeatedly, until the breakdown of multiple concatenated diodes of formation
Voltage is met the requirements.It should be noted that the number for doing second injection must be positive odd number, so that the channel bottom
1 region of substrate in the injection sub-district 31 of the first conduction type that is formed with it is interior at the top of 1 region of substrate of the trenched side-wall
What is formed is the injection sub-district 32 of the second conduction type, so as to the formation of subsequent electrode.
Further, include: the step of dielectric layer 4 are formed on 2 bottom of groove on 1 surface of substrate and
Deposited oxide in the groove 2；The oxide is etched back to certain thickness, to form the dielectric layer 4, the oxide
It can be silica, aluminium oxide or silica and the combination of aluminium oxide etc., can be dry etching to the etching of the oxide
Or wet etching, in the present embodiment, preferably dry etching, the etch rate of dry etching are more equal than wet etching
It is even, meanwhile, using dry etching extremely accurate etching effect can be obtained with strict control process.
Attached drawing 13 is arrived please continue to refer to attached drawing 6, to divide in corresponding 3 region of injection region of the two side walls of the groove 2
It Xing Cheng not be for three series connection and the identical diode in direction, specifically to the injection of the multiple alternate first conduction type
The formation basic theory of the injection sub-district 32 of area 31 and the second conduction type is further described.Firstly, attached drawing 6 is please referred to, in institute
It states 2 side wall of groove and does the first injection, in the present embodiment, the injection ion of first injection is phosphonium ion, described
The injection region 3 of the first conduction type is formed in 2 side wall of groove and the substrate area of bottom.Then, attached drawing 7 is please referred to, described
Deposited oxide in groove 2 is etched back to the oxide to certain thickness, with shape until the oxide fills up the groove 2
At dielectric layer 4 described in first layer.Then, attached drawing 8 is please referred to, is exposure mask with dielectric layer 4 described in first layer, in 2 side of groove
Wall does second injection for the first time, and the injection ion of second injection is boron ion for the first time, and implantation concentration is higher than institute
State the implantation concentration of the first injection, therefore can be by 2 side wall of groove leaks out cruelly at this time region transoid at the second conductive-type
Type.Then, attached drawing 9 is please referred to, dielectric layer 4 described in the second layer are re-formed on the dielectric layer 4 described in the first layer of formation.Then,
Attached drawing 10 is please referred to, is exposure mask with the first layer of formation and second layer dielectric layer 4, does second described the in the trenched side-wall
Two injections, the injection ion of second injection is phosphonium ion for the second time, when implantation concentration is higher than the second injection for the first time is done
Implantation concentration, therefore can be by region transoid that the trenched side-wall leaks out cruelly at this time at the first conduction type.Then, please join
Attached drawing 11 is read, dielectric layer 4 described in third layer are re-formed on the dielectric layer 4 described in the second layer of formation.Finally, please referring to attached drawing
12, dielectric layer 4 described in the first layer, the second layer and third layer using formation does third time institute in 2 side wall of groove as exposure mask
State the second injection, the injection ion of third time second injection is boron ion, and implantation concentration, which is higher than, to be done second described the
Implantation concentration when two injections, therefore the region transoid that 2 side wall of groove can be leaked out cruelly at this time is at the second conduction type,
And then three series connection and the identical diode in direction are respectively formed in the corresponding injection region 3 of two side walls of the groove 2.
In order to guarantee the pressure-resistant performance of device, in the present embodiment, the ion implanting agent that the first time second injects
Twice of preferably described first injection of amount, in the case where N is not 1, the ion note of described second to n-th the second injection
Enter twice that dosage is preferably its preceding one time second injection, in the present embodiment, first implantation dosage is 1E15-3E15
Between.The thickness of the dielectric layer 4 formed every time in the present embodiment may be the same or different, in order to guarantee the resistance to of device
Performance is pressed, the thickness of the dielectric layer 4 is identical.The thickness of the dielectric layer 4 formed every time is by subsequent by the second injection institute
The junction depth of the injection sub-district 32 of the injection sub-district 31 and the second conduction type of the first conduction type formed determines, according to device
Resistance to pressure request determine, be seldom limited herein.
Attached drawing 14 and attached drawing 15 are please referred to, step S04 is executed: forming side wall 52 on 2 side wall of groove；Specifically,
Further, the forming step of the side wall 52 includes: to form oxide layer in 1 surface of substrate and trenched side-wall and bottom
51；It does the technique that is etched back to of the oxide layer 51, removes the oxide layer 51 of 1 surface of substrate and the channel bottom, described in formation
Side wall 52.The side wall 52 is sub for realizing the first electrode 61 and the injection of the first conduction type of 2 side wall of groove
Isolation between area 31 and the injection sub-district 32 of the second conduction type, to the etching of the oxide layer 51 can for dry etching or
Wet etching, in the present embodiment, preferably dry etching, the etch rate of dry etching is more more uniform than wet etching,
Meanwhile extremely accurate etching effect can be obtained with strict control process using dry etching.Further, described
The step of oxide layer 51 are formed on 1 surface of substrate and 2 side wall of groove and bottom includes: to do high-temperature oxydation to the injection region 3
Technique forms the oxide layer 51, realizes while forming oxide layer 51 and drives in process to the heat of the injection region 3,
To realize the activation to 3 impurity of injection region, the temperature of the high temperature oxidation process is 1050-1150 DEG C.In this embodiment party
In formula, the material that the oxide layer 51 is is silica, and silica has good insulation blocking effect.
Attached drawing 16 is please referred to, step S05 is executed: forming first electrode 61 and second electrode 62；Wherein, the first electrode
61 are formed in the groove and are electrically connected with the injection sub-district 31 for the first conduction type for being located at 2 bottom of groove, and institute
First electrode 61 is stated between corresponding two side walls 52 of 2 two side walls of groove, the second electrode 62 be located at institute
The injection sub-district 32 for stating the second conduction type at the top of 1 region of substrate of 2 side wall of groove is electrically connected.Specifically, in this embodiment party
In formula, first conduction type is N-type, and second conduction type is p-type, then corresponding, the first electrode 61 is
Cathode, the second electrode 62 are anode.In other embodiments, if first conduction type is p-type, described second is led
Electric type is N-type, corresponding, and the first electrode 61 is anode, and the second electrode 62 is cathode.
Attached drawing 17 is please referred to, in other embodiments, the injection sub-district 31 of first conduction type and the second conduction
The injection sub-district 32 of type can also be formed only in one of side wall 1 region of substrate corresponding with bottom of the groove 2,
Forming method and first conduction type is formed in two side walls 1 region of substrate corresponding with bottom of the groove 2
The method for injecting the injection sub-district 32 of sub-district 31 and the second conduction type is substantially similar, and difference has, and needs described in do
First injection before, on another side wall formed one layer of mask layer 7, and it is subsequent do the second injection when retain the mask layer always
7, which is also used as the side wall 52 of subsequent corresponding side wall, therefore, when being subsequently formed the side wall 52, it is only necessary to
Be not formed the mask layer 7 side wall formed side wall 52, according to the method formed first injection sub-district 31 with it is described
The quantity of second injection sub-district 32 is identical.
Please refer to attached drawing 2, a kind of Transient Voltage Suppressor, comprising: the substrate 1 with a groove 2；It is formed in the groove
The injection sub-district 31 of multiple alternate first conduction types in 1 region of 2 side walls and the substrate of bottom and the note of the second conduction type
Enter sub-district 32, wherein what is formed in corresponding 1 region of substrate in 2 bottom of groove is the injection sub-district of the first conduction type
31, what is formed in the top in corresponding 1 region of substrate of the trenched side-wall is the injection sub-district 32 of the second conduction type；It is formed
Side wall 52 on 2 side wall of groove；First electrode 61, the first electrode 61 are formed in the groove 2 and are located at institute
The injection sub-district 31 for stating the first conduction type of 2 bottom of groove is electrically connected；And second electrode 62, the second electrode 62 be located at
The injection sub-district 32 of second conduction type of 1 upper surface of substrate is electrically connected.
It is appreciated that by forming the groove 2 and being formed in 1 region of substrate of 2 side wall of groove and bottom
The mode of the injection sub-district 32 of the injection sub-district 31 and the second conduction type of multiple alternate first conduction types, and then form institute
Transient Voltage Suppressor is stated, the protection voltage of Transient Voltage Suppressor is if desired increased, it is only necessary to increase the depth of groove 2, increase
The injection of Doped ions does not need the area for increasing device, while yet convenient device or the layout of circuit.
Further, carrier of the substrate 1 as the Transient Voltage Suppressor, primarily serves the effect of support.?
In present embodiment, the substrate 1 is that material is silicon substrate 1, and silicon is most common, cheap and stable performance semiconductor material
Material, in other embodiments, the material of the substrate 1 can also be silicon substrate, germanium substrate or germanium silicon substrate etc..In this reality
It applies in mode, the substrate 1 is free of Doped ions, and in other embodiments, the substrate 1 can also be mixed for p-type or the light of N-type
Miscellaneous substrate.
Further, the groove 2 is formed in the upper surface of the substrate 1, specifically, forming the process of the groove 2
It can be with are as follows: form etching barrier layer (not shown) over the substrate, photoresist layer is then formed on etching barrier layer, and (figure is not
Show), the photoresist layer is exposed using the mask plate with 2 figure of groove later, then develops, is had
There is the photoresist layer of 2 figure of groove.Using the photoresist layer with 2 figure of groove as exposure mask, carved using reactive ion
The lithographic methods such as erosion method, etching forms the figure opening (not shown) of the groove 2 on etching barrier layer.Then with institute
The etching barrier layer for stating 2 figure of groove opening is exposure mask, using the methods of wet etching or dry etching, removes the resistance that is not etched
1 region of the substrate of barrier covering, and then the groove 2 is formed in the substrate 1, the width of the groove 2 usually exists
Between 1-2um.Hereafter the methods of chemical cleaning removal photoresist layer and etching barrier layer can be used.In above process, it is
Guarantee exposure accuracy, can also form anti-reflecting layer between photoresist layer and etching barrier layer.
Attached drawing 13 is arrived referring once again to attached drawing 6, in the present embodiment, the multiple injection sub-district includes the of N+1
One injection sub-district 31 and N number of second injection sub-district 32, the first injection sub-district 31 are the injection of first conduction type
Sub-district 31, the second injection sub-district 32 are the injection sub-district 32 of second conduction type, and N is positive odd number；More specifically,
The step of forming the first injection sub-district 31 of the N+1 and N number of second injection sub-district 32 includes: to do the in 2 side wall of groove
One injection, to form the injection region 3 of the first conduction type in 1 region of substrate of 2 side wall of groove and bottom；In the note
Enter to do the injection of n times second in area 3, and forms one layer of dielectric layer in 2 bottom of groove before doing second injection each time
4, the second injection gradually forms the note of multiple first conduction types to accumulate the dielectric layer 4 formed as mask every time
Enter the injection sub-district 32 of sub-district 31 and the second conduction type, wherein do for the first time second inject when ionic conduction type with do
The ionic conduction type of first injection is opposite and ion implantation dosage is higher than the described first ion implantation dosage injected, with
The 3 region transoid of injection region that 2 side wall of groove is exposed is at the second conduction type；In the case where N is not 1, second is done
Ion concentration when secondary the second injection to n-th successively increases and relative to the second injection for the first time is done with previous the
Two injection conduction types on the contrary, with the conduction type transoid in 3 region of injection region for respectively exposing 2 side wall of groove at
It is opposite with after first one time second injection, wherein first injection is inclination injection with second injection；Remove the ditch
N layer dielectric layer 4 in slot 2.It is appreciated that by repeating second injection multiple friendships can be formed in the injection region 3
For the injection sub-district 31 of concatenated first conduction type and the injection sub-district 32 of the second conduction type, and then in the injection region 3
It is interior to form multiple concatenated diodes, if desired increase the protection voltage of Transient Voltage Suppressor, it is only necessary to increase the groove 2
Depth increases the number of second injection, while not needing additionally to increase the area of device, also convenient device or electricity
The layout on road.More specifically, the injection ion of first injection is phosphonium ion, in other embodiments, first note
The injection ion entered can be also other pentavalent ions such as arsenic or antimony.Do for the first time it is described second injection injection ion be boron from
Son can be also in other embodiments other trivalent ions such as indium, gallium；It is envisioned that if doing second described the
Two injection, inject ion conduction type and for the first time it is described second injection on the contrary, its inject ion can be phosphonium ion,
It can also be other pentavalent ions such as arsenic or antimony, then doing the conduction type of third time the second injection ion and doing second
The conduction type of the second injection ion is opposite and identical as the ionic conduction type of second injection for the first time, so anti-
It is multiple, until the breakdown voltage of multiple concatenated diodes of formation is met the requirements.It should be noted that doing second note
The number entered must be positive odd number, so that the injection sub-district of the first conduction type formed in 1 region of substrate of 2 bottom of the groove
31 at the top of 1 region of substrate of 2 side wall of groove interior formation be the second conduction type injection sub-district 32, so as to subsequent
The formation of electrode.
Further, include: the step of dielectric layer 4 are formed on 2 bottom of groove on 1 surface of substrate and
Deposited oxide in the groove 2；The oxide is etched back to certain thickness, to form the dielectric layer 4, the oxide
It can be silica, aluminium oxide or silica and the combination of aluminium oxide etc., can be dry etching to the etching of the oxide
Or wet etching, in the present embodiment, preferably dry etching, the etch rate of dry etching are more equal than wet etching
It is even, meanwhile, using dry etching extremely accurate etching effect can be obtained with strict control process.
In order to guarantee the pressure-resistant performance of device, in the present embodiment, the ion implanting agent that the first time second injects
Twice of preferably described first injection of amount, in the case where N is not 1, the ion note of described second to n-th the second injection
Enter twice that dosage is preferably its preceding one time second injection, in the present embodiment, first implantation dosage is 1E15-3E15
Between.The thickness of the dielectric layer 4 formed every time in the present embodiment may be the same or different, in order to guarantee the resistance to of device
Performance is pressed, the thickness of the dielectric layer 4 is identical.The thickness of the dielectric layer 4 formed every time is by subsequent by the second injection institute
The junction depth of the injection sub-district 32 of the injection sub-district 31 or the second conduction type of the first conduction type formed determines, according to device
Resistance to pressure request determine, be seldom limited herein.
Referring once again to attached drawing 14 and attached drawing 15, further, the forming step of the side wall 52 includes: in the substrate
Oxide layer 51 is formed on surface and trenched side-wall and bottom；The technique that is etched back to of the oxide layer 51 is done, 1 surface of substrate and institute are removed
The oxide layer 51 for stating channel bottom forms the side wall 52.The side wall 52 is for realizing the first electrode 61 and the ditch
Isolation between the injection sub-district 31 of first conduction type and the injection sub-district 32 of the second conduction type of 2 side wall of slot, it is right
The etching of the oxide layer 51 can be dry etching or wet etching, in the present embodiment, preferably dry etching, dry method
The etch rate of etching is more more uniform than wet etching, meanwhile, using dry etching pole can be obtained with strict control process
Its accurate etching effect.Further, the oxide layer 51 is formed on 1 surface of substrate and 2 side wall of groove and bottom
Step includes: to do high temperature oxidation process to the injection region 3, forms the oxide layer 51, is forming the same of the oxide layer 51
Shi Shixian drives in process to the heat of the injection region 3, to realize the activation to 3 impurity of injection region, the high temperature oxygen chemical industry
The temperature of skill is 1050-1150 DEG C.In the present embodiment, the material that the oxide layer 51 is is silica, silica
With good insulation blocking effect.
Referring once again to attached drawing 16, further, first electrode 61 and second electrode 62 are formed；Wherein, first electricity
Pole 61 is formed in the groove and is electrically connected with the injection sub-district 31 for the first conduction type for being located at 2 bottom of groove, and
The first electrode 61 between corresponding two side walls 52 of 2 two side walls of groove, the second electrode 62 be located at
The injection sub-district 32 of the second conduction type at the top of 1 region of substrate of 2 side wall of groove is electrically connected.Specifically, in this implementation
In mode, first conduction type is N-type, and second conduction type is p-type, then corresponding, the first electrode 61
For cathode, the second electrode 62 is anode.In other embodiments, if first conduction type be p-type, described second
Conduction type is N-type, corresponding, and the first electrode 61 is anode, and the second electrode 62 is cathode.
Referring once again to attached drawing 17, in other embodiments, the injection sub-district 31 of the multiple first conduction type and
The injection sub-district 32 of second conduction type can also be formed only in one of side wall substrate 1 corresponding with bottom of the groove 2
In region, forming method and described first is formed in two side walls 1 region of substrate corresponding with bottom of the groove 2 lead
The method of the injection sub-district 32 of the injection sub-district 31 and the second conduction type of electric type is substantially similar, and difference has, and needs
Do it is described first injection before, on another side wall formed one layer of mask layer 7, and it is subsequent do the second injection when retain always
The mask layer 7, the mask layer 7 are also used as the side wall 52 of subsequent corresponding side wall, therefore, are subsequently formed the side wall 52
When, it is only necessary to the side wall 52 is formed in the side wall that the mask layer 7 is not formed, the first injection formed according to the method
Sub-district 31 is identical as the second injection quantity of sub-district 32.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of production method of Transient Voltage Suppressor, which is characterized in that the described method includes:
Substrate is provided；
Groove is formed over the substrate；
Multiple first conduction types and the second conduction type are alternatively formed in the substrate area of the trenched side-wall and bottom
Inject sub-district, wherein what is formed in the corresponding substrate area of the channel bottom is the injection sub-district of the first conduction type,
What is formed in the corresponding substrate top region of the trenched side-wall is the injection sub-district of the second conduction type；
Side wall is formed on the trenched side-wall；
Form first electrode and second electrode；Wherein, the first electrode is formed in the groove and is located at the trench bottom
The injection sub-district of first conduction type in portion is electrically connected, the second electrode and the substrate top region for being located at the trenched side-wall
The second conduction type injection sub-district electrical connection.
2. the method according to claim 1, wherein the multiple injection sub-district includes N+1 first injection
Area and N number of second injection sub-district, the first injection sub-district are the injection sub-district of first conduction type, second injection
Sub-district is the injection sub-district of the second conduction type, wherein N is positive odd number.
3. according to the method described in claim 2, it is characterized in that, forming the N+1 first injection sub-district and N number of second note
The step of entering sub-district include:
The first injection is done in the trenched side-wall, to form the first conductive-type in the substrate area of the trenched side-wall and bottom
The injection region of type；
The injection of n times second is done in the injection region, and is formed before doing second injection each time in the channel bottom
One layer of dielectric layer, the second injection gradually forms the multiple injection sub-district to accumulate the dielectric layer formed as mask every time,
Wherein, do the second ionic conduction type when injecting for the first time with do described first inject ionic conduction type is opposite and ion
Implantation dosage is higher than the ion implantation dosage of first injection, the injection region transoid that the trenched side-wall is exposed
At the second conduction type；In the case where N is not 1, second to the second of n-th ion concentration when injecting is done relative to doing
Second injection for the first time successively increases and the conduction type with previous second injection is on the contrary, with respectively by the channel side
It is opposite after conduction type transoid Cheng Yuqian mono- time second injection of the injection region that wall exposes；
Remove the dielectric layer in the groove.
4. the method according to claim 1, wherein the packet the step of channel bottom forms the dielectric layer
It includes:
The deposited oxide in the substrate surface and the groove；
The oxide is etched back to certain thickness, to form the dielectric layer.
5. according to the method described in claim 2, it is characterized in that, the ion implantation dosage of the injection of the first time second is institute
Twice for stating the first injection, in the case where N is not 1, the ion implantation dosage difference of described second to n-th the second injection
It is twice of its preceding one time second injection.
6. the method according to claim 1, wherein the forming step of the side wall includes:
Oxide layer is formed in the substrate surface and trenched side-wall and bottom；
The technique that is etched back to of the oxide layer is done, the oxide layer of substrate surface and the channel bottom is removed, forms the side wall.
7. according to the method described in claim 6, it is characterized in that, the process for forming the oxide layer includes:
High temperature oxidation process is done to the injection region, forms the oxide layer, is realized while forming the oxide layer to institute
The heat for stating injection region drives in process.
8. a kind of Transient Voltage Suppressor characterized by comprising
Substrate with a groove；
It is formed in multiple alternate first conduction types and the second conduction type of the substrate area of the trenched side-wall and bottom
Injection sub-district, wherein what is formed in the corresponding substrate area of the channel bottom is the injection sub-district of the first conduction type,
What is formed in the top of the corresponding substrate area of the trenched side-wall is the injection sub-district of the second conduction type；
The side wall being formed on the trenched side-wall；
First electrode, the first electrode are formed in the note in the groove with the first conduction type for being located at the channel bottom
Enter sub-district electrical connection；And
Second electrode, the second electrode are electrically connected with the injection sub-district for the second conduction type for being located at the upper surface of substrate.
9. Transient Voltage Suppressor according to claim 8, which is characterized in that the multiple injection sub-district includes N+1
First injection sub-district and N number of second injection sub-district, the first injection sub-district are the injection sub-district of first conduction type, institute
State the injection sub-district electricity that the second injection sub-district is the second conduction type, wherein N is positive odd number；Form the N+1 first injection
Sub-district and it is N number of second injection sub-district the step of include:
The first injection is done in the trenched side-wall, to form the first conductive-type in the substrate area of the trenched side-wall and bottom
The injection region of type；
The injection of n times second is done in the injection region, and is formed before doing second injection each time in the channel bottom
One layer of dielectric layer, the second injection gradually forms the multiple injection sub-district to accumulate the dielectric layer formed as mask every time,
Wherein, do the second ionic conduction type when injecting for the first time with do described first inject ionic conduction type is opposite and ion
Implantation dosage is higher than the ion implantation dosage of first injection, the injection region transoid that the trenched side-wall is exposed
At the second conduction type；In the case where N is not 1, second to the second of n-th ion concentration when injecting is done relative to doing
Second injection for the first time successively increases and the conduction type with previous second injection is on the contrary, with respectively by the channel side
It is opposite after conduction type transoid Cheng Yuqian mono- time second injection of the injection region that wall exposes；
Remove the dielectric layer in the groove.
10. Transient Voltage Suppressor according to claim 9, which is characterized in that the ion that the first time second injects
Implantation dosage is twice of first injection, in the case where N is not 1, the ion of described second to n-th the second injection
Implantation dosage is respectively twice of its preceding one time second injection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810891020.0A CN109037351A (en) | 2018-08-07 | 2018-08-07 | A kind of Transient Voltage Suppressor and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810891020.0A CN109037351A (en) | 2018-08-07 | 2018-08-07 | A kind of Transient Voltage Suppressor and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109037351A true CN109037351A (en) | 2018-12-18 |
Family
ID=64649259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810891020.0A Withdrawn CN109037351A (en) | 2018-08-07 | 2018-08-07 | A kind of Transient Voltage Suppressor and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109037351A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368170A (en) * | 1991-06-14 | 1992-12-21 | Nissan Motor Co Ltd | Semiconductor protection circuit |
| US20020105051A1 (en) * | 2000-05-31 | 2002-08-08 | Bertin Claude L. | Structures and methods of anti-fuse formation in SOI |
| JP2007317683A (en) * | 2006-05-23 | 2007-12-06 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
| CN104253050A (en) * | 2014-04-10 | 2014-12-31 | 电子科技大学 | Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device |
| US20150262996A1 (en) * | 2014-03-11 | 2015-09-17 | Realtek Semiconductor Corporation | Semiconductor device and method of manufacturing same |
| CN106298510A (en) * | 2015-06-05 | 2017-01-04 | 北大方正集团有限公司 | Groove-shaped packet routing device and manufacture method thereof |
| CN206742245U (en) * | 2017-03-20 | 2017-12-12 | 苏州矽航半导体有限公司 | A kind of TVS diode of bi-directional symmetrical |
-
2018
- 2018-08-07 CN CN201810891020.0A patent/CN109037351A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04368170A (en) * | 1991-06-14 | 1992-12-21 | Nissan Motor Co Ltd | Semiconductor protection circuit |
| US20020105051A1 (en) * | 2000-05-31 | 2002-08-08 | Bertin Claude L. | Structures and methods of anti-fuse formation in SOI |
| JP2007317683A (en) * | 2006-05-23 | 2007-12-06 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
| US20150262996A1 (en) * | 2014-03-11 | 2015-09-17 | Realtek Semiconductor Corporation | Semiconductor device and method of manufacturing same |
| CN104253050A (en) * | 2014-04-10 | 2014-12-31 | 电子科技大学 | Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device |
| CN106298510A (en) * | 2015-06-05 | 2017-01-04 | 北大方正集团有限公司 | Groove-shaped packet routing device and manufacture method thereof |
| CN206742245U (en) * | 2017-03-20 | 2017-12-12 | 苏州矽航半导体有限公司 | A kind of TVS diode of bi-directional symmetrical |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9508811B2 (en) | Semi-floating-gate device and its manufacturing method | |
| TWI528458B (en) | Semiconductor device and manufacturing method thereof | |
| CN102867846B (en) | Semiconductor device | |
| CN109037204B (en) | Power device and manufacturing method thereof | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN108336152A (en) | Groove-shaped silicon carbide SBD device with floating junction and its manufacturing method | |
| CN113035714A (en) | Groove type power device and manufacturing method thereof | |
| CN102496573B (en) | Manufacturing method of trench IGBT | |
| KR20180104236A (en) | Method of Manufacturing Power Semiconductor Device | |
| CN102496568B (en) | Method for manufacturing trench power device structure | |
| CN114141621A (en) | Carrier storage groove gate bipolar transistor with split gate and preparation method thereof | |
| CN117995881A (en) | Terminal structure and manufacturing process | |
| CN109244069B (en) | Transient voltage suppressor and preparation method thereof | |
| CN104821334B (en) | N-type LDMOS device and process | |
| CN213601874U (en) | MOSFET device | |
| CN102779750A (en) | Manufacturing method of trench insulated gate bipolar transistor (TIGBT) | |
| CN109065533B (en) | Semiconductor device and manufacturing method thereof | |
| CN109037351A (en) | A kind of Transient Voltage Suppressor and preparation method thereof | |
| CN211017088U (en) | ESD integrated VDMOS device | |
| CN112530867B (en) | Trench type field effect transistor structure and preparation method thereof | |
| CN209016063U (en) | IGBT device | |
| CN113937098A (en) | Electrostatic protection chip for rapid charging management system and preparation method thereof | |
| KR20180032771A (en) | Schottky barrier diode and method of manufacturing the schottky barrier diode | |
| CN103187292B (en) | A kind of method manufacturing trench semiconductor power device | |
| CN109037205A (en) | Transient Voltage Suppressor and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181218 |
|
| WW01 | Invention patent application withdrawn after publication |