CN104253050A - Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device - Google Patents

Manufacturing method of groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device Download PDF

Info

Publication number
CN104253050A
CN104253050A CN201410143064.7A CN201410143064A CN104253050A CN 104253050 A CN104253050 A CN 104253050A CN 201410143064 A CN201410143064 A CN 201410143064A CN 104253050 A CN104253050 A CN 104253050A
Authority
CN
China
Prior art keywords
layer
conduction type
semiconductor
groove
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410143064.7A
Other languages
Chinese (zh)
Other versions
CN104253050B (en
Inventor
罗小蓉
李鹏程
田瑞超
石先龙
范远航
周坤
魏杰
杨超
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201410143064.7A priority Critical patent/CN104253050B/en
Publication of CN104253050A publication Critical patent/CN104253050A/en
Application granted granted Critical
Publication of CN104253050B publication Critical patent/CN104253050B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

The invention relates to a manufacturing method of a groove type transverse MOSFET (metal oxide semiconductor field effect transistor) device, and belongs to the technical field of power semiconductor device manufacturing. According to the method, through key process steps including deep groove etching, insulation dielectric layer formation through thermal growth, semiconductor layer deposition, semiconductor layer planarization, angled ion implantation, high-temperature pushing knotting, insulation medium deposition, insulation medium planarization, final active region and electrode formation and the like, the process manufacturing of the groove type transverse semiconductor device is realized. The process provided by the invention has the following advantages that 1, two kinds of narrow high-concentration P post regions or N post regions which are in different doping types and extend to the bottom of a medium groove can be formed at two side walls of the groove, the voltage-resistant performance of the device is favorably improved, the conduction resistance is reduced, and the transverse size of the device is reduced; 2, the complicated mask is not needed, and the process cost is reduced; 3, the influence of the medium groove filling planarization on a body region, a body contact region, a source region and a drain region is avoided.

Description

A kind of manufacture method of grooved lateral MOSFET device
Technical field
The invention belongs to power semiconductor manufacturing technology field, relate to MOSFET (Metal Oxide Semiconductor field effect transistor, metal-oxide semiconductor fieldeffect transistor) device, especially the manufacture method of LDMOD (Lateral Double-diffusion Metal Oxide Semiconductor field effect transistor, lateral double diffused metal-Oxide-Semiconductor Field effect transistor) device.
Background technology
Power MOSFET is many electronic conductions type device, and its key parameter is withstand voltage and conduction resistance.The raising that it is withstand voltage requires the increase of drift region length and the reduction of drift doping concentration.But drift region concentration reduces, and can cause the increase of conducting resistance; Drift region length increases, and both increases conducting resistance, and also increases the area of device, thus conduction resistance increases.In traditional power MOSFET, conduction resistance R on, sp(conduction resistance=conducting resistance × device area) is according to the relational expression R with withstand voltage BV on, sp∝ BV 2.5sharply increase.Above deficiency limits the application of power MOSFET in high voltage integrated circuit, the application especially in the circuit requiring low-loss and little chip area.
In order to reduce the size of power device, and improve its performance, groove structure is introduced in power device, forms slot type power device.Slot type power device is the important component part of Power Electronic Circuit, and when cut-off state, puncture voltage is high, leakage current is little; When conducting state, conduction resistance is little.Adopt groove structure significantly can shorten lateral device dimensions, reduce the chip area shared by device.To sum up, slot type power device has become the power device of main flow.
Commonly use the processing steps such as extension, deposit, diffusion and ion implantation in semiconductor processing.Wherein, epitaxy technique can control the thickness of generated semiconductor layer accurately, and what extension generated is single-crystal semiconductor layer.Deposit is low for technological requirement, and cost is low, and due to deposit temperature required lower, therefore deposition speed is comparatively fast usually used in generating thicker semiconductor layer.Spread low for technological requirement, cost is low.Ion implantation can accurately controlled doping content and penetration depth, and the uniformity of doping is also better.In addition ion implantation have produce single ionic bundle, adopt low temperature process, the ion of injection can pass film and without advantages such as solid solubility limits.Angle-tilt ion is injected and is had unique advantage for groove wall doping: can be formed in groove two side two kinds of different doping types, narrow and high concentration extend to P post region bottom media slot or N post district.
Summary of the invention
The present invention, in conjunction with several processing steps commonly used in existing semiconductor technology, proposes a kind of manufacture method of grooved lateral MOSFET device.
The present invention realizes by adopting following technical proposals;
A manufacture method for grooved lateral MOSFET device, comprises the following steps:
Step 1: material prepares.Prepare SOI material (as shown in Figure 1a) or body silicon materials (as shown in Figure 1 b), described SOI material comprises substrate layer 1, dielectric buried layer 2 and active layer 3, wherein dielectric buried layer 2 is between substrate layer 1 and active layer 3, the conduction type of substrate layer 1 is not limit, and the conduction type of active layer 3 is the first conduction type; Described body silicon materials comprise substrate layer 1 and active layer 2, and wherein the conduction type of substrate layer 1 is the second conduction type, and the conduction type of active layer 3 is the first conduction type.
Step 2: the SOI material adopting thermal oxidation technology to prepare in step 1 or the active layer 3 superficial growth layer of oxide layer 41 of body silicon materials, then at oxide layer 41 surface deposition Si 3n 4layer 42, smears photoresist 43 and carries out photoetching (as shown in Figure 2);
Step 3: by step 2 gained photoetching window, first etch Si 3n 4layer 42 and oxide layer 41, be then etched with active layer 3 to set depth, form the first groove, then remove photoresist (as shown in Figure 3);
Step 4: adopt thermal oxidation technology in step 3 gained first trench wall growth layer of oxide layer as buffer layer 4 (as shown in Figure 4);
Step 5: the polycrystalline silicon material of deposit first conduction type in the first groove after forming buffer layer 4, and ensure that the polycrystalline silicon material of the first conduction type is full of the first groove (as shown in Figure 5);
Step 6: with Si 3n 4layer 42 carries out planarization (as shown in Figure 6) as the polycrystalline silicon material of etch stop layer to the first conduction type of step 5 deposit;
Step 7: etch the polycrystalline silicon material of the first conduction type to set depth in the setting width of distance the first trenched side-wall, form the semiconductor-assisted layer 5b (as shown in Figure 7) of the first conduction type at buffer layer 4 along flute wall surfaces;
Step 8: adopt angle-tilt ion to inject also knot to the side of the semiconductor-assisted layer 5b of the first conduction type and form the semiconductor-assisted layer 5a (as shown in Figure 8) of the second conduction type;
Step 9: fill dielectric 6 in the first groove after the semiconductor-assisted layer 5b of formation first conduction type and the semiconductor-assisted layer 5a of the second conduction type, and ensure that dielectric 6 is full of the first groove (as shown in Figure 9);
Step 10: planarization is carried out to the dielectric 6 that step 9 is filled, and removes Si 3n 4layer 42 and oxide layer 41, finally make dielectric 6 surface flush (as shown in Figure 10) with active layer 3 surface;
Step 11: inject the second conductive type impurity at active layer 3 intermediate ion of the semiconductor-assisted layer 5a side near the second conduction type, and knot forms the second conductivity type body region 7 (as shown in figure 11);
Step 12: near side ion implantation first conductive type impurity of buffer layer 4 in the second conductivity type body region 7, and knot forms the first conduction type heavy doping source region 9a; Inject the first conductive type impurity at active layer 3 intermediate ion of the semiconductor-assisted layer 5b side near the first conduction type, and knot forms the first conduction type heavy doping drain region 9b simultaneously; And inject the first conductive type impurity at the semiconductor-assisted layer 5b surface ion of the first conduction type, and knot forms the first cut-off region, conduction type heavy doping field 11 (as shown in figure 12);
Step 13: side ion implantation second conductive type impurity of the first conduction type heavy doping source region 9a in the second conductivity type body region 7, and knot forms the second conduction type heavy doping body contact zone 8; Inject the second conductive type impurity at the semiconductor-assisted layer 5a surface ion of the second conduction type, and knot forms the second conduction type grid end ohmic contact regions 10a (as shown in figure 13) simultaneously;
Step 14: each electrode preparation and surface passivation technology, form complete device (as shown in figure 14); After device completes, the exit of the first conduction type heavy doping source region 9a and the second conduction type heavy doping body contact zone 8 all connects with metal source S-phase, the exit of the first conduction type heavy doping drain region 9b is connected with metal-drain D, and the exit of the second conduction type grid end ohmic contact regions 10a is connected with metal gates G.
Further, the buffer layer 4 that step 4 is formed in step 3 gained first trench wall growth oxide layer can be silicon dioxide or the dielectric coefficient dielectric higher than silicon dioxide, and critical breakdown electric field is greater than 30V/ μm.
Further, angle-tilt ion described in step 8 is injected and is referred to that the direction of ion implantation and active layer 3 surface normal angular separation are 0 ~ 30 degree, and concrete angle depends on the depth-to-width ratio of the first groove; First groove depth-to-width ratio is larger, and angle-tilt ion implant angle is less; The impurity that angle-tilt ion injects the second conduction type should select the impurity that diffusion coefficient is little, to control transverse width and the CONCENTRATION DISTRIBUTION of the second conduction type semiconductor-assisted layer 5a.
Further, when step 9 fills dielectric 6 in the first groove, the medium that the mode due to deposit grows is fine and close not as good as the medium of heat growth, can select high temperature density, in the first groove, dielectric is thicker, need to adopt the mode of repeatedly deposit to fill; The dielectric 6 filled is silicon dioxide or the dielectric coefficient dielectric lower than silicon dioxide, and critical breakdown electric field is greater than 30V/ μm.
Further, the specific operation process of step 10 is: first adopt chemical-mechanical planarization to remove the dielectric 6 at top, until expose Si 3n 4layer 42, then adopts SPA to remove Si 3n 4layer 42, then uses hydrofluoric acid rinse to remove oxide layer 41, flushes with active layer 3 surface to make dielectric 6 surface.
The grooved lateral MOSFET device adopting process of the present invention to be formed has following advantage.
The first, the present invention can be formed in media slot two side two kinds of different doping types, narrow and high concentration extend to P post region bottom media slot or N post district, be conducive to improving the withstand voltage of device, reduce conducting resistance and reduction of device lateral dimension; The second, do not need complicated mask, reduce process costs; 3rd, avoid the impact that media slot filling and planarization produce tagma, body contact zone and source region and drain region.Device application prepared by this method significantly can alleviate the contradictory relation between withstand voltage and conduction resistance on MOS control device.
Accompanying drawing explanation
The generalized section of Fig. 1 a, SOI material.
The generalized section of Fig. 1 b, body silicon materials.
Fig. 2, form oxide layer and Si in active layer surface 3n 4masking layer and smear photoresist carry out photoetching after generalized section.
Fig. 3, longitudinally etching, form the generalized section of the first groove.
Fig. 4, form the generalized section of buffer layer at the first trench wall.
Fig. 5, on buffer layer the generalized section of the polysilicon layer of deposit first conduction type.
The generalized section after planarization is carried out on Fig. 6, polysilicon layer surface.
Fig. 7, polysilicon layer longitudinally etch the generalized section of formation first conduction type semiconductor-assisted layer.
Fig. 8, angle-tilt ion are injected also knot and are formed the generalized section of the second conduction type semiconductor-assisted layer.
Fig. 9, in the first groove, fill the generalized section of dielectric.
Figure 10, to dielectric surface carry out the generalized section after planarization.
Figure 11, ion implantation form tagma, and the generalized section of knot.
Figure 12, ion implantation knot form source region, the generalized section of the cut-off region, field of drain region and the first conduction type.
Figure 13, ion implantation the generalized section of knot organizator contact zone and grid end ohmic contact regions.
The preparation of Figure 14, each electrode and surface passivation technology, form the generalized section (normal work needs external diode) of complete device.
Figure 15, top longitudinally etching in the first conduction type side of semiconductor-assisted layer, form the generalized section of the second groove.
Figure 16, ion implantation form source region, drain region and form the generalized section of cut-off region, field of the first conduction type at the second groove.
Figure 17, the generalized section of drain terminal contact zone formed after planarization to the second trench fill second conductive type semiconductor layer.
Figure 18, ion implantation the generalized section of knot organizator contact zone and grid end ohmic contact regions.
The preparation of Figure 19, each electrode and surface passivation technology, form the generalized section (can independently normally work) of complete device.
Reference numeral:
1 is substrate layer; 2 is dielectric buried layers; 3 is active layers; 3a is N-type drift region; 4 is buffer layers; 5a is the second conduction type semiconductor-assisted layer; 5b is the first conduction type semiconductor-assisted layer; 6 is media slot; 7 is second conductivity type body region; 8 is second conduction type heavy doping body contact zones; 9a is the first conduction type heavy doping source region; 9b is the first conduction type heavy doping drain region; 10a is the second conduction type grid end ohmic contact regions; 10b is the second conduction type drain terminal contact zone; 11 is first cut-off regions, conduction type heavy doping field; 41 is the oxide layers on active layer 3 surface; 42 is the Si on oxide layer 41 surface 3n 4masking layer; D1 is diode; S is metal source; D is metal-drain; G is metal gates.
Embodiment
Embodiment 1
As a kind of better embodiment of the present invention, the invention discloses a kind of novel having has the N channel laterally slot type power MOS FET of the semiconductor-assisted layer of two kinds of different conduction-types manufacture method outside deep trouth and groove, specifically comprise the steps:
Step 1: material prepares.Prepare SOI material (as shown in Figure 1a) or body silicon materials (as shown in Figure 1 b), described SOI material comprises substrate layer 1, dielectric buried layer 2 and active layer 3, wherein dielectric buried layer 2 is between substrate layer 1 and active layer 3, the conduction type of substrate layer 1 is not limit, and the conduction type of active layer 3 is the first conduction type; Described body silicon materials comprise substrate layer 1 and active layer 2, and wherein the conduction type of substrate layer 1 is the second conduction type, and the conduction type of active layer 3 is the first conduction type.
Step 2: the SOI material adopting thermal oxidation technology to prepare in step 1 or the active layer 3 superficial growth layer of oxide layer 41 of body silicon materials, then at oxide layer 41 surface deposition Si 3n 4layer 42, smears photoresist 43 and carries out photoetching (as shown in Figure 2);
Step 3: by step 2 gained photoetching window, first etch Si 3n 4layer 42 and oxide layer 41, be then etched with active layer 3 to set depth, form the first groove, then remove photoresist (as shown in Figure 3);
Step 4: adopt thermal oxidation technology in step 3 gained first trench wall growth layer of oxide layer as buffer layer 4 (as shown in Figure 4);
Step 5: the polycrystalline silicon material of deposit first conduction type in the first groove after forming buffer layer 4, and ensure that the polycrystalline silicon material of the first conduction type is full of the first groove (as shown in Figure 5);
Step 6: with Si 3n 4layer 42 carries out planarization (as shown in Figure 6) as the polycrystalline silicon material of etch stop layer to the first conduction type of step 5 deposit;
Step 7: etch the polycrystalline silicon material of the first conduction type to set depth in the setting width of distance the first trenched side-wall, form the semiconductor-assisted layer 5b (as shown in Figure 7) of the first conduction type at buffer layer 4 along flute wall surfaces;
Step 8: adopt angle-tilt ion to inject also knot to the side of the semiconductor-assisted layer 5b of the first conduction type and form the semiconductor-assisted layer 5a (as shown in Figure 8) of the second conduction type;
Step 9: fill dielectric 6 in the first groove after the semiconductor-assisted layer 5b of formation first conduction type and the semiconductor-assisted layer 5a of the second conduction type, and ensure that dielectric 6 is full of the first groove (as shown in Figure 9);
Step 10: planarization is carried out to the dielectric 6 that step 9 is filled, and removes Si 3n 4layer 42 and oxide layer 41, finally make dielectric 6 surface flush (as shown in Figure 10) with active layer 3 surface;
Step 11: inject the second conductive type impurity at active layer 3 intermediate ion of the semiconductor-assisted layer 5a side near the second conduction type, and knot forms the second conductivity type body region 7 (as shown in figure 11);
Step 12: near side ion implantation first conductive type impurity of buffer layer 4 in the second conductivity type body region 7, and knot forms the first conduction type heavy doping source region 9a; Inject the first conductive type impurity at active layer 3 intermediate ion of the semiconductor-assisted layer 5b side near the first conduction type, and knot forms the first conduction type heavy doping drain region 9b simultaneously; And inject the first conductive type impurity at the semiconductor-assisted layer 5b surface ion of the first conduction type, and knot forms the first cut-off region, conduction type heavy doping field 11 (as shown in figure 12);
Step 13: side ion implantation second conductive type impurity of the first conduction type heavy doping source region 9a in the second conductivity type body region 7, and knot forms the second conduction type heavy doping body contact zone 8; Inject the second conductive type impurity at the semiconductor-assisted layer 5a surface ion of the second conduction type, and knot forms the second conduction type grid end ohmic contact regions 10a (as shown in figure 13) simultaneously;
Step 14: each electrode preparation and surface passivation technology, form complete device (as shown in figure 14); After device completes, the exit of the first conduction type heavy doping source region 9a and the second conduction type heavy doping body contact zone 8 all connects with metal source S-phase, the exit of the first conduction type heavy doping drain region 9b is connected with metal-drain D, and the exit of the second conduction type grid end ohmic contact regions 10a is connected with metal gates G.
As shown in figure 14, the grooved lateral MOSFET device technique that the present embodiment manufactures is simple, and do not need complicated mask, cost is low.But the proper device operation be made up of embodiment 1 needs external diode d1.
Embodiment 2
This example proposes a kind of novel manufacture method with the N channel laterally slot type power MOS FET of the semiconductor-assisted layer outside deep trouth and groove with two kinds of different conduction-types not needing external circuits just can normally work.This example specifically also needs to increase following processing step compared with embodiment 1:
(1) described in embodiment 1, increase steps A between step 11 and step 12: in active layer 3 superficial growth layer of oxide layer, smear photoresist, semiconductor-assisted layer 5b that the first conduction type is exposed in photoetching, then the semiconductor-assisted layer 5b etching the first conduction type until set depth, to form the second groove (as shown in figure 15);
(2) step B is being increased between step 12 and step 13 described in embodiment 1: in steps A gained second groove, fill P type semiconductor, and planarization is carried out to its surface and removes oxide layer, make its surface flush to form the second conduction type drain terminal contact zone 10b (as shown in figure 17) with active layer 3 surface.
Compared with embodiment 1, embodiment 2 adds 2 step process, makes device be integrated with external diode, does not need external diode just can normally work.

Claims (6)

1. a manufacture method for grooved lateral MOSFET device, comprises the following steps:
Step 1: material prepares; Prepare SOI material or body silicon materials, described SOI material comprises substrate layer (1), dielectric buried layer (2) and active layer (3), wherein dielectric buried layer (2) is positioned between substrate layer (1) and active layer (3), the conduction type of substrate layer (1) is not limit, and the conduction type of active layer (3) is the first conduction type; Described body silicon materials comprise substrate layer (1) and active layer (2), and wherein the conduction type of substrate layer (1) is the second conduction type, and the conduction type of active layer (3) is the first conduction type;
Step 2: the SOI material adopting thermal oxidation technology to prepare in step 1 or active layer (3) the superficial growth layer of oxide layer (41) of body silicon materials, then at oxide layer (41) surface deposition Si 3n 4layer (42), smears photoresist (43) and carries out photoetching;
Step 3: by step 2 gained photoetching window, first etch Si 3n 4layer (42) and oxide layer (41), be then etched with active layer (3) to set depth, form the first groove, then remove photoresist;
Step 4: adopt thermal oxidation technology in step 3 gained first trench wall growth layer of oxide layer as buffer layer (4);
Step 5: the polycrystalline silicon material of deposit first conduction type in the first groove after forming buffer layer (4), and ensure that the polycrystalline silicon material of the first conduction type is full of the first groove;
Step 6: with Si 3n 4layer (42) carries out planarization as the polycrystalline silicon material of etch stop layer to the first conduction type of step 5 deposit;
Step 7: etch the polycrystalline silicon material of the first conduction type to set depth in the setting width of distance the first trenched side-wall, form the semiconductor-assisted layer (5b) of the first conduction type at buffer layer (4) along flute wall surfaces;
Step 8: adopt angle-tilt ion to inject also knot to the side of the semiconductor-assisted layer (5b) of the first conduction type and form the semiconductor-assisted layer (5a) of the second conduction type;
Step 9: fill dielectric (6) in the first groove after the semiconductor-assisted layer (5b) of formation first conduction type and the semiconductor-assisted layer (5a) of the second conduction type, and ensure that dielectric (6) is full of the first groove;
Step 10: planarization is carried out to the dielectric (6) that step 9 is filled, and removes Si 3n 4layer (42) and oxide layer (41), finally make dielectric (6) surface flush with active layer (3) surface;
Step 11: inject the second conductive type impurity at active layer (3) intermediate ion of semiconductor-assisted layer (5a) side near the second conduction type, and knot forms the second conductivity type body region (7);
Step 12: near side ion implantation first conductive type impurity of buffer layer (4) in the second conductivity type body region (7), and knot forms the first conduction type heavy doping source region (9a); Inject the first conductive type impurity at active layer (3) intermediate ion of semiconductor-assisted layer (5b) side near the first conduction type, and knot forms the first conduction type heavy doping drain region (9b) simultaneously; And inject the first conductive type impurity at semiconductor-assisted layer (5b) surface ion of the first conduction type, and knot forms the first cut-off region, conduction type heavy doping field (11);
Step 13: side ion implantation second conductive type impurity in the first conduction type heavy doping source region (9a) in the second conductivity type body region (7), and knot forms the second conduction type heavy doping body contact zone (8); Inject the second conductive type impurity at semiconductor-assisted layer (5a) surface ion of the second conduction type, and knot forms the second conduction type grid end ohmic contact regions (10a) simultaneously;
Step 14: each electrode preparation and surface passivation technology, form complete device; After device completes, first conduction type heavy doping source region (9a) is all connected with metal source (S) with the exit of the second conduction type heavy doping body contact zone (8), the exit in the first conduction type heavy doping drain region (9b) is connected with metal-drain (D), and the exit of the second conduction type grid end ohmic contact regions (10a) is connected with metal gates (G).
2. the manufacture method of grooved lateral MOSFET device according to claim 1, it is characterized in that, between step 11 and step 12, increase steps A: in active layer (3) superficial growth layer of oxide layer, smear photoresist, semiconductor-assisted layer (5b) that the first conduction type is exposed in photoetching, then the semiconductor-assisted layer (5b) etching the first conduction type to set depth, to form the second groove; Step B is increased: in steps A gained second groove, fill P type semiconductor between step 12 and step 13, and planarization is carried out to its surface and removes oxide layer, make its surface flush to form the second conduction type drain terminal contact zone (10b) with active layer 3 surface.
3. the manufacture method of grooved lateral MOSFET device according to claim 1 and 2, it is characterized in that, the buffer layer (4) that step 4 is formed in step 3 gained first trench wall growth oxide layer is for silicon dioxide or dielectric coefficient are higher than the dielectric of silicon dioxide, and critical breakdown electric field is greater than 30V/ μm.
4. the manufacture method of grooved lateral MOSFET device according to claim 1 and 2, it is characterized in that, angle-tilt ion described in step 8 is injected and is referred to that the direction of ion implantation and active layer (3) surface normal angular separation are 0 ~ 30 degree, and concrete angle depends on the depth-to-width ratio of the first groove; First groove depth-to-width ratio is larger, and angle-tilt ion implant angle is less; The impurity that angle-tilt ion injects the second conduction type should select the impurity that diffusion coefficient is little, to control transverse width and the CONCENTRATION DISTRIBUTION of the second conduction type semiconductor-assisted layer (5a).
5. the manufacture method of grooved lateral MOSFET device according to claim 1 and 2, it is characterized in that, when step 9 fills dielectric (6) in the first groove, the medium grown due to the mode of deposit is fine and close not as good as the medium of heat growth, high temperature density can be selected, in the first groove, dielectric is thicker, need to adopt the mode of repeatedly deposit to fill; The dielectric (6) filled is for silicon dioxide or dielectric coefficient are lower than the dielectric of silicon dioxide, and critical breakdown electric field is greater than 30V/ μm.
6. the manufacture method of grooved lateral MOSFET device according to claim 1 and 2, is characterized in that, the specific operation process of step 10 is: first adopt chemical-mechanical planarization to remove the dielectric (6) at top, until expose Si 3n 4layer (42), then adopts SPA to remove Si 3n 4layer (42), then uses hydrofluoric acid rinse to remove oxide layer (41), flushes with active layer (3) surface to make dielectric (6) surface.
CN201410143064.7A 2014-04-10 2014-04-10 A kind of manufacture method of grooved lateral MOSFET device Active CN104253050B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410143064.7A CN104253050B (en) 2014-04-10 2014-04-10 A kind of manufacture method of grooved lateral MOSFET device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410143064.7A CN104253050B (en) 2014-04-10 2014-04-10 A kind of manufacture method of grooved lateral MOSFET device

Publications (2)

Publication Number Publication Date
CN104253050A true CN104253050A (en) 2014-12-31
CN104253050B CN104253050B (en) 2016-12-21

Family

ID=52187844

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410143064.7A Active CN104253050B (en) 2014-04-10 2014-04-10 A kind of manufacture method of grooved lateral MOSFET device

Country Status (1)

Country Link
CN (1) CN104253050B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105161420A (en) * 2015-07-13 2015-12-16 电子科技大学 Method of manufacturing transverse MOSFET device
CN105826195A (en) * 2015-01-07 2016-08-03 北大方正集团有限公司 Super junction power device and manufacturing method thereof
CN109037351A (en) * 2018-08-07 2018-12-18 深圳市南硕明泰科技有限公司 A kind of Transient Voltage Suppressor and preparation method thereof
CN110828561A (en) * 2018-08-08 2020-02-21 英飞凌科技奥地利有限公司 Si layer for oxygen insertion to reduce contact implant out-diffusion in vertical power devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257047A (en) * 2008-04-03 2008-09-03 北京大学 High pressure resistant lateral direction bilateral diffusion MOS transistor
CN102832237B (en) * 2012-07-03 2015-04-01 电子科技大学 Trough-type semiconductor power device
CN103050540B (en) * 2012-12-20 2016-03-30 电子科技大学 Use the lateral power of the low conduction resistance of high-dielectric constant groove structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105826195A (en) * 2015-01-07 2016-08-03 北大方正集团有限公司 Super junction power device and manufacturing method thereof
CN105826195B (en) * 2015-01-07 2018-12-04 北大方正集团有限公司 A kind of super junction power device and preparation method thereof
CN105161420A (en) * 2015-07-13 2015-12-16 电子科技大学 Method of manufacturing transverse MOSFET device
CN105161420B (en) * 2015-07-13 2017-10-13 电子科技大学 A kind of manufacture method of lateral MOSFET device
CN109037351A (en) * 2018-08-07 2018-12-18 深圳市南硕明泰科技有限公司 A kind of Transient Voltage Suppressor and preparation method thereof
CN110828561A (en) * 2018-08-08 2020-02-21 英飞凌科技奥地利有限公司 Si layer for oxygen insertion to reduce contact implant out-diffusion in vertical power devices
CN110828561B (en) * 2018-08-08 2021-09-28 英飞凌科技奥地利有限公司 Si layer for oxygen insertion to reduce contact implant out-diffusion in vertical power devices

Also Published As

Publication number Publication date
CN104253050B (en) 2016-12-21

Similar Documents

Publication Publication Date Title
CN105448979B (en) Horizontal dual pervasion field effect pipe and forming method thereof
CN107316899B (en) Semi-super junction device and manufacturing method thereof
TW201306255A (en) Semiconductor device with enhanced mobility and method
CN104716177B (en) A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage
CN104937720A (en) Semiconductor device and method for manufacturing same
CN101872724A (en) Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)
CN103178093B (en) The structure of high-voltage junction field-effect transistor and preparation method
CN106409676A (en) Semiconductor structure and manufacturing method thereof
CN104253050B (en) A kind of manufacture method of grooved lateral MOSFET device
CN103311272B (en) There is the (Silicon-on-insulator) MOSFET lateral of dielectric isolation groove
CN106356401A (en) Field limiting ring terminal structure for power semiconductor device
CN113659009A (en) Power semiconductor device with internal anisotropic doping and manufacturing method thereof
CN102945799B (en) Method for manufacturing longitudinal power semiconductor device
CN102376533A (en) Method and device for manufacturing alternately arranged P-type and N-type semiconductor thin layer structure
CN111370464A (en) Trench gate power device and manufacturing method thereof
CN106601795B (en) A kind of trench field effect transistor and its manufacturing method
CN112951715B (en) Groove gate structure and preparation method of groove type field effect transistor structure
CN103779416B (en) The power MOSFET device of a kind of low VF and manufacture method thereof
CN103545350B (en) A kind of manufacture method of transverse high-voltage device drift region
TWI524524B (en) Manufacturing method and structure of power semiconductor device
CN104064596B (en) NLDMOS device and manufacture method thereof
CN103871881B (en) The groove and preparation method of p-type LDMOS device
CN112309853A (en) Preparation method of shielded gate trench structure
KR101063567B1 (en) Mos device and the manufacturing method thereof
CN106206742B (en) High-voltage MOSFET (Metal-oxide-semiconductor field Effect transistor) with super junction P area in staggered arrangement and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant