CN111370464A - Trench gate power device and manufacturing method thereof - Google Patents

Trench gate power device and manufacturing method thereof Download PDF

Info

Publication number
CN111370464A
CN111370464A CN201811601026.6A CN201811601026A CN111370464A CN 111370464 A CN111370464 A CN 111370464A CN 201811601026 A CN201811601026 A CN 201811601026A CN 111370464 A CN111370464 A CN 111370464A
Authority
CN
China
Prior art keywords
region
gate
trench
layer
power device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811601026.6A
Other languages
Chinese (zh)
Inventor
李东升
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Sanrise Tech Co ltd
Original Assignee
Shenzhen Sanrise Tech Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Sanrise Tech Co ltd filed Critical Shenzhen Sanrise Tech Co ltd
Priority to CN201811601026.6A priority Critical patent/CN111370464A/en
Publication of CN111370464A publication Critical patent/CN111370464A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a trench gate power device.A current carrier storage layer and a channel region in a front structure are both formed by adopting epitaxial layers, a well region formed by a well injection process and a push well is not used as the channel region, and an ion injection and push well are used for forming the current carrier storage layer, so that the influence of the push well process on the impurity concentration distribution and the thickness of the current carrier storage layer and the channel region can be eliminated, and the current carrier storage layer and the channel region can both have a structure capable of accurately controlling the impurity concentration distribution and the thickness. Therefore, the invention also discloses a manufacturing method of the trench gate power device. The invention can accurately control the doping concentration distribution and the thickness of the channel region and the carrier storage layer at the same time, thereby improving the performance of the device.

Description

Trench gate power device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate power device; the invention also relates to a manufacturing method of the trench gate power device.
Background
The semiconductor power device is a basic electronic component for controlling and converting energy of a power electronic system, and the continuous development of the power electronic technology develops a wide application field for the semiconductor power device. Semiconductor power devices marked by Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are mainstream devices in the field of power electronics nowadays, wherein an IGBT device is a composite device of a voltage-controlled MOSFET and a Bipolar Junction Transistor (BJT).
Structurally, the structure of the IGBT is similar to that of a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS), and only the N + substrate of the VDMOS is replaced by the P + substrate, and the introduced conductance modulation effect overcomes the contradiction between the inherent on-resistance and breakdown voltage of the VDMOS, so that the IGBT has the common advantages of a bipolar power transistor and a MOSFET at the same time: high input impedance, low input drive power, low on-state voltage, high current capacity, high switching speed, etc. Due to the unique and irreplaceable performance advantages of IGBTs, their self-propelled utility products find wide application in many areas, such as: solar power generation, wind power generation, motor cars, high-speed rails, new energy automobiles and numerous energy conversion fields.
In order to further reduce the conduction voltage drop of the IGBT, the gate structure of the IGBT is optimized from a planar gate structure to a trench gate structure, and the trench gate IGBT changes the channel from the transverse direction to the longitudinal direction, so that the influence of a JFET (junction field effect transistor) in the conduction resistance is eliminated. Meanwhile, the size of the primitive cell, namely stepping (pitch), is reduced, the density of the primitive cell is greatly improved, the total width of a channel of each chip is increased, and the resistance of the channel is reduced. On the other hand, the area of the polysilicon gate is increased, so that the distributed resistance is reduced, and the switching speed is favorably improved.
In order to further reduce the conduction voltage drop of the IGBT, the grid structure of the unit structure of the IGBT is optimized from a plane grid structure to a groove grid structure. The trench gate IGBT changes the channel from the transverse direction to the longitudinal direction, and eliminates the influence of a JFET in the on-resistance. Meanwhile, the size of the unit cell is reduced, the density of the unit cell is greatly improved, the total width of a channel of each chip is increased, and the resistance of the channel is reduced. On the other hand, the area of the polysilicon gate is increased, so that the distributed resistance is reduced, and the switching speed is favorably improved.
In order to reduce saturation voltage drop (Vcesat) and turn-off loss of the IGBT, for an N-type device, a Carrier Stored (CS) layer is generally required to be formed below a P-type well (Pwell) of a cell structure, a CS layer is generally formed by injection and push-in junction, i.e., push-in well, a forming process is generally performed before or after the Pwell process, Pwell is generally used as a channel region, and in the prior art, Pwell itself is also formed by an injection and push-in well process, and due to the influence of a thermal process in the forming process of Pwell and CS layers, concentration distribution and thickness of the carrier stored layer are difficult to be accurately controlled, and distribution of Pwell is influenced; namely: the forming process of the Cs layer is not easy to control the impurity distribution and the thickness, and meanwhile, the thermal process of the forming process of the Cs layer can also influence the impurity distribution of the Pwell; the formation process of Pwell also affects the formation of the Cs layer.
Disclosure of Invention
The invention aims to provide a trench gate power device, which can accurately control the doping concentration distribution and the thickness of a channel region and a current carrier storage layer simultaneously, thereby improving the performance of the device. Therefore, the invention also provides a manufacturing method of the trench gate power device.
In order to solve the above technical problem, the front structure of the trench gate power device provided by the present invention includes:
the drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirements of the drift region.
And the second epitaxial layer is formed on the surface of the first epitaxial layer, has the first conductive type doping, has the doping concentration higher than that of the first epitaxial layer, and is used as a current carrier storage layer of the trench gate power device.
And the third epitaxial layer is formed on the surface of the second epitaxial layer, has second conductive type doping, and is used as a channel region of the trench gate power device.
The carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
The groove gate comprises a gate groove, a gate dielectric layer and a polysilicon gate, the gate groove penetrates through the channel region and the carrier storage layer, the gate dielectric layer is formed on the side surface and the bottom surface of the gate groove, the polysilicon gate is filled in the gate groove formed with the gate dielectric layer, and the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel.
And the source region consists of a first conduction type heavily doped region formed on the surface of the channel region.
The interlayer film, the contact hole, the source electrode and the grid electrode are formed by patterning the front metal layer.
The contact hole penetrates the interlayer film.
The source region is connected to the source electrode through the contact hole corresponding to the top.
The polysilicon gate is connected to the gate through the corresponding contact hole at the top.
The further improvement is that the trench gate power device is a trench gate IGBT, and comprises the following back structure:
and a collector region consisting of a second conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate.
And a collector composed of a back metal layer is formed on the back of the collector region.
The further improvement is that the trench gate power device is a trench gate MOSFET, and comprises the following back structure:
and a drain region consisting of a first conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate.
And a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
In a further improvement, the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers.
The gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
In a further improvement, the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
In a further improvement, the doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
In a further improvement, the back structure of the trench gate power device further includes:
and the field stop layer is doped with the first conduction type and is formed between the drift region and the collector region.
In a further improvement, the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom.
And a well contact region formed by a second conductive type heavily doped region is further formed on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, and the well contact region and the contact hole corresponding to the top form ohmic contact.
In order to solve the above technical problem, in the manufacturing method of the trench gate power device provided by the present invention, the step of forming the front structure of the trench gate power device includes:
the method comprises the following steps of firstly, forming a first epitaxial layer with first conductivity type doping on the surface of a semiconductor substrate by adopting an epitaxial growth process, wherein a drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirements of the drift region.
And secondly, forming a second epitaxial layer on the surface of the first epitaxial layer by adopting an epitaxial growth process, wherein the second epitaxial layer has the first conductive type doping, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the second epitaxial layer is used as a current carrier storage layer of the trench gate power device.
Forming a third epitaxial layer on the surface of the second epitaxial layer by adopting an epitaxial growth process, wherein the third epitaxial layer has second conductive type doping and is used as a channel region of the trench gate power device;
the carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
Step four, forming a trench gate, comprising the following sub-steps:
and 41, forming a grid groove by adopting a photoetching process, wherein the grid groove penetrates through the channel region and the current carrier storage layer.
And 42, forming a gate dielectric layer on the side surface and the bottom surface of the gate groove.
And 43, filling polycrystalline silicon into the grid groove formed with the grid dielectric layer to form a polycrystalline silicon grid, wherein the surface of the channel region covered by the side surface of the polycrystalline silicon grid is used for forming a channel.
And fifthly, forming a source region on the surface of the channel region between the trench gates in a self-alignment manner by adopting a first conductive type heavy doping ion implantation process.
And step six, forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode.
The contact hole penetrates the interlayer film.
The source region is connected to the source electrode through the contact hole corresponding to the top.
The polysilicon gate is connected to the gate through the corresponding contact hole at the top.
The further improvement is that the trench gate power device is a trench gate IGBT, and the method comprises the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate.
And step eight, forming a collector region consisting of a second conductive type heavily doped region on the back of the thinned semiconductor substrate.
And step nine, forming a back metal layer on the back of the collector region and forming a collector by the back metal layer.
In a further improvement, the trench gate power device is a trench gate MOSFET, and the method comprises the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate.
And step eight, forming a drain region consisting of the first conductive type heavily doped region on the back surface of the thinned semiconductor substrate.
And step nine, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
In a further improvement, the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers.
The gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
In a further improvement, the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
The doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
In a further improvement, the back structure of the trench gate power device further includes:
and forming a field stop layer doped with the first conductivity type by adopting a back ion implantation process, wherein the field stop layer is positioned between the drift region and the collector region.
Alternatively, the field stop layer is formed on the surface of the semiconductor substrate by an epitaxial process before being formed on the first epitaxial layer.
In a further improvement, the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom.
After the opening of the contact hole is formed and before metal filling, forming a well contact region formed by a second conduction type heavily doped region on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, wherein the well contact region and the contact hole corresponding to the top form ohmic contact.
The technical scheme of the invention is specially designed according to the technical problem of the invention, and the invention breaks through the conventional thinking mode that the forming process of the well region and the carrier storage layer corresponding to the channel region of the trench gate power device in the prior art adopts injection plus push well, but adopts the epitaxial layer which can accurately control the doping concentration, the doping concentration distribution and the thickness as the corresponding channel region and the carrier storage layer, so the invention can prevent the influence of the thermal process in the structure formed by injecting the carrier storage layer or the channel region into plus push well on the doping concentration distribution and the thickness of the carrier storage layer and the channel region, thereby realizing the accurate control of the impurity concentration distribution and the thickness of the carrier storage layer and the channel region, and improving the performance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a trench gate power device according to a second embodiment of the present invention;
fig. 3A-3F are schematic structural diagrams of devices in steps of a method according to a first embodiment of the present invention.
Detailed Description
The trench gate power device of the first embodiment of the present invention:
as shown in fig. 1, which is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention, a front structure of the trench gate power device according to the first embodiment of the present invention includes:
the semiconductor device comprises a first epitaxial layer 2 formed on the surface of a semiconductor substrate 1, wherein the first epitaxial layer 2 has doping of a first conductivity type, a drift region is formed by the first epitaxial layer 2, and the doping concentration of the first epitaxial layer 2 is set according to the requirement of the drift region.
The second epitaxial layer 3 is formed on the surface of the first epitaxial layer 2, the second epitaxial layer 3 has a first conductivity type doping, the doping concentration of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2, and the second epitaxial layer 3 serves as a carrier storage layer 3 of the trench gate power device.
And a third epitaxial layer 4 formed on the surface of the second epitaxial layer 3, wherein the third epitaxial layer 4 has a second conductivity type doping, and the third epitaxial layer 4 is used as a channel region 4 of the trench gate power device.
The carrier storage layer 3 and the channel region 4 both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer 3 or the channel region 4 on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4 can be prevented, so that the carrier storage layer 3 and the channel region 4 both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
The trench gate comprises a gate trench 5, a gate dielectric layer 6 and a polysilicon gate 7, wherein the gate trench 5 penetrates through the channel region 4 and the carrier storage layer 3, the gate dielectric layer 6 is formed on the side surface and the bottom surface of the gate trench 5, the polysilicon gate 7 is filled in the gate trench 5 formed with the gate dielectric layer 6, and the surface of the channel region 4 covered by the side surface of the polysilicon gate 7 is used for forming a channel.
And the source region 8 consists of a first conduction type heavily doped region formed on the surface of the channel region 4.
The interlayer film 9, the contact hole 10, the source electrode and the gate electrode formed by patterning the front metal layer 12.
The contact hole 10 passes through the interlayer film 9.
The source region 8 is connected to the source electrode through the corresponding contact hole 10 at the top.
The polysilicon gate 7 is connected to the gate through the corresponding contact hole 10 at the top.
In a first embodiment of the present invention, the trench gate power device is a trench gate IGBT, and includes the following back structure:
a collector region 13a composed of a heavily doped region of the second conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
A collector composed of a back metal layer 14 is formed on the back surface of the collector region 13 a.
In the first embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the first epitaxial layer 2, the second epitaxial layer 3, and the third epitaxial layer 4 are all silicon epitaxial layers.
The gate dielectric layer 6 is a gate oxide layer and is formed by adopting a thermal oxidation process.
The doping concentration of the carrier storage layer 3 is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
The doping concentration of the channel region 4 is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
Preferably, the back structure of the trench gate power device further includes:
a field stop layer doped with a first conductivity type is formed between the drift region and the collector region 13 a.
The bottom of the contact hole 10 corresponding to the top of the source region 8 also passes through the source region 8 and is connected with the channel region 4 at the bottom. In an IGBT device, the source region 8 is also referred to as an emitter region.
The surface of the channel region 4 at the bottom of the contact hole 10 corresponding to the top of the source region 8 is also formed with a well contact region 11 formed by a second conductive type heavily doped region, and the well contact region 11 and the contact hole 10 corresponding to the top form ohmic contact.
In the first embodiment of the present invention, the trench gate power device is an N-type device, the first conductivity type is an N-type device, and the second conductivity type is a P-type device. In other embodiments can also be: the trench gate power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The technical solution of the first embodiment of the present invention is designed particularly according to the technical problem of the present invention, and the first embodiment of the present invention breaks through the conventional thinking mode that the formation processes of the well region corresponding to the channel region 4 of the trench gate power device and the carrier storage layer 3 in the prior art both adopt the formation of the injection and push well, but instead an epitaxial layer is used as the corresponding channel region 4 and carrier storage layer 3 that allows for precise control of the doping concentration and doping concentration profile and thickness, therefore, the first embodiment of the present invention can prevent the influence of the thermal process in the structure in which the carrier storage layer 3 or the channel region 4 is formed using the injection plus push well on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4, thereby enabling accurate control of the impurity concentration distribution and thickness of the carrier storage layer 3 and the channel region 4, and thus enabling improvement of device performance.
The trench gate power device of the second embodiment of the present invention:
as shown in fig. 2, which is a schematic structural diagram of a trench gate power device according to a second embodiment of the present invention, the difference between the trench gate power device according to the second embodiment of the present invention and the first trench gate power device according to the present invention is:
in a second embodiment of the present invention, the trench gate power device is a trench gate MOSFET, and includes the following back structure:
a drain region 13b composed of a heavily doped region of the first conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
A drain electrode made of a back metal layer 14 is formed on the back surface of the drain region 13 b.
The method of the first embodiment of the invention:
as shown in fig. 3A to fig. 3F, which are schematic structural diagrams of devices in steps of the method according to the first embodiment of the present invention, in the method for manufacturing a trench-gate power device according to the first embodiment of the present invention, the step of forming the front surface structure of the trench-gate power device includes:
step one, as shown in fig. 3A, a first epitaxial layer 2 doped with a first conductivity type is formed on the surface of a semiconductor substrate 1 by using an epitaxial growth process, a drift region is composed of the first epitaxial layer 2, and the doping concentration of the first epitaxial layer 2 is set according to the requirement of the drift region.
In the method according to the first embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate, and the subsequent first epitaxial layer 2, second epitaxial layer 3, and third epitaxial layer 4 are all silicon epitaxial layers.
Step two, as shown in fig. 3A, a second epitaxial layer 3 is formed on the surface of the first epitaxial layer 2 by adopting an epitaxial growth process, the second epitaxial layer 3 has a first conductivity type dopant, the dopant concentration of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2, and the second epitaxial layer 3 serves as a current carrier storage layer 3 of the trench gate power device.
The doping concentration of the carrier storage layer 3 is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
Step three, as shown in fig. 3A, a third epitaxial layer 4 is formed on the surface of the second epitaxial layer 3 by using an epitaxial growth process, the third epitaxial layer 4 has a second conductivity type dopant, and the third epitaxial layer 4 is used as a channel region 4 of the trench gate power device.
The doping concentration of the channel region 4 is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
The carrier storage layer 3 and the channel region 4 both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer 3 or the channel region 4 on the doping concentration distribution and thickness of the carrier storage layer 3 and the channel region 4 can be prevented, so that the carrier storage layer 3 and the channel region 4 both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled.
Step four, forming a trench gate, comprising the following sub-steps:
step 41, as shown in fig. 3B, a gate trench 5 is formed by using a photolithography etching process, and the gate trench 5 penetrates through the channel region 4 and the carrier storage layer 3.
A Hard Mask (HM) is usually used to form the gate trench 5 by etching, the HM is silicon dioxide and has a thickness of
Figure BDA0001922505600000091
The width of the top opening of the gate trench 5 defined by photoetching is 0.3-1.5 micrometers, and the depth of the gate trench 5 is 1.5-7.0 micrometers.
And 42, as shown in fig. 3C, forming a gate dielectric layer 6 on the side surface and the bottom surface of the gate trench 5.
The gate dielectric layer 6 is a gate oxide layer formed by a thermal oxidation process, and the thickness of the gate dielectric layer 6 is
Figure BDA0001922505600000092
The temperature of the thermal oxidation process is 800-1050 ℃.
Step 43, as shown in fig. 3D, filling polysilicon into the gate trench 5 formed with the gate dielectric layer 6 to form a polysilicon gate 7, and forming a channel on the surface of the channel region 4 covered by the side surface of the polysilicon gate 7.
And fifthly, as shown in fig. 3E, forming a source region 8 on the surface of the channel region 4 between the trench gates in a self-alignment manner by adopting a first conductive type heavily doped ion implantation process.
The implanted impurity of the source region 8 is phosphorus or arsenic, and the doping concentration is 1e15cm-3～1e16cm-3. And annealing is carried out after the ion implantation of the source region 8 is finished, wherein the annealing is rapid thermal annealing or furnace tube annealing, and the annealing temperature is 700-950 ℃.
And sixthly, as shown in fig. 3F, forming an interlayer film 9, a contact hole 10 and a front metal layer 12, and patterning the front metal layer 12 to form a source electrode and a gate electrode.
The interlayer film 9 is an oxide layer with a thickness of
Figure BDA0001922505600000093
The contact hole 10 passes through the interlayer film 9.
The source region 8 is connected to the source electrode through the corresponding contact hole 10 at the top.
The polysilicon gate 7 is connected to the gate through the corresponding contact hole 10 at the top.
In the method according to the first embodiment of the present invention, the bottom of the contact hole 10 corresponding to the top of the source region 8 further passes through the source region 8 and is connected to the channel region 4 at the bottom, and the thickness of the contact hole 10 over-etching silicon at the bottom is 0.2 to 0.6 micrometers.
After the opening of the contact hole 10 is formed and before the metal filling, forming a well contact region 11 formed by a second conductive type heavily doped region on the surface of the channel region 4 at the bottom of the contact hole 10 corresponding to the top of the source region 8, wherein the well contact region 11 and the contact hole 10 corresponding to the top form an ohmic contact. The ion implantation impurity of the trap contact region 11 is B or BF2, and the doping concentration is 1e14cm-3～5e15cm-3. And annealing is carried out after the ion implantation of the source region 8 is finished, wherein the annealing is rapid thermal annealing or furnace tube annealing, and the annealing temperature is 700-950 ℃.
The trench gate power device is a trench gate IGBT and comprises the following steps of forming a back structure:
and seventhly, thinning the back of the semiconductor substrate 1.
Step eight, as shown in fig. 1, a collector region 13a composed of a heavily doped region of the second conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
The collector region 13a is typically formed using a back side implant followed by activation using a laser anneal.
In the method according to the first embodiment of the present invention, before forming the collector region 13a in the eighth step, a field stop layer doped with a first conductivity type is formed by using a back ion implantation process, where the field stop layer is located between the drift region and the collector region 13 a. In other embodiments can also be: the field stop layer is formed on the surface of the semiconductor substrate 1 by an epitaxial process before being formed on the first epitaxial layer 2.
Step nine, forming a back metal layer 14 on the back of the collector region 13a and forming a collector by the back metal layer 14.
The method of the second embodiment of the invention:
the difference between the method according to the second embodiment of the present invention and the method according to the first embodiment of the present invention is that the method according to the second embodiment of the present invention comprises the following steps of forming the back structure:
and seventhly, thinning the back of the semiconductor substrate 1.
Step eight, as shown in fig. 2, a drain region 13b composed of a heavily doped region of the first conductivity type is formed on the back surface of the thinned semiconductor substrate 1.
Generally, the semiconductor substrate 1 can be directly provided with a heavy doping of the first conductivity type, so that the drain region 13b can be directly formed after thinning the semiconductor substrate 1. Can also be: the drain region 13b is formed by ion implantation after the semiconductor substrate 1 is thinned.
Step nine, forming a back metal layer 14 on the back of the drain region 13b and forming a drain electrode by the back metal layer 14.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A trench-gate power device, wherein a front structure of the trench-gate power device comprises:
the drift region is composed of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirement of the drift region;
the second epitaxial layer is formed on the surface of the first epitaxial layer and has first conductive type doping, the doping concentration of the second epitaxial layer is larger than that of the first epitaxial layer, and the second epitaxial layer is used as a carrier storage layer of the trench gate power device;
a third epitaxial layer formed on the surface of the second epitaxial layer, wherein the third epitaxial layer has a second conductivity type doping, and the third epitaxial layer is used as a channel region of the trench gate power device;
the carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled;
the groove gate comprises a gate groove, a gate dielectric layer and a polysilicon gate, the gate groove penetrates through the channel region and the carrier storage layer, the gate dielectric layer is formed on the side surface and the bottom surface of the gate groove, the polysilicon gate is filled in the gate groove formed with the gate dielectric layer, and the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel;
the source region consists of a first conduction type heavily doped region formed on the surface of the channel region;
the interlayer film, the contact hole, the source electrode and the grid electrode are formed by patterning the front metal layer;
the contact hole penetrates through the interlayer film;
the source region is connected to the source electrode through the contact hole corresponding to the top;
the polysilicon gate is connected to the gate through the corresponding contact hole at the top.
2. The trench-gate power device of claim 1 wherein: the trench gate power device is a trench gate IGBT and comprises a back structure as follows:
a collector region consisting of a second conductive type heavily doped region is formed on the back surface of the thinned semiconductor substrate;
and a collector composed of a back metal layer is formed on the back of the collector region.
3. The trench-gate power device of claim 1 wherein: the trench gate power device is a trench gate MOSFET and comprises the following back structure:
forming a drain region consisting of a first conductive type heavily doped region on the back surface of the thinned semiconductor substrate;
and a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
4. The trench-gate power device of claim 1 wherein: the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers;
the gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
5. The trench-gate power device of claim 1 wherein: the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5-5 microns.
6. The trench-gate power device of claim 1 wherein: the doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
7. The trench-gate power device of claim 2 wherein: the back structure of the trench gate power device further comprises:
and the field stop layer is doped with the first conduction type and is formed between the drift region and the collector region.
8. The trench-gate power device of claim 1 wherein: the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom;
and a well contact region formed by a second conductive type heavily doped region is further formed on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, and the well contact region and the contact hole corresponding to the top form ohmic contact.
9. A manufacturing method of a trench gate power device is characterized in that the step of forming a front structure of the trench gate power device comprises the following steps:
forming a first epitaxial layer doped with a first conduction type on the surface of a semiconductor substrate by adopting an epitaxial growth process, wherein a drift region consists of the first epitaxial layer, and the doping concentration of the first epitaxial layer is set according to the requirement of the drift region;
forming a second epitaxial layer on the surface of the first epitaxial layer by adopting an epitaxial growth process, wherein the second epitaxial layer has a first conductive type doping, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer, and the second epitaxial layer is used as a current carrier storage layer of the trench gate power device;
forming a third epitaxial layer on the surface of the second epitaxial layer by adopting an epitaxial growth process, wherein the third epitaxial layer has second conductive type doping and is used as a channel region of the trench gate power device;
the carrier storage layer and the channel region both adopt epitaxial layer process structures, and the influence of a thermal process in a structure formed by injecting and pushing wells in the carrier storage layer or the channel region on the doping concentration distribution and thickness of the carrier storage layer and the channel region can be prevented, so that the carrier storage layer and the channel region both have a structure in which the impurity concentration distribution and the thickness can be accurately controlled;
step four, forming a trench gate, comprising the following sub-steps:
step 41, forming a gate trench by adopting a photoetching process, wherein the gate trench penetrates through the channel region and the carrier storage layer;
step 42, forming gate dielectric layers on the side surfaces and the bottom surfaces of the gate trenches;
step 43, filling polysilicon in the gate trench formed with the gate dielectric layer to form a polysilicon gate, wherein the surface of the channel region covered by the side surface of the polysilicon gate is used for forming a channel;
forming a source region on the surface of the channel region between the trench gates in a self-alignment manner by adopting a first conductive type heavily doped ion implantation process;
forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode;
the contact hole penetrates through the interlayer film;
the source region is connected to the source electrode through the contact hole corresponding to the top;
the polysilicon gate is connected to the gate through the corresponding contact hole at the top.
10. The method of manufacturing a trench-gate power device of claim 9, wherein: the trench gate power device is a trench gate IGBT and comprises the following steps of forming a back structure:
seventhly, thinning the back of the semiconductor substrate;
step eight, forming a collector region consisting of a second conductive type heavily doped region on the back of the thinned semiconductor substrate;
and step nine, forming a back metal layer on the back of the collector region and forming a collector by the back metal layer.
11. The method of manufacturing a trench-gate power device of claim 9, wherein: the trench gate power device is a trench gate MOSFET and comprises the following steps of forming a back structure:
seventhly, thinning the back of the semiconductor substrate;
step eight, forming a drain region consisting of a first conductive type heavily doped region on the back of the thinned semiconductor substrate;
and step nine, forming a back metal layer on the back of the drain region and forming a drain electrode by the back metal layer.
12. The method of manufacturing a trench-gate power device of claim 9, wherein: the semiconductor substrate is a silicon substrate, and the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are silicon epitaxial layers;
the gate dielectric layer is a gate oxide layer and is formed by adopting a thermal oxidation process.
13. The method of manufacturing a trench-gate power device of claim 9, wherein: the doping concentration of the carrier storage layer is 5e15cm-3～5e17cm-3The thickness is 0.5 to 5 microns;
the doping concentration of the channel region is 5e16cm-3～5e17cm-3The thickness is 0.5-3 microns.
14. The method of manufacturing a trench-gate power device of claim 10, wherein: the back structure of the trench gate power device further comprises:
forming a field stop layer doped with a first conductive type by adopting a back ion implantation process, wherein the field stop layer is positioned between the drift region and the collector region;
alternatively, the field stop layer is formed on the surface of the semiconductor substrate by an epitaxial process before being formed on the first epitaxial layer.
15. The method of manufacturing a trench-gate power device of claim 9, wherein: the bottom of the contact hole corresponding to the top of the source region also penetrates through the source region and is connected with the channel region at the bottom;
after the opening of the contact hole is formed and before metal filling, forming a well contact region formed by a second conduction type heavily doped region on the surface of the channel region at the bottom of the contact hole corresponding to the top of the source region, wherein the well contact region and the contact hole corresponding to the top form ohmic contact.
CN201811601026.6A 2018-12-26 2018-12-26 Trench gate power device and manufacturing method thereof Pending CN111370464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811601026.6A CN111370464A (en) 2018-12-26 2018-12-26 Trench gate power device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811601026.6A CN111370464A (en) 2018-12-26 2018-12-26 Trench gate power device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN111370464A true CN111370464A (en) 2020-07-03

Family

ID=71211494

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811601026.6A Pending CN111370464A (en) 2018-12-26 2018-12-26 Trench gate power device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111370464A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113903801A (en) * 2021-09-27 2022-01-07 上海华虹宏力半导体制造有限公司 IGBT device and manufacturing method thereof
CN116417507A (en) * 2023-03-31 2023-07-11 瑶芯微电子科技(上海)有限公司 IGBT device structure integrating Schottky contact and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070267663A1 (en) * 2006-05-19 2007-11-22 Mitsubishi Electric Corporation Semiconductor device having improved insulated gate bipolar transistor and method for manufacturing the same
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
CN105280493A (en) * 2015-11-04 2016-01-27 上海道之科技有限公司 Trench IGBT device manufacturing method
CN105679667A (en) * 2016-03-09 2016-06-15 上海道之科技有限公司 Manufacturing method for terminal structure of trench IGBT device
US20170213908A1 (en) * 2014-07-25 2017-07-27 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070267663A1 (en) * 2006-05-19 2007-11-22 Mitsubishi Electric Corporation Semiconductor device having improved insulated gate bipolar transistor and method for manufacturing the same
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
US20170213908A1 (en) * 2014-07-25 2017-07-27 United Silicon Carbide, Inc. Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same
CN105280493A (en) * 2015-11-04 2016-01-27 上海道之科技有限公司 Trench IGBT device manufacturing method
CN105679667A (en) * 2016-03-09 2016-06-15 上海道之科技有限公司 Manufacturing method for terminal structure of trench IGBT device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113903801A (en) * 2021-09-27 2022-01-07 上海华虹宏力半导体制造有限公司 IGBT device and manufacturing method thereof
CN113903801B (en) * 2021-09-27 2023-08-18 上海华虹宏力半导体制造有限公司 IGBT device and manufacturing method thereof
CN116417507A (en) * 2023-03-31 2023-07-11 瑶芯微电子科技(上海)有限公司 IGBT device structure integrating Schottky contact and preparation method thereof
CN116417507B (en) * 2023-03-31 2024-01-12 瑶芯微电子科技(上海)有限公司 IGBT device structure integrating Schottky contact and preparation method thereof

Similar Documents

Publication Publication Date Title
US20200235230A1 (en) Super-junction igbt device and method for manufacturing same
CN105531825A (en) Semiconductor device and semiconductor device manufacturing method
JP2001210822A (en) Barrier storage mode field-effect transistor
CN105185825A (en) Injection Control In Semiconductor Power Devices
CN110504310B (en) RET IGBT with self-bias PMOS and manufacturing method thereof
CN108682624B (en) Manufacturing method of IGBT chip with composite gate
CN107731898B (en) CSTBT device and manufacturing method thereof
CN113838916B (en) Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof
CN113838922A (en) Split-gate super-junction IGBT device structure with carrier concentration enhancement function and method
CN110473914B (en) Preparation method of SiC-MOS device
CN117080269A (en) Silicon carbide MOSFET device and preparation method thereof
CN113838918A (en) Super-junction IGBT device structure with carrier concentration enhancement and manufacturing method
CN103855206A (en) Insulated gate bipolar transistor and manufacturing method thereof
CN113066865B (en) Semiconductor device for reducing switching loss and manufacturing method thereof
CN111370479A (en) Trench gate power device and manufacturing method thereof
CN109065608B (en) Transverse bipolar power semiconductor device and preparation method thereof
CN111370464A (en) Trench gate power device and manufacturing method thereof
CN113782586A (en) Multi-channel super-junction IGBT device
CN104253152A (en) IGBT (insulated gate bipolar transistor) and manufacturing method thereof
CN103117309A (en) Horizontal power device structure and preparation method thereof
US20150144990A1 (en) Power semiconductor device and method of manufacturing the same
CN110504314B (en) Groove-type insulated gate bipolar transistor and preparation method thereof
CN113964197B (en) IGBT device with low leakage current and preparation method thereof
CN106409895A (en) Insulated gate bipolar transistor and manufacturing method thereof
CN110504168B (en) Manufacturing method of multi-groove-grid transverse high-voltage power device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200703