CN116417507A - IGBT device structure integrating Schottky contact and preparation method thereof - Google Patents

IGBT device structure integrating Schottky contact and preparation method thereof Download PDF

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CN116417507A
CN116417507A CN202310342649.0A CN202310342649A CN116417507A CN 116417507 A CN116417507 A CN 116417507A CN 202310342649 A CN202310342649 A CN 202310342649A CN 116417507 A CN116417507 A CN 116417507A
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contact hole
region
igbt device
grid
body region
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CN116417507B (en
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徐涛
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
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    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

In the IGBT device structure, the Schottky contact, namely the Schottky diode, is formed by the contact between the top metal layer and the P body regions with different doping concentrations, and the Schottky diode has higher on-voltage drop, so that the Fermi potential energy of holes can be improved to form a hole barrier, the conductivity modulation of the N-type drift region when the IGBT device is conducted in the forward direction is enhanced, the forward-direction conduction voltage drop of the IGBT device is further reduced, the compromise relation between the forward-direction conduction voltage drop and the turn-off loss of the IGBT device is finally improved, the performance of the IGBT device is improved, and in addition, compared with the process for enhancing carriers by utilizing floating P columns in the prior art, the problem that the extraction speed of the IGBT device to the holes is slow when the IGBT device is turned off is solved to a certain extent, and compared with the process for enhancing the carriers by adding the carrier storage layer, the manufacturing cost of the IGBT device is also reduced.

Description

IGBT device structure integrating Schottky contact and preparation method thereof
Technical Field
The invention relates to the technical field of power semiconductor device preparation, in particular to an IGBT device structure integrating Schottky contact and a preparation method thereof.
Background
The IGBT (Insulated Gate Bipolar Transistor) is a composite full-control voltage-driven power semiconductor device composed of a bipolar triode and an insulated gate field effect transistor, and has the characteristics of low impedance and easy driving of a metal-oxide semiconductor field effect transistor (MOSFET), high current and low conduction voltage drop of a Bipolar Junction Transistor (BJT) and the like, so that the IGBT is widely applied to various fields of automobiles, railways, household appliances, communication and aerospace. The use of IGBTs greatly improves the performance of power electronics systems, but it has been an effort to optimize the trade-off relationship between their on-voltage drop Vce (on) and off-loss Eoff.
In the practical use process of the IGBT, in order to improve the trade-off relationship between the forward conduction voltage drop and the turn-off loss of the IGBT device structure, a carrier enhancement technology is generally used, and the current common carrier enhancement technology includes adding a carrier storage layer or preparing an IGBT structure with a floating P column. However, adding a carrier storage layer can enhance the surface electric field, resulting in reduced device withstand voltage, and a photolithography mask is added, so that the cost is increased, and the preparation of the floating P-pillar can also affect the extraction of holes when the IGBT device is turned off.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an IGBT device structure integrating schottky contact and a method for manufacturing the same, which are used for solving the problem in the prior art how to improve the trade-off relationship between the forward conduction voltage drop and the turn-off loss of the IGBT device without increasing the device withstand voltage, and without affecting the extraction of holes and increasing the cost when the device is turned off.
To achieve the above and other related objects, the present invention provides an IGBT device structure integrating schottky contacts, comprising:
a P+ collector and an N-type buffer layer formed on the P+ collector;
the N-type drift region is arranged on the N-type buffer layer and is far away from the P+ collector electrode;
the P body region is positioned at the top of the N-type drift region, and at least a first contact hole and a second contact hole are formed in the P body region, wherein the doping concentration of the P body region exposed by the first contact hole is larger than that of the P body region of the second contact Kong Xianlou;
the grid structure is arranged in contact with the N-type drift region;
the source region is positioned in the P body region and is electrically isolated from the grid structure, and the depth of the source region is not greater than the depths of the first contact hole and the second contact hole;
and the top metal layer is positioned on the source region and fills the first contact hole and the second contact hole, wherein the top metal layer positioned in the first contact hole is electrically connected with the P body region to form ohmic contact, and the top metal layer positioned in the second contact hole is electrically connected with the P body region to form Schottky contact.
Optionally, the gate structure is a trench gate, and includes a trench, a gate oxide layer formed on an inner surface of the trench, and a gate filled in the trench, where a depth of the trench gate is greater than a depth of the P body region and less than a depth of the N-type drift region.
Optionally, an interlayer dielectric layer is further disposed between the source region and the top metal layer, and the interlayer dielectric layer completely covers the source region and the trench gate.
Optionally, the gate structure is a planar gate, and includes a gate formed on a top surface of the N-type drift region and a gate oxide layer surrounding the gate, and the planar gate is electrically isolated from the P-body region by the gate oxide layer.
Optionally, the width of the first contact hole is not greater than the width of the second contact hole.
Optionally, the top metal layer is one or a combination of titanium, nickel or platinum.
The invention also provides a preparation method of the IGBT device structure integrating the Schottky contact, which comprises the following steps:
providing a semiconductor substrate, and forming an N-type drift region on the front surface of the substrate;
ion implantation is carried out on the front surface of the N-type drift region to form a P body region, the P body region is etched to form a first contact hole and a second contact hole, a grid structure is formed, and the grid structure is in contact arrangement with the N-type drift region;
ion implantation is carried out on the top of the P body region to form a source region, and the depth of the source region is smaller than the depths of the first contact hole and the second contact hole;
performing ion implantation on the P body region exposed in the first contact hole so that the doping concentration of the P body region exposed in the first contact hole is greater than that of the P body region exposed in the second contact hole;
forming a top metal layer above the source region, wherein the top metal layer fills the first contact hole and the second contact hole, is electrically connected with the P body region exposed in the first contact hole to form ohmic contact, and is electrically connected with the P body region exposed in the second contact hole to form Schottky contact;
thinning the back surface of the substrate to expose the N-type drift region, and performing N+ ion implantation on the N-type drift region to form an N-type buffer layer;
p+ ion implantation is carried out on the N-type buffer layer to form a P+ collector, and a metalized collector is formed below the P+ collector.
Optionally, the gate structure is a trench gate, and the forming step of the trench gate is to etch the top of the N-type drift region to form a trench, and form a gate oxide layer on the inner surface of the trench and fill the gate in the trench, where the depth of the trench gate is greater than the depth of the P body region and less than the depth of the N-type drift region.
Optionally, before forming the top metal layer, a step of forming an interlayer dielectric layer is further included, wherein the interlayer dielectric layer is located above the source region and completely covers the source region and the trench gate.
Optionally, the gate structure is a planar gate, and the forming step of the planar gate is to form a gate and a gate oxide layer wrapping the gate on top of the N-type drift region, where the planar gate covers the P-body region and exposes the first contact hole and the second contact hole.
As described above, the integrated schottky contact IGBT device structure and the method for manufacturing the same of the present invention have the following beneficial effects: the Schottky diode is formed by the contact between the top metal layer and the P body region, and the Fermi potential energy of holes can be improved to form a hole barrier due to the fact that the Schottky diode has higher opening voltage drop, so that the conductance modulation of a drift region of an IGBT device in forward conduction is enhanced, the forward conduction voltage drop of the IGBT device is further reduced, the compromise relation between the forward conduction voltage drop and the turn-off loss of the IGBT device is finally improved, the performance of the IGBT device is improved, and in addition, compared with the process for enhancing carriers by using floating P columns in the prior art, the problem that the extraction speed of holes is slow when the IGBT device is turned off is solved to a certain extent, and compared with the process for enhancing carriers by adding a carrier storage layer, the manufacturing cost of the IGBT device is also reduced.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing an IGBT device structure with integrated schottky contacts according to the present invention.
Fig. 2 is a schematic cross-sectional view illustrating the formation of an N-type drift region in the IGBT device structure according to the present invention.
Fig. 3 is a schematic cross-sectional view illustrating the formation of a P body region and a contact via in the IGBT device structure of the invention.
Fig. 4 is a schematic cross-sectional view illustrating the formation of a trench gate in the IGBT device structure of the invention.
Fig. 5 is a schematic cross-sectional view illustrating a planar gate formed in the IGBT device structure according to the present invention.
Fig. 6 is a schematic cross-sectional view showing the formation of a source region in the structure of the IGBT device for forming a trench gate according to the present invention.
Fig. 7 is a schematic cross-sectional view showing the formation of a source region in the IGBT device structure for forming a planar gate according to the present invention.
Fig. 8 is a schematic cross-sectional structure diagram of heavily doping a P body region exposed by a first contact hole in the IGBT device structure according to the present invention.
Fig. 9 is a schematic cross-sectional view of an interlayer dielectric layer formed in the IGBT device structure for forming a trench gate according to the present invention.
Fig. 10 is a schematic diagram showing a cross-sectional structure of forming a top metal layer and a schottky contact in the IGBT device structure for forming a trench gate according to the present invention.
Fig. 11 is a schematic cross-sectional view illustrating formation of a top metal layer and schottky contacts in the IGBT device structure for forming a planar gate according to the present invention.
Fig. 12 is a schematic cross-sectional view showing the formation of an N-type buffer layer in the structure of the IGBT device for forming a trench gate according to the present invention.
Fig. 13 is a schematic cross-sectional view of forming a p+ collector and a metalized collector in the IGBT device structure for forming a trench gate according to the present invention.
Description of element reference numerals
100. A substrate; 101. a P+ collector; 102. an N-type buffer layer; 103. an N-type drift region; 104. a P body region; 1051. a first contact hole; 1052. a second contact hole; 106. a trench gate; 1061. a gate; 1062. a gate oxide layer; 107. a source region; 108. an interlayer dielectric layer; 109. a top metal layer; 110. a Schottky contact; 111. ohmic contact; 112. a planar gate; 1121. a gate; 1122. a gate oxide layer; 113. a metallized collector; S1-S7, and step.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
Please refer to fig. 1 to 13. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, in this embodiment, a method for manufacturing an IGBT device structure integrating schottky contacts is provided, and the method includes the following steps:
s1: providing a semiconductor substrate 100, and forming an N-type drift region 103 on the front surface of the substrate 100;
s2: ion implantation is carried out on the front surface of the N-type drift region to form a P body region, the P body region is etched to form a first contact hole and a second contact hole, a grid structure is formed, and the grid structure is in contact arrangement with the N-type drift region;
s3: ion implantation is performed on top of the P body 104 to form a source region 107, and the depth of the source region 107 is smaller than the depths of the first contact hole 1051 and the second contact hole 1052;
s4: performing ion implantation on the P body 104 exposed in the first contact hole 1051 so that the doping concentration of the P body 104 exposed in the first contact hole 1051 is greater than that of the P body 104 exposed in the second contact hole 1052;
s5: forming a top metal layer 109 over the source region 107, wherein the top metal layer 109 fills the first contact hole 1051 and the second contact hole 1052, is electrically connected with the P body region 104 exposed in the first contact hole 1051 to form an ohmic contact 111, and is electrically connected with the P body region 104 exposed in the second contact hole 1052 to form a schottky contact 110;
s6: thinning the back surface of the substrate 100 to expose the N-type drift region 103, and performing n+ ion implantation on the N-type drift region 103 to form an N-type buffer layer 102;
s7: p+ ion implantation is performed on the N-type buffer layer 102 to form a p+ collector 101, and a metalized collector 113 is formed below the p+ collector 101.
The following describes a preparation method of an IGBT device structure with integrated schottky contact in combination with the accompanying drawings, specifically as follows:
in step S1, referring to fig. 1 and 2, a semiconductor substrate 100 is provided, and an N-type drift region 103 is formed on the front surface of the substrate 100.
By way of example, the semiconductor substrate 100 may be, for example, a silicon substrate 100, and the semiconductor substrate 100 may also include other types, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe), among others. The semiconductor substrate 100 may further include a compound semiconductor and/or an alloy semiconductor, such as gallium nitride, gallium arsenide, or the like. In this embodiment, the semiconductor substrate 100 is an N-type heavily doped silicon carbide substrate and the N-type drift region 103 is formed on the silicon carbide substrate. It should be noted that heavy doping and subsequent light doping are both relative concepts, and specific doping amounts can be adjusted as needed.
In the present embodiment, the N-type drift region 103 is formed over the semiconductor substrate 100 by a multi-layer epitaxial growth process, and the doping concentration type of the N-type drift region 103 is lightly doped.
In step S2, referring to fig. 1 and fig. 3 to 5, ion implantation is performed on the front surface of the N-type drift region 103 to form a P body region 104, and the P body region 104 is etched to form a first contact hole 1051 and a second contact hole 1052, and a gate structure is formed, wherein the gate structure is disposed in contact with the N-type drift region 103.
Specifically, as shown in fig. 3, ion implantation is performed on the front surface of the N-type drift region 103 to form a P body region 104, and specifically, a photoresist masking layer is fabricated on the front surface of the N-type drift region 103, and p+ ion implantation is performed by way of ion implantation, so that P body region 104 is formed by performing push diffusion. In this embodiment, the junction depth of the P body 104 can be controlled by controlling the implantation energy, implantation time, and temperature in the ion implantation process, which are well known to those skilled in the art and will not be described herein.
As shown in fig. 3, in the present embodiment, after forming the P body 104, the P body 104 is etched to form a first contact hole 1051 and a second contact hole 1052 as subsequent metal filling holes. Specifically, a photoresist mask layer (not shown) is formed on top of the P body 104, and etched regions of the first contact hole 1051 and the second contact hole 1052 are reserved, the photoresist mask layer is removed after the first contact hole 1051 and the second contact hole 1052 are formed, and at least one first contact hole 1051 and at least one second contact hole 1052 are formed in the P body 104 through an etching process. Wherein the first contact hole 1051 and the second contact hole 1052 have a depth smaller than the depth of the P body region 104.
As an example, the gate structure is a trench gate 106, and the forming step of the trench gate 106 is to etch the top of the N-type drift region 103 to form a trench, and form a gate oxide layer 1062 on the inner surface of the trench and fill the gate 1061 in the trench, where the depth of the trench gate 106 is greater than the depth of the P body region 104 and less than the depth of the N-type drift region 103.
Specifically, as shown in fig. 4, in this embodiment, after forming the P body 104 and the first contact hole 1051 and the second contact hole 1052, a photoresist masking layer is formed again on top of the P body 104, and a portion of the P body 104 is reserved and etched to form a trench, where the depth of the trench is greater than the depth of the P body 104 and less than the depth of the N-type drift region 103 so as to ensure that the depth of the trench gate 106 formed subsequently is greater than the depth of the P body 104 and less than the depth of the N-type drift region 103.
Further, as shown in fig. 4, a gate oxide layer 1062 is formed on the inner surface of the trench, then the trench is filled with polysilicon to form a gate 1061, and the gate oxide layer 1062 and the gate 1061 together form the trench gate 106, and further, after the gate 1061 is formed, the surface excess polysilicon needs to be removed by a CMP process, so that the gate 1061 is finally level with the top of the P body 104.
As an example, the gate structure is a planar gate 112, including a gate 1121 formed on the top surface of the N-type drift region 103 and a gate oxide layer 1122 surrounding the gate 1121, and the planar gate 112 is electrically isolated from the P-body region 104 by the gate oxide layer 1122.
Specifically, as shown in fig. 5, in another embodiment, after forming the P body region 104 and the first contact hole 1051 and the second contact hole 1052, a planar gate 112 is formed on top of the N-type drift region 103, wherein the planar gate 112 includes a gate 1121 and a gate oxide layer 1122 surrounding the gate 1121, the planar gate 112 is in contact with the N-type drift region 103 and the P body region 104 and is electrically isolated by the gate oxide layer 1122, and the planar gate 112 completely covers the P body region 104 and does not cover the first contact hole 1051 and the second contact hole 1052.
In step S3, referring to fig. 1 and 6, an ion implantation is performed on top of the P body 104 to form a source region 107, and the depth of the source region 107 is not greater than the depths of the first contact hole 1051 and the second contact hole 1052.
As shown in fig. 6, taking the formation of the trench gate 106 as an example, in this embodiment, after the formation of the trench gate 106, ion implantation is continued on top of the P body 104 to form the source region 107. Specifically, a photoresist masking layer is formed again on the surface of the P body region 104 between the trench gates 106, and an implantation region of the source region 107 is reserved, and n+ ion implantation is performed, where the implantation impurity of the n+ source region 107 is typically arsenic. After the implantation is completed, the photoresist masking layer is removed and diffusion is advanced to form source region 107. Wherein the source region 107 is located at both sides of the contact via and is electrically isolated from the adjacent gate electrode 1061 by the gate oxide layer 1062, and the depth of the source region 107 is not greater than the depths of the first contact hole 1051 and the second contact hole 1052.
In another embodiment, as shown in fig. 7, when the gate structure is a planar gate 112, an ion implantation is performed on top of the P body 104 to form the source region 107, then the planar gate 112 is formed on top of the source region 107 and the P body 104, and finally the planar gate 112 completely covers the P body 104 and the source region 107 and does not cover the first contact hole 1051 and the second contact hole 1052.
In step S4, referring to fig. 1 and 8, ion implantation is performed on the P-body 104 exposed in the first contact hole 1051 so that the doping concentration of the P-body 104 exposed in the first contact hole 1051 is greater than that of the P-body 104 exposed in the second contact hole 1052.
As shown in fig. 8, in this embodiment, after the first contact hole 1051 and the second contact hole 1052 are formed, the first contact hole 1051 and the second contact hole 1052 respectively expose the P-body region 104, and further, heavily doped ion implantation is required to be performed on the bottom of the first contact hole 1051, so that the doping concentration of the P-body region 104 exposed by the first contact hole 1051 is greater than that of the P-body region 104 exposed by the second contact hole 1052, so as to ensure that after the metal is filled in the first contact hole 1051, the P-body region 104 can form an ohmic contact 111111 with the metal filled in the first contact hole 1051, thereby reducing the contact resistance, and form a schottky contact 110110 with the metal filled in the second contact hole 1052, so that the forward voltage drop of the device is further reduced, and the reverse recovery current is further reduced.
In step S5, referring to fig. 1 and 10, a top metal layer 109 is formed over the source region 107, and the top metal layer 109 fills the first contact hole 1051 and the second contact hole 1052, and is electrically connected to the P body 104 exposed in the first contact hole 1051 to form an ohmic contact 111, and is electrically connected to the P body 104 exposed in the second contact hole 1052 to form a schottky contact 110.
As an example, steps S1-S7 of forming an interlayer dielectric layer 108 are further included before forming the top metal layer 109, the interlayer dielectric layer 108 is located above the source region 107, and the interlayer dielectric layer 108 completely covers the source region 107 and the trench gate 106.
Specifically, as shown in fig. 9, before forming the top metal layer 109 in this embodiment, an interlayer dielectric layer 108 is formed on top of the N-type drift region 103, where the interlayer dielectric layer 108 completely covers the source region 107 and the trench gate 106 without covering the first contact hole 1051 and the second contact hole 1052, and the interlayer dielectric layer 108 may protect the trench gate 106 from contact with the top metal layer 109 and further protect the source region 107.
By way of example, the top metal layer 109 may be titanium, nickel or platinum or other metal with good electrical conductivity, without limitation.
Specifically, as shown in fig. 10, after forming the interlayer dielectric layer 108, metal is deposited over the interlayer dielectric layer 108 to form the top metal layer 109, where the top metal layer 109 fills the first contact hole 1051 and the second contact hole 1052 to be electrically connected with the P body region 104 and the source region 107, and since the doping concentration of the P body region 104 exposed by the first contact hole 1051 is high, the P body region 104 exposed by the first contact hole 1051 can be electrically connected with the top metal layer 109 in the first contact hole 1051 to form an ohmic contact 111, and the doping concentration of the P body region 104 exposed by the second contact hole 1052 is low, so that the P body region 104 exposed by the second contact hole 1052 can be electrically connected with the top metal layer 109 in the second contact hole 1052 to form a schottky contact 110, and since the width of the first contact hole 1051 is not greater than the width of the second contact hole 1052, the length of the schottky contact 110 is not less than the length of the formed ohmic contact 111, and the forward-switching-on/off voltage drop of the positive-off device is improved by using the high-drop of the schottky diode 103, and the forward-switching-drop positive-hole-drop-off device is improved.
In another embodiment, as shown in fig. 11, when the gate structure is the planar gate 112, the interlayer dielectric layer 108 is not required to be formed, but metal is deposited directly above the planar gate 112 to form the top metal layer 109, wherein the top metal layer 109 fills the first contact hole 1051 and the second contact hole 1052 to electrically connect with the P body region 104 and the source region 107, and the P body region 104 exposed by the first contact hole 1051 is highly doped, so that the P body region 104 exposed by the first contact hole 1051 can be electrically connected with the top metal layer 109 in the first contact hole 1051 to form the ohmic contact 111, and the P body region 104 exposed by the second contact hole 1052 is lightly doped, so that the P body region 104 exposed by the second contact hole 1052 can be electrically connected with the top metal layer 109 in the second contact hole 1052 to form the base contact 110.
In step S6, referring to fig. 1 and 12, the N-type drift region 103 is thinned on the back surface of the substrate 100, and n+ ion implantation is performed on the back surface of the N-type drift region 103 to form the N-type buffer layer 102.
Specifically, as shown in fig. 12, in this embodiment, after forming the schottky contact 110, a thinning process is performed on the back surface of the substrate 100 to expose the back surface of the N-type drift region 103, n+ ion implantation is performed on the back surface of the N-type drift region 103 to form the N-type buffer layer 102, the doping concentration of the N-type buffer layer 102 is greater than that of the N-type drift region 103, and the thickness of the N-type drift region 103 can be reduced by the N-type buffer layer 102, so that the saturation voltage drop of the device can be reduced and the switching time can be shortened.
In step S7, referring to fig. 1 and 13, p+ ion implantation is performed on the N-type buffer layer 102 to form a p+ collector 101, and a metalized collector 113 is formed under the p+ collector 101.
Specifically, as shown in fig. 13, in the present embodiment, p+ ion implantation is performed on the back surface of the N-type buffer layer 102 to form a p+ collector 101, and a metal is deposited on the back surface of the p+ collector 101 to form a metalized collector 113.
Example two
As shown in fig. 13, the present embodiment provides an IGBT device structure including: p+ collector 101 and N-type buffer layer 102 formed on p+ collector 101; an N-type drift region 103, the N-type drift region 103 being disposed on the N-type buffer layer 102 and away from the p+ collector 101; a P body 104, where the P body 104 is located on top of the N-type drift region 103, and at least a first contact hole 1051 and a second contact hole 1052 are formed on the P body 104, and a doping concentration of the P body 104 exposed by the first contact hole 1051 is greater than a doping concentration of the P body 104 exposed by the second contact hole 1052; a gate structure disposed in contact with the N-type drift region 103; a source region 107, the source region 107 being located within the P-body region 104 and being disposed in electrical isolation from the gate structure, and the depth of the source region 107 being no greater than the depths of the first contact hole 1051 and the second contact hole 1052; and a top metal layer 109 located on the source region 107 and filling the first contact hole 1051 and the second contact hole 1052, wherein the top metal layer 109 located in the first contact hole 1051 is electrically connected with the P body region 104 to form an ohmic contact 111, and the top metal layer 109 located in the second contact hole 1052 is electrically connected with the P body region 104 to form a schottky contact 110.
As an example, the gate structure is a trench gate 106, including a trench, a gate oxide layer 1062 formed on the inner surface of the trench, and a gate 1061 filled in the trench, where the depth of the trench gate 106 is greater than the depth of the P body region 104 and less than the depth of the N-type drift region 103.
As an example, an interlayer dielectric layer 108 is further disposed between the source region 107 and the top metal layer 109, and the interlayer dielectric layer 108 completely covers the source region 107 and the trench gate 106.
As an example, the gate structure is a planar gate 112, including a gate 1121 formed on the top surface of the N-type drift region 103 and a gate oxide layer 1122 surrounding the gate 1121, and the planar gate 112 is electrically isolated from the P-body region 104 by the gate oxide layer 1122.
As an example, the width of the first contact hole 1051 is not greater than the width of the second contact hole 1052.
As an example, the top metal layer 109 may be one or a combination of titanium, nickel, or platinum.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
In summary, in the IGBT device structure of the present invention, the schottky contact, that is, the schottky diode is formed by the contact between the top metal layer and the P body region with low doping concentration, because the schottky diode has a higher turn-on voltage drop, it can increase the fermi potential energy of holes to form hole barriers, thereby enhancing the conductance modulation of the N-type drift region when the IGBT device is turned on in the forward direction, further reducing the forward turn-on voltage drop of the IGBT device, and finally achieving the compromise relationship of improving the forward turn-on voltage drop and turn-off loss of the IGBT device, improving the performance of the IGBT device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. An IGBT device structure integrating schottky contacts, comprising at least:
a P+ collector and an N-type buffer layer formed on the P+ collector;
the N-type drift region is arranged on the N-type buffer layer and is far away from the P+ collector electrode;
the P body region is positioned at the top of the N-type drift region, and at least a first contact hole and a second contact hole are formed in the P body region, wherein the doping concentration of the P body region exposed by the first contact hole is larger than that of the P body region of the second contact Kong Xianlou;
the grid structure is arranged in contact with the N-type drift region;
the source region is positioned in the P body region and is electrically isolated from the grid structure, and the depth of the source region is not greater than the depths of the first contact hole and the second contact hole;
and the top metal layer is positioned on the source region and fills the first contact hole and the second contact hole, wherein the top metal layer positioned in the first contact hole is electrically connected with the P body region to form ohmic contact, and the top metal layer positioned in the second contact hole is electrically connected with the P body region to form Schottky contact.
2. The IGBT device structure of claim 1 wherein: the gate structure is a trench gate and comprises a trench, a gate oxide layer formed on the inner side surface of the trench and a gate filled in the trench, wherein the depth of the trench gate is greater than that of the P body region and less than that of the N-type drift region.
3. The IGBT device structure of claim 2 wherein: an interlayer dielectric layer is further arranged between the source region and the top metal layer, and the source region and the trench gate are completely covered by the interlayer dielectric layer.
4. The IGBT device structure of claim 1 wherein: the grid structure is a planar grid and comprises a grid formed on the top surface of the N-type drift region and a grid oxide layer wrapping the grid, and the planar grid and the P body region are electrically isolated through the grid oxide layer.
5. The IGBT device structure of claim 1 wherein: the width of the first contact hole is not larger than the width of the second contact hole.
6. The IGBT device structure of claim 1 wherein: the top metal layer adopts one or a combination of titanium, nickel or platinum.
7. A preparation method of an IGBT device structure integrating Schottky contact is characterized by comprising the following steps: the method comprises the following steps:
providing a semiconductor substrate, and forming an N-type drift region on the front surface of the substrate;
ion implantation is carried out on the front surface of the N-type drift region to form a P body region, the P body region is etched to form a first contact hole and a second contact hole, a grid structure is formed, and the grid structure is in contact arrangement with the N-type drift region;
ion implantation is carried out on the top of the P body region to form a source region, and the depth of the source region is not greater than the depths of the first contact hole and the second contact hole;
performing ion implantation on the P body region exposed in the first contact hole so that the doping concentration of the P body region exposed in the first contact hole is greater than that of the P body region exposed in the second contact hole;
forming a top metal layer above the source region, wherein the top metal layer fills the first contact hole and the second contact hole, is electrically connected with the P body region exposed in the first contact hole to form ohmic contact, and is electrically connected with the P body region exposed in the second contact hole to form Schottky contact;
thinning the back surface of the substrate to expose the N-type drift region, and performing N+ ion implantation on the N-type drift region to form an N-type buffer layer;
p+ ion implantation is carried out on the N-type buffer layer to form a P+ collector, and a metalized collector is formed below the P+ collector.
8. The method for manufacturing the IGBT device structure according to claim 7, wherein: the grid structure is a trench grid, the top of the N-type drift region is etched to form a trench, a grid oxide layer is formed on the inner side surface of the trench, and the grid in the trench is filled, wherein the depth of the trench grid is larger than that of the P body region and smaller than that of the N-type drift region.
9. The method for manufacturing the IGBT device structure according to claim 8, wherein: the method further comprises the step of forming an interlayer dielectric layer before forming the top metal layer, wherein the interlayer dielectric layer is located above the source region and completely covers the source region and the trench gate.
10. The method for manufacturing the IGBT device structure according to claim 7, wherein: the grid structure is a planar grid, and the forming step of the planar grid is to form a grid and a grid oxide layer wrapping the grid at the top of the N-type drift region, wherein the planar grid covers the P body region and exposes the first contact hole and the second contact hole.
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