CN107452624A - Schottky contacts SiC IGBT and preparation method thereof - Google Patents
Schottky contacts SiC IGBT and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The present invention relates to a kind of Schottky contacts SiC IGBT and preparation method thereof, wherein, preparation method includes：Choose SiC substrate；In SiC substrate superficial growth transition zone；N+ emission layers, p-type well layer, N drift layers, N+ cushions and P+ current collection layers are continuously grown in transition layer surface；Using CMP process, SiC substrate and transition zone are removed；Repeatedly selective Al ion implantation forms P+ areas and P areas in N+ emission layers；Make groove grid grid；Colelctor electrode is prepared in P+ current collection layer surfaces；Emitter stage ohmic contact metal layer is prepared in N+ transmittings layer surface；Emitter stage Schottky contact metal layer is prepared on p-type well layer surface, to complete the preparation of the Schottky contacts SiC IGBT.Emitter stage contact electrode is divided into two parts by Schottky contacts SiC IGBT proposed by the present invention；Ohmic contact and Schottky contacts；Schottky barrier has raised the potential of p-type base, plays a part of stopping hole, so as to enhance conductivity modulation effect, reduces conducting resistance.
Description
Technical field
The invention belongs to technical field of semiconductor device preparation, more particularly to a kind of Schottky contacts SiC IGBT and its preparation
Method.
Background technology
At present, China's novel power transistor mainly has a VDMOS and IGBT class devices, and new material power electronic devices
Main representative be SiC and GaN device.SiC is typical semiconductor material with wide forbidden band, has that energy gap is big, critical electric field
The features such as height, carrier saturation velocity are high, physicochemical properties are stable, hardness is high, heat endurance is good and thermal conductivity is high, it is very suitable
For making high temperature, radioresistance, high frequency, high-power and High Density Integration power electronic devices.IGBT(Insulated Gate
Bipolar Transistor), insulated gate bipolar transistor, it is that the one kind to grow up on the basis of MOSFET and BJT is new
Type hybrid power device, the advantages of being compounded with the two, there is MOS inputs, bipolar output function, collection BJT device on-state voltage drops are small,
It is excellent that current carrying density is big, high pressure and power MOSFET driving powers are small, switching speed is fast, input impedance is high, heat endurance is good
Point is.Since the advent of the world, develop into the main flow device for power switching of middle high power field of power electronics quickly.By
It is widely used in the fields such as Industry Control, automotive electronics, household appliances, network service.
SiC IGBT combine the characteristics of low in energy consumption, breakdown voltage is high, switching speed is fast, relative to SiC MOSFET and
The devices such as the IGBT of silicon substrate, IGCT have significant advantage, especially suitable for high temperature, high pressure, high frequency, high-power electric system
Application field.And SiC MOS devices have released the device of high-breakdown-voltage and interface state density, the exploitation for being SiC IGBT is spread
Road is put down.In recent years, with energy-saving and emission-reduction dynamics continue to increase and the continuous development of new energy field, IGBT as section
Energy Efficient devices obtain more wide development space.
Fig. 1 is referred to, Fig. 1 is a kind of traditional Si C IGBT structure schematic diagrames, including：Colelctor electrode 1, P+ current collection layers 2, N+ delay
Rush layer 3, N- drift layers 4, p-type well layer 5, P+ contact zones 6, N+ emission layers 7, emitter stage 8 and grid 9.
As other power devices, the optimization of SiC IGBT structures also mainly around reduction power consumption and improves breakdown potential
Two aspects of pressure.The subject matter that SiC IGBT face from the perspective of power consumption:In order to reduce the power consumption of device, first have to drop
Low on-resistance, this requires that the drift layer of device has the free carrier of higher concentration in on-state, however, largely freely carrying
Stream can cause the device turn-off time longer again, increase the turn-off power loss of device, so reducing conducting resistance and reducing shut-off damage
There is contradiction in consumption, this is subject matter existing for SiC IGBT.
Therefore how to balance and reduce SiC IGBT conducting resistances and reduce turn-off power loss and the particularly important of contradiction change be present.
The content of the invention
Based on subject matter existing for above-mentioned SiC IGBT, it is necessary to seek better method to balance reduction conducting resistance
And reduce the contradiction between turn-off power loss.If only increasing carrier concentration near emitter stage by technological means such as structure optimizations,
The carrier of emitter stage side can be scanned out rapidly under forceful electric power field action during due to shut-off, and the turn-off time can't be caused bright
Aobvious increase, is to reduce conducting resistance in this way, again without increase turn-off power loss, can solve this contradiction well
Problem.
Based on above-mentioned thought, the invention provides a kind of Schottky contacts SiC IGBT and preparation method thereof；The present invention will
The technical problem of solution is achieved through the following technical solutions：
An embodiment provides a kind of Schottky contacts SiC IGBT preparation method, including：
(a) in SiC substrate superficial growth transition zone；
(b) N+ emission layers, p-type well layer, N- drift layers are continuously grown in transition layer surface；
(c) N+ cushions and P+ current collection layers are continuously grown in N- drifts layer surface；
(d) CMP process is utilized, removes SiC substrate and transition zone；
(e) repeatedly selective Al ion implantation forms P+ areas and P areas in N+ emission layers；
(f) groove grid grid is made；
(g) collector electrode metal layer is prepared in P+ current collections layer surface；
(h) emitter stage ohmic contact metal layer is prepared in N+ transmittings layer surface；
(i) emitter stage Schottky contact metal layer is prepared on p-type well layer surface, to complete Schottky contacts SiC IGBT's
Prepare.
Wherein, by the way that emitter stage contact electrode is divided into two parts, metal and N+ emission layers contact portion are Ohmic contact,
Metal and p-type well layer contact portion are Schottky contacts.Schottky barrier has raised the potential of p-type well layer, plays and stops hole
Effect, so as to enhance conductivity modulation effect, reduce the resistance of N- drift layers, make device under high current have it is less
Conduction voltage drop.In turn off process, grid voltage is gradually reduced to 0, and as electric current is gradually reduced, device partial pressure becomes larger, due to Xiao
The forward conduction characteristic of special based diode exponential form, will not hinder hole to flow out, and make hole outflow on the contrary faster, so will not
Increase the turn-off time, switching loss can be reduced on the contrary.Be provided with a floor P areas between P+ areas and metal, make P areas be in order to formed compared with
For preferable Schottky contacts.
In one embodiment of the invention, step (a) includes：
(a1) N+ type SiC substrate pieces are chosen；
(a2) RCA standard cleanings are carried out to SiC substrate；
(a3) using low pressure hot wall chemical vapor depositing technics in the mistake that SiC substrate superficial growth thickness is 10 μm~30 μm
Cross layer.
In one embodiment of the invention, step (b) includes：
(b1) low pressure hot wall chemical vapor depositing technics is utilized, in transition zone superficial growth N+ emission layers；
(b2) low pressure hot wall chemical vapor depositing technics is utilized, in N+ emission layer superficial growth p-type well layer；
(b3) low pressure hot wall chemical vapor depositing technics is utilized, in p-type well layer superficial growth N- drift layers.
In one embodiment of the invention, step (g) includes：
(g1) in P+ current collection layer surface deposition Ti/Al alloys；
(g2) at a temperature of 1050 DEG C, the 3min that annealed in nitrogen atmosphere forms collector electrode metal layer.
In one embodiment of the invention, N+ emission layers thickness be 0.1~0.5 μm, Nitrogen ion doping concentration be 1 ×
1018~1 × 1020cm-3；P-type well layer thickness is 0.5~2 μm, Al-doping concentration is 1 × 1017cm-3~1 × 1018cm-3；
N- drift layer thickness is 100 μm~200 μm, Nitrogen ion doping concentration is 1 × 1014~1 × 1015cm-3。
In one embodiment of the invention, N+ buffer layer thicknesses are 1~10 μm, Nitrogen ion doping concentration 1 × 1016~1
×1018cm-3；P+ current collection layers thickness is 3~5 μm of (or 300 μm or so), Al-doping concentration 1 × 1018~1 × 1020cm-3。
In one embodiment of the invention, P+ areas thickness be 0.1~0.5 μm, Al-doping concentration be 1 × 1019~1
×1021cm-3；P areas thickness is 0.01~0.1 μm, Al-doping concentration is 2 × 1017~1 × 1018cm-3。
An alternative embodiment of the invention provides a kind of Schottky contacts SiC IGBT, is provided by any of the above-described embodiment
Preparation method formed.
Another embodiment of the present invention provides a kind of Schottky contacts SiC IGBT, including：Colelctor electrode, P+ current collections
Floor, N+ cushions, N- drift layers, p-type well layer, P+ areas, P areas, N+ emission layers, emitter stage and grid；
Wherein, the first metal for forming emitter stage contacts to form Ohmic contact with N+ emission layers, forms the second of emitter stage
Metal contacts to form Schottky contacts with P areas；P areas are between P+ areas and the second metal
Preferably, the first metal is Ni/Ti/Al alloys, and the second metal is Ni materials.
Compared with prior art, the invention has the advantages that：
1) low on-resistance proposed by the present invention, the Novel Schottky contact SiC IGBT of low switching losses connect emitter stage
Touched electrode is divided into two parts；Metal is Ohmic contact with N+ emission layers contact portion, and metal and p-type base contact part are Xiao Te
Base contacts.Schottky barrier has raised the potential of p-type base, plays a part of stopping hole, so as to enhance conductance modulation effect
Should, reduce conducting resistance.
2) present invention, which is provided between P+ areas and metal in a floor, adulterates P areas, and it is to be formed more that P areas are adulterated in making
Preferable Schottky contacts.P+ areas and middle doping P areas inject to be formed by primary ions simultaneously, the technique for simplifying ion implanting
Step.
3) due to the forward conduction characteristic of Schottky diode exponential form, hole stream will not be hindered in turn off process
Go out, make hole outflow on the contrary faster, so the turn-off time will not be increased, switching loss can be reduced on the contrary；
4) compared to other for enhancing conductance modulation and improved new construction, new construction proposed by the present invention is in manufacturing process
On it is simpler, feasibility is higher.
Brief description of the drawings
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
Fig. 1 is a kind of traditional Si C IGBT structure schematic diagrames provided in an embodiment of the present invention；
Fig. 2 is a kind of Schottky contacts SiC IGBT preparation method schematic flow sheets of the embodiment of the present invention；
Fig. 3 a- Fig. 3 n are that a kind of Schottky contacts SiC IGBT preparation method techniques that one embodiment of the invention provides are shown
It is intended to；
Fig. 4 a- Fig. 4 m are another Schottky contacts SiC IGBT preparation methods technique signal provided in an embodiment of the present invention
Figure；
Fig. 5 a- Fig. 5 j illustrate for another Schottky contacts SiC IGBT preparation methods technique provided in an embodiment of the present invention
Figure；
Fig. 6 is a kind of Schottky contacts SiC n-IGBT structural representations provided in an embodiment of the present invention；And
Fig. 7 is a kind of Schottky contacts SiC p-IGBT structural representations provided in an embodiment of the present invention.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 2 is referred to, Fig. 2 is that a kind of Schottky contacts SiC IGBT preparation method flows provided in an embodiment of the present invention are shown
It is intended to, including：
(a) in SiC substrate superficial growth transition zone；
(b) N+ emission layers, p-type well layer, N- drift layers are continuously grown in transition layer surface；
(c) N+ cushions and P+ current collection layers are continuously grown in N- drifts layer surface；
(d) CMP process is utilized, removes SiC substrate and transition zone；
(e) repeatedly selective Al ion implantation forms P+ areas and P areas in N+ emission layers；
(f) groove grid grid is made；
(g) collector electrode metal layer is prepared in P+ current collections layer surface；
(h) emitter stage ohmic contact metal layer is prepared in N+ transmittings layer surface；
(i) emitter stage Schottky contact metal layer is prepared on p-type well layer surface.
Preferably, step (a) can include：
(a1) N+ type SiC substrate pieces are chosen；
(a2) RCA standard cleanings are carried out to SiC substrate；
(a3) using low pressure hot wall chemical vapor depositing technics in the mistake that SiC substrate superficial growth thickness is 10 μm~30 μm
Cross layer.
Preferably, step (b) can include：
(b1) low pressure hot wall chemical vapor depositing technics is utilized, in transition zone superficial growth N+ emission layers；
(b2) low pressure hot wall chemical vapor depositing technics is utilized, in N+ emission layer superficial growth p-type well layer；
(b3) low pressure hot wall chemical vapor depositing technics is utilized, in p-type well layer superficial growth N- drift layers.
Preferably, step (g) can include：
(g1) collector contact metal is formed in P+ current collection layer surface deposition Ti/Al alloys；
(g2) at a temperature of 1050 DEG C, the 3min that annealed in nitrogen atmosphere forms colelctor electrode.
Preferably, N+ emission layers thickness be 0.1~0.5 μm, Nitrogen ion doping concentration be 1 × 1018~1 × 1020cm-3；P
Type well layer thickness is 0.5~2 μm, Al-doping concentration is 1 × 1017cm-3~1 × 1018cm-3；N- drift layer thickness is 100 μ
M~200 μm, Nitrogen ion doping concentration are 1 × 1014~1 × 1015cm-3。
Preferably, N+ buffer layer thicknesses are 1~10 μm, Nitrogen ion doping concentration 1 × 1016~1 × 1018cm-3；P+ current collections
Thickness degree is 3~5 μm of (or 300 μm or so), Al-doping concentration 1 × 1018~1 × 1020cm-3。
Preferably, P+ areas thickness is 0.1~0.5 μm, and Al-doping concentration is 1 × 1019~1 × 1021cm-3；P areas are thick
Spend for 0.01~0.1 μm, Al-doping concentration is 2 × 1017~1 × 1018cm-3。
Emitter stage contact electrode is divided into two parts by the present invention, by taking n-IGBT as an example, metal and N+ emission layer contact portions
For Ohmic contact, metal and p-type base contact part are Schottky contacts.Doped layer P in a floor is provided between P+ areas and metal
Area, by the way that ion implantation energy and depth regulation and control can be achieved, doped layer P areas are to form ideal Xiao in making
Te Ji is contacted.Schottky barrier has raised the potential of p-type base, plays a part of stopping hole, so as to enhance conductance modulation
Effect, reduce conducting resistance.And due to the forward conduction characteristic of Schottky diode exponential form, will not in turn off process
Hole outflow is hindered, makes hole outflow on the contrary faster, so the turn-off time will not be increased, switching loss can be reduced on the contrary.
Embodiment two
Refer to Fig. 3 a- Fig. 3 n, Fig. 3 a- Fig. 3 n is a kind of Schottky contacts SiC IGBT systems provided in an embodiment of the present invention
Preparation Method process schematic representation, the preparation method comprise the following steps：
1st step, choose N+Type SiC substrate piece, in N+Type SiC substrate piece Epitaxial growth transition zone.
As shown in Figure 3 a, N is chosen+Type SiC substrate piece 301, to N+Type SiC substrate piece carries out RCA standard cleanings；
As shown in Figure 3 b, it is 10 μ with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on SiC substrate piece front
The transition zone 302 of m~30 μm, its epitaxy technique condition are：Temperature be 1600 DEG C, pressure 100mbar, reacting gas be silane and
Propane, carrier gas are pure hydrogen.
2nd step, in transition zone Epitaxial growth emission layer.
As shown in Figure 3 c, it is 0.1~0.5 μ with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on transition zone
M, Nitrogen ion doping concentration 1 × 1018~1 × 1020cm-3N+ emission layers 303, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and impurity source is liquid nitrogen.
3rd step, on the emitter epitaxial growth well region.
As shown in Figure 3 d, on the emitter with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness be 0.5~2 μm,
Al-doping concentration is 1 × 1017cm-3~1 × 1018cm-3P-type well layer 304, its epitaxial temperature be 1600 DEG C, pressure
100mbar, reacting gas are silane and propane, and carrier gas is pure hydrogen, and impurity source is trimethyl aluminium.
4th step, in well region Epitaxial growth drift layer.
As shown in Figure 3 e, it is 100 μm~200 μ with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on well region
M, Nitrogen ion doping concentration is 1 × 1014~1 × 1015cm-3Drift layer 305, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and impurity source is liquid nitrogen.
5th step, in drift layer Epitaxial growth cushion.
As illustrated in figure 3f, it is 1~10 μm, nitrogen with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on drift layer
Ion doping concentration 1 × 1016~1 × 1018cm-3Cushion 306, its epitaxial temperature be 1600 DEG C, pressure 100mbar, reaction
Gas is silane and propane, and carrier gas is pure hydrogen, and impurity source is liquid nitrogen；
6th step, on the buffer layer epitaxial growth current collection layer.
As shown in figure 3g, on the buffer layer with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness be 3~5 μm (or
300 μm or so), Al-doping concentration 1 × 1018~1 × 1020cm-3Current collection layer 307, its epitaxial temperature be 1600 DEG C, pressure
Power 100mbar, reacting gas are silane and propane, and carrier gas is pure hydrogen, and impurity source is trimethyl aluminium；
7th step, remove substrate and transition zone.
As illustrated in figure 3h, using CMP process, the substrate and transition zone of removal devices.
8th step, as shown in figure 3i, the multiple selective Al ion implantation in emission layer, form P+ areas 308 and middle doped layer
P areas 309.
With low pressure chemical vapor deposition mode in one layer of SiO of drift layer surface deposition2, to SiO2Layer carries out photoetching and developed,
Expose the region for needing to carry out p-type ion implanting.Post bake is carried out to the photoresist of reservation, strengthens its corrosion stability, uses afterwards
Reactive ion etching (RIE) or the method for inductively coupled plasma etching (ICP), which remove, to be needed to carry out ion implanted regions
SiO2Layer.1 Al ion implantation is carried out at a temperature of 650 DEG C, by the control to implantation dosage and corresponding energy, makes hair
The doping concentration of emitter contact part is minimum, and it is 0.1~0.5 μm, Al-doping concentration 1 × 10 to form thickness19~1 ×
1021cm-3P+ areas and thickness be 0.01~0.1 μm, Al-doping concentration 2 × 1017~1 × 1018cm-3Middle doped layer P
Area.Photoresist is removed with such as method of acetone wet etching or oxygen plasma etch, with RIE or ICP methods
Remove SiO2Layer mask.Surface of SiC is cleaned successively using RCA cleanings standard, dried and the protection of C films, and 1700~
Make 15min ion-activated annealing in 1750 DEG C of argon atmospheres.
10th step, make groove grid.
As shown in Fig. 3 j, groove is formed using the method for reactive ion etching, oxide layer is formed by thermally grown mode；
As shown in figure 3k, polysilicon 310 is formed in groove by the method for deposit.
11st step, deposit form emitter stage ohmic contact metal layer.
As shown in Fig. 3 l, in whole device surface resist coating, emitter stage metal ohmic contact is then formed by development
Window, Ni/Ti/Al alloys are deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage ohm afterwards connects
Metal level is touched, is annealed at a temperature of 900 DEG C, in nitrogen atmosphere 5 minutes and forms Ohmic contact 311.
12nd step, deposit form collector contact metal level.
As shown in figure 3m, to whole current collection layer surface deposition Ti/Al alloys, as collector contact metal, at 1050 DEG C
Under, annealed in nitrogen atmosphere 3 minutes and form contact electrode 312.
13rd step, deposit form emitter stage Schottky contact metal layer.
As shown in figure 3n, in whole device surface resist coating, emitter stage Schottky contacts gold is then formed by development
Belong to window, W metal is deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage Schottky contacts afterwards
Metal level 313, without annealing.
Embodiment three
Refer to Fig. 4 a- Fig. 4 m, Fig. 4 a- Fig. 4 m is another Schottky contacts SiC IGBT provided in an embodiment of the present invention
Preparation method process schematic representation, the preparation method comprise the following steps：
1st step, in N+SiC substrate piece Epitaxial growth transition zone.
As shown in fig. 4 a, N is chosen+Type SiC substrate piece 401, first to N+Type SiC substrate piece carries out RCA standard cleanings；Such as figure
Shown in 4b, with the transition zone that low pressure hot wall chemical vapor sedimentation epitaxial growth thickness is 10~30 μm on SiC substrate front
402, its epitaxy technique condition is：Temperature is 1600 DEG C, and pressure 100mbar, reacting gas is silane and propane, and carrier gas is
Pure hydrogen.
2nd step, the extension drift layer on transition zone.
As illustrated in fig. 4 c, it is 100~200 μ with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on transition zone
M, Nitrogen ion doping concentration is 1 × 1014~1 × 1015cm-3Drift layer 403, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and impurity source is liquid nitrogen.
3rd step, in drift layer Epitaxial growth cushion.
As shown in figure 4d, it is 1~10 μm, nitrogen with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on drift layer
Ion doping concentration 1 × 1016~1 × 1018cm-3Cushion 404, its epitaxy technique condition is：Temperature is 1600 DEG C, pressure
100mbar, reacting gas are silane and propane, and carrier gas is pure hydrogen, and impurity source is liquid nitrogen.
4th step, on the buffer layer epitaxial growth current collection layer.
As shown in fig 4e, on the buffer layer with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness be 3~5 μm (or
300 μm or so), Al-doping concentration 1 × 1018~1 × 1020cm-3Current collection layer 405, its epitaxy technique condition is：Temperature
For 1600 DEG C, pressure 100mbar, reacting gas is silane and propane, and carrier gas is pure hydrogen, and impurity source is trimethyl aluminium.
5th step, remove substrate and transition zone.
As shown in fig. 4f, using CMP process, the substrate and transition zone of removal devices.
6th step, in drift layer Epitaxial growth p-type well layer.
Be as shown in figure 4g, 0.5~2 μm with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on drift layer,
Al-doping concentration 1 × 1017cm-3~1 × 1018cm-3P-type well layer 406, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas is silane and propane, and carrier gas is pure hydrogen, and impurity source is trimethyl aluminium.
7th step, as shown in figure 4h, the multiple selective Al ion implantation in p-type well layer, form P+ areas 407 and middle doping
Floor P areas 408.
With low pressure chemical vapor deposition mode in one layer of SiO of drift layer surface deposition2, to SiO2Layer carries out photoetching and developed,
Expose the region for needing to carry out p-type ion implanting.Post bake is carried out to the photoresist of reservation, strengthens its corrosion stability, uses afterwards
Reactive ion etching (RIE) or the method for inductively coupled plasma etching (ICP), which remove, to be needed to carry out ion implanted regions
SiO2Layer.1 Al ion implantation is carried out at a temperature of 650 DEG C, by the control to implantation dosage and corresponding energy, makes hair
The doping concentration of emitter contact part is minimum, and it is 0.1~0.5 μm, Al-doping concentration 1 × 10 to form thickness19~1 ×
1021cm-3P+ areas and thickness be 0.01~0.1 μm, Al-doping concentration 2 × 1017~1 × 1018cm-3Middle doped layer P
Area.Photoresist is removed with such as method of acetone wet etching or oxygen plasma etch, with RIE or ICP methods
Remove SiO2Layer mask.Surface of SiC is cleaned successively using RCA cleanings standard, dried and the protection of C films, and 1700~
Make 15min ion-activated annealing in 1750 DEG C of argon atmospheres.
8th step, as shown in figure 4i, the multiple selective N~+ implantation in p-type well layer, form emission layer 409.
With low pressure chemical vapor deposition mode in one layer of SiO of drift layer surface deposition2, to SiO2Layer carries out photoetching and developed,
Expose the region for needing to carry out p-type ion implanting.Post bake is carried out to the photoresist of reservation, strengthens its corrosion stability, uses afterwards
Reactive ion etching (RIE) or the method for inductively coupled plasma etching (ICP), which remove, to be needed to carry out ion implanted regions
SiO2Layer.It is 0.1~0.5 μm, Nitrogen ion doping concentration 1 that 2 N~+ implantations are carried out at a temperature of 650 DEG C and form depth
×1018~1 × 1020cm-3N+ emission layers 409.Gone with such as method of acetone wet etching or oxygen plasma etch
Except photoresist, SiO is removed with RIE or ICP methods2Layer mask.Surface of SiC is carried out successively clearly using RCA cleanings standard
Wash, dry and the protection of C films, and make in 1700~1750 DEG C of argon atmospheres 15min ion-activated annealing.
9th step, make groove grid.
As shown in figure 4j, groove is formed using the method for reactive ion etching, oxide layer is formed by thermally grown mode,
Then polysilicon 410 is formed in groove by the method for deposit.
10th step, deposit form emitter stage ohmic contact metal layer.
As shown in fig. 4k, in whole device surface resist coating, emitter stage metal ohmic contact is then formed by development
Window, Ni/Ti/Al alloys are deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage ohm afterwards connects
Metal level 411 is touched, is annealed at a temperature of 900 DEG C, in nitrogen atmosphere 5 minutes and forms Ohmic contact.
11st step, deposit form collector contact metal level.
As shown in Fig. 4 l, to whole current collection layer surface deposition Ti/Al alloys, as collector contact metal, at 1050 DEG C
Under, annealed in nitrogen atmosphere 3 minutes and form contact electrode 412.
12nd step, deposit form emitter stage Schottky contact metal layer.
As shown in Fig. 4 m, in whole device surface resist coating, emitter stage Schottky contacts gold is then formed by development
Belong to window, W metal is deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage Schottky contacts afterwards
Metal level 413, without annealing.
Example IV
Refer to Fig. 5 a- Fig. 5 j, Fig. 5 a- Fig. 5 j is another Schottky contacts SiC IGBT provided in an embodiment of the present invention
Preparation method process schematic representation, the preparation method comprise the following steps：
1st step, in N+SiC substrate piece Epitaxial growth cushion.
As shown in Figure 5 a, N is chosen+Type SiC substrate piece 501, first to N+Type SiC substrate piece carries out RCA standard cleanings；Such as figure
Shown in 5b, on sic substrates with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness be 1~10 μm, Al-doping it is dense
Degree 1 × 1016~1 × 1018cm-3Cushion 502, its epitaxy technique condition is：Temperature is 1600 DEG C, pressure 100mbar, instead
It is silane and propane to answer gas, and carrier gas is pure hydrogen, and impurity source is trimethyl aluminium.
2nd step, on the buffer layer epitaxial growth drift layer.
As shown in Figure 5 c, with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness it is on the buffer layer 100~200 μ
M, Al-doping concentration is 1 × 1014~1 × 1015cm-3Drift layer 503, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas uses silane and propane, and carrier gas uses pure hydrogen, and impurity source is trimethyl aluminium.
3rd step, in drift layer Epitaxial growth N-type well region.
Be as fig 5d, 0.5~2 μm with low pressure hot wall chemical vapor sedimentation epitaxial growth thickness on drift layer,
Nitrogen ion doping concentration is 1 × 1017cm-3~1 × 1018cm-3N-type well region 504, its epitaxy technique condition is：Temperature is 1600
DEG C, pressure 100mbar, reacting gas is silane and propane, and carrier gas is pure hydrogen, and impurity source is liquid nitrogen.
4th step, as depicted in fig. 5e, the multiple selective N~+ implantation in N-type well region, form N+ areas 505 and middle doping
Floor N areas 506.
With low pressure chemical vapor deposition mode in one layer of SiO of drift layer surface deposition2, to SiO2Layer carries out photoetching and developed,
Expose the region for needing to carry out N-type ion implanting.Post bake is carried out to the photoresist of reservation, strengthens its corrosion stability, uses afterwards
Reactive ion etching (RIE) or the method for inductively coupled plasma etching (ICP), which remove, to be needed to carry out ion implanted regions
SiO2Layer.1 N~+ implantation is carried out at a temperature of 650 DEG C, by the control to implantation dosage and corresponding energy, makes hair
The doping concentration of emitter contact part is minimum, and it is 0.1~0.5 μm, Nitrogen ion doping concentration 1 × 10 to form thickness19~1 ×
1021cm-3N+ areas 505 and thickness be 0.01~0.1 μm, Nitrogen ion doping concentration 5 × 1017~1 × 1018cm-3Middle doping
Floor N areas 506.Remove photoresist with such as method of acetone wet etching or oxygen plasma etch, with RIE or
ICP methods remove SiO2Layer mask.Using RCA cleaning standard surface of SiC is cleaned successively, dry and C films protection, and
Make 15min ion-activated annealing in 1700~1750 DEG C of argon atmospheres.
5th step, as shown in figure 5f, the multiple selective Al ion implantation in N-type well region, form emission layer 507.
With low pressure chemical vapor deposition mode in one layer of SiO of drift layer surface deposition2, to SiO2Layer carries out photoetching and developed,
Expose the region for needing to carry out p-type ion implanting.Post bake is carried out to the photoresist of reservation, strengthens its corrosion stability, uses afterwards
Reactive ion etching (RIE) or the method for inductively coupled plasma etching (ICP), which remove, to be needed to carry out ion implanted regions
SiO2Layer.2 Al ion implantations are carried out at a temperature of 650 DEG C, it is 0.1~0.5 μm, Al-doping concentration to form depth
1×1018~1 × 1020cm-3P+ emission layers 507.With such as method of acetone wet etching or oxygen plasma etch
Photoresist is removed, SiO is removed with RIE or ICP methods2Layer mask.Surface of SiC is carried out successively using RCA cleanings standard
Cleaning, drying and C films are protected, and make 15min ion-activated annealing in 1700~1750 DEG C of argon atmospheres.
6th step, make groove grid.
As shown in fig. 5g, groove is formed using the method for reactive ion etching, oxide layer is formed by thermally grown mode,
Then polysilicon 508 is formed in groove by the method for deposit.
7th step, deposit form emitter stage ohmic contact metal layer.
As shown in figure 5h, in whole device surface resist coating, emitter stage metal ohmic contact is then formed by development
Window, Ti/Al alloys are deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage Ohmic contact gold afterwards
Belong to layer 509, annealed at a temperature of 1050 DEG C, in nitrogen atmosphere 3 minutes and form Ohmic contact.
8th step, deposit form collector contact metal level.
As shown in figure 5i, to whole current collection layer surface deposition Ni/Ti/Al alloys, as collector contact metal, 900
Annealed at DEG C, in nitrogen atmosphere 5 minutes and form contact electrode 510.
9th step, deposit form emitter stage Schottky contact metal layer.
As shown in figure 5j, in whole device surface resist coating, emitter stage Schottky contacts gold is then formed by development
Belong to window, W metal is deposited to whole device surface, peeled off by ultrasonic wave makes front form emitter stage Schottky contacts afterwards
Metal level 511, without annealing.
Embodiment five
By taking n-IGBT as an example, Fig. 6 is referred to, Fig. 6 is a kind of Schottky contacts SiC n- provided in an embodiment of the present invention
IGBT structure schematic diagram, including：
Colelctor electrode 601, P+ current collection layers 602, N+ cushions 603, N- drift layers 604, p-type well layer 605, P+ areas 606, P areas
607, N+ emission layers 608, emitter stage Schottky contact metal layer 609, emitter stage ohmic contact metal layer 610 and grid 611.
Preferably, metal and the contact portion of N+ emission layers 608 are emitter stage ohmic contact metal layer 610, metal and P areas
607 contact portions are emitter stage Schottky contact metal layer 609；
Wherein, P areas 607 are between P+ areas 606 and metal.
Preferably, the material of emitter stage Schottky contact metal layer 609 is W metal；Emitter stage ohmic contact metal layer 610
Material is Ni/Ti/Al alloys.
Wherein, Schottky barrier has raised the potential of p-type well layer 605, plays a part of stopping hole, enhances conductance tune
Effect processed, make device that there is less conduction voltage drop under high current, and due to the positive guide of Schottky diode exponential form
Logical characteristic, does not increase turn-off power loss.
Embodiment six
By taking p-IGBT as an example, Fig. 7 is referred to, Fig. 7 is a kind of Schottky contacts SiC p- provided in an embodiment of the present invention
IGBT structure schematic diagram, including：
Colelctor electrode 701, N+ current collection layers 702, P+ cushions 703, P- drift layers 704, N-type well region 705, N+ areas 706, N areas
707, P+ emission layers 708, emitter stage Schottky contact metal layer 709, emitter stage ohmic contact metal layer 710 and grid 711.
Preferably, metal and the contact portion of P+ emission layers 708 are emitter stage ohmic contact metal layer 710, metal and N-type trap
The contact portion of area 705 is emitter stage Schottky contact metal layer 709；
Wherein, N areas are between N+ areas 706 and metal.
Preferably, the material of emitter stage Schottky contact metal layer 709 is W metal；Emitter stage ohmic contact metal layer 710
Material is Ti/Al alloys.
Wherein, Schottky barrier has raised the potential of N-type well region 705, plays a part of stopping hole, enhances conductance tune
Effect processed, make device that there is less conduction voltage drop under high current, and due to the positive guide of Schottky diode exponential form
Logical characteristic, does not increase turn-off power loss.
Emitter stage contact electrode is divided into two parts by the present invention, by taking p-IGBT as an example, metal and P+ emission layer contact portions
For Ohmic contact, metal and the middle contact portion of doped layer N areas 707 are Schottky contacts.It is provided between N+ areas and metal in a floor
Doped layer N areas, by the way that ion implantation energy and depth regulation and control can be achieved, doped layer N areas are to be formed more in making
Preferable Schottky contacts.Schottky barrier reduces the potential of N-type well region, plays a part of stopping electronics, so as to enhance
Conductivity modulation effect, reduce conducting resistance.And due to the forward conduction characteristic of Schottky diode exponential form, turning off
Electronics will not be hindered to flow out in journey, make electronics outflow on the contrary faster, so the turn-off time will not be increased, switch damage can be reduced on the contrary
Consumption.In addition, relative to n-IGBT, n-type substrate is selected in p-IGBT making, and n-type substrate resistivity is low, quality is good, and this is p-
IGBT is relative to where n-IGBT advantage.
Specific case used herein Schottky contacts SiC IGBT a kind of to present invention principle and embodiment is entered
Elaboration is gone, the explanation of above example is only intended to help the method and its core concept for understanding the present invention；Meanwhile for this
The those skilled in the art in field, according to the thought of the present invention, there will be changes in specific embodiments and applications,
To sum up, this specification content should not be construed as limiting the invention, and protection scope of the present invention should be with appended claim
It is defined.
Claims (10)
- A kind of 1. Schottky contacts SiC IGBT preparation method, it is characterised in that including：(a) in SiC substrate superficial growth transition zone；(b) N+ emission layers, p-type well layer, N- drift layers are continuously grown in the transition layer surface；(c) N+ cushions and P+ current collection layers are continuously grown in N- drifts layer surface；(d) CMP process is utilized, removes the SiC substrate and the transition zone；(e) repeatedly selective Al ion implantation forms P+ areas and P areas in the N+ emission layers；(f) groove grid grid is made；(g) collector electrode metal layer is prepared in the P+ current collections layer surface；(h) emitter stage ohmic contact metal layer is prepared in N+ transmittings layer surface；(i) emitter stage Schottky contact metal layer is prepared on the p-type well layer surface, to complete the Schottky contacts SiC IGBT preparation.
- 2. preparation method according to claim 1, it is characterised in that step (a) includes：(a1) N+ type SiC substrate pieces are chosen；(a2) RCA standard cleanings are carried out to the SiC substrate；(a3) it is 10 μm~30 μm of institute in the SiC substrate superficial growth thickness using low pressure hot wall chemical vapor depositing technics State transition zone.
- 3. preparation method according to claim 1, it is characterised in that step (b) includes：(b1) low pressure hot wall chemical vapor depositing technics is utilized, in N+ emission layers described in the transition zone superficial growth；(b2) low pressure hot wall chemical vapor depositing technics is utilized, in p-type well layer described in the N+ emission layers superficial growth；(b3) low pressure hot wall chemical vapor depositing technics is utilized, in N- drift layers described in the p-type well layer superficial growth.
- 4. preparation method according to claim 1, it is characterised in that step (g) includes：(g1) in the P+ current collection layers surface deposition Ti/Al alloys；(g2) at a temperature of 1050 DEG C, the 3min that annealed in nitrogen atmosphere forms the collector electrode metal layer.
- 5. preparation method according to claim 1, it is characterised in that the N+ emission layers thickness is 0.1~0.5 μm, nitrogen Ion doping concentration is 1 × 1018~1 × 1020cm-3；The p-type well layer thickness is 0.5~2 μm, Al-doping concentration is 1 ×1017cm-3~1 × 1018cm-3；The N- drift layer thickness is 100 μm~200 μm, Nitrogen ion doping concentration is 1 × 1014~ 1×1015cm-3。
- 6. preparation method according to claim 1, it is characterised in that the N+ buffer layer thicknesses are 1~10 μm, Nitrogen ion Doping concentration 1 × 1016~1 × 1018cm-3；The P+ current collection layers thickness is 3~5 μm, Al-doping concentration 1 × 1018~1 × 1020cm-3。
- 7. preparation method according to claim 1, it is characterised in that P+ areas thickness is 0.1~0.5 μm, aluminium ion Doping concentration is 1 × 1019~1 × 1021cm-3；P areas thickness is 0.01~0.1 μm, Al-doping concentration is 2 × 1017 ~1 × 1018cm-3。
- 8. a kind of Schottky contacts SiC IGBT, it is characterised in that the SiC IGBT are as described in any one of claim 1~7 Method prepare to be formed.
- A kind of 9. Schottky contacts SiC IGBT, it is characterised in that including：Colelctor electrode, P+ current collection layers, N+ cushions, N- drifts Floor, p-type well layer, P+ areas, P areas, N+ emission layers, emitter stage and grid；Wherein, the first metal for forming the emitter stage contacts to form Ohmic contact with the N+ emission layers, forms the transmitting Second metal of pole contacts to form Schottky contacts with the P areas；The P areas be located at the P+ areas and second metal it Between.
- 10. IGBT according to claim 9, it is characterised in that first metal is Ni/Ti/Al alloys, described second Metal is Ni materials.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113764510A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Novel low turn-off loss electron injection effect enhanced IGBT device |
| CN116417507A (en) * | 2023-03-31 | 2023-07-11 | 瑶芯微电子科技(上海)有限公司 | IGBT device structure integrating Schottky contact and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140231867A1 (en) * | 2013-02-15 | 2014-08-21 | Toyota Jidosha Kabushiki Kaisha | Diode and semiconductor device including built-in diode |
| CN105206656A (en) * | 2015-08-25 | 2015-12-30 | 电子科技大学 | Reverse conducting IGBT device |
| CN106711208A (en) * | 2016-12-29 | 2017-05-24 | 西安电子科技大学 | Silicon carbide vertical insulated gate bipolar transistor and production method thereof |
-
2017
- 2017-06-19 CN CN201710465576.9A patent/CN107452624A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140231867A1 (en) * | 2013-02-15 | 2014-08-21 | Toyota Jidosha Kabushiki Kaisha | Diode and semiconductor device including built-in diode |
| CN105206656A (en) * | 2015-08-25 | 2015-12-30 | 电子科技大学 | Reverse conducting IGBT device |
| CN106711208A (en) * | 2016-12-29 | 2017-05-24 | 西安电子科技大学 | Silicon carbide vertical insulated gate bipolar transistor and production method thereof |
Non-Patent Citations (1)
| Title |
|---|
| MENGXUAN JIANG ET AL: "Simulation Study of an Injection Enhanced Insulated-Gate Bipolar Transistor With p-Base Schottky Contact", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113764510A (en) * | 2021-07-30 | 2021-12-07 | 西安电子科技大学 | Novel low turn-off loss electron injection effect enhanced IGBT device |
| CN113764510B (en) * | 2021-07-30 | 2022-09-09 | 西安电子科技大学 | Low-turn-off-loss IGBT device with enhanced electron injection effect |
| CN116417507A (en) * | 2023-03-31 | 2023-07-11 | 瑶芯微电子科技(上海)有限公司 | IGBT device structure integrating Schottky contact and preparation method thereof |
| CN116417507B (en) * | 2023-03-31 | 2024-01-12 | 瑶芯微电子科技(上海)有限公司 | IGBT device structure integrating Schottky contact and preparation method thereof |
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