CN102832248A - Silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) based on semi-super junction and manufacturing method - Google Patents

Silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) based on semi-super junction and manufacturing method Download PDF

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CN102832248A
CN102832248A CN2012103327533A CN201210332753A CN102832248A CN 102832248 A CN102832248 A CN 102832248A CN 2012103327533 A CN2012103327533 A CN 2012103327533A CN 201210332753 A CN201210332753 A CN 201210332753A CN 102832248 A CN102832248 A CN 102832248A
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silicon carbide
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CN2012103327533A
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汤晓燕
宋庆文
李华超
张玉明
张义门
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西安电子科技大学
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Abstract

The invention discloses a silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) based on a super junction structure and traditional drift region combined semi-super junction, mainly for solving the problem that the existing silicon carbide MOSFET has a high on resistance in a high breakdown voltage. The silicon carbide MOSFET comprises a source (1), a grid (2), an SiO2 oxide medium (3), an N<+> source region (4), a P<+> contact region (5), a P trap (6), a JFET (junction field effect transistor) region (7), an N<-> epitaxial layer (11), an N<+> substrate (12) and a drain (13), wherein a current extension layer (10) is arranged above the N<-> epitaxial layer (11), a P<+> column region (8) with a doping concentration of 1*10<16>-3*10<17> cm<-3> is arranged below the P trap (6) and on each of two sides above the current extension layer (10), the two P<+> column regions (8) are in equal transverse width, and an N<+> column region (9) in the same doping concentration of the P<+> column region and in the width equal to the sum of the widths of the two P<+> column regions is arranged under the JFET region (7). The device disclosed by the invention has the advantage of low on resistance and can be used for high-power electrical equipment, solar energy power generation module and hybrid electric vehicle.

Description

Silicon carbide MOSFET and manufacture method based on half ultra knot

Technical field

The invention belongs to microelectronic, relate in particular to a kind of silicone carbide metal oxide semiconductor field effect pipe, can be used for high-power electrical equipment, solar power generation module and fuel combination electric motor car.

Technical background

SiC is the semiconductor material with wide forbidden band that develops rapidly for over ten years recently, and with other semi-conducting material, such as Si, GaN and GaAs compare, and the SiC material has advantages such as broad stopband, high heat conductance, the saturated mobility of high carrier, high power density.SiC can thermal oxidation generate silicon dioxide, makes the realization of SiC metal oxide semiconductor field effect tube MOSFET and circuit become possibility.Since the nineties in 20th century, SiC MOSFET has obtained at aspects such as switching power supply, automotive electronics and power amplifiers widely and has used.

Yet as a kind of power device, shown in accompanying drawing 1, still there is very big problem in traditional silicon carbide MOSFET on performance.One of most critical is exactly because the restricting relation that exists between its puncture voltage of epitaxial loayer drift region that plays to bear withstand voltage effect and the conducting resistance; Improve puncture voltage and often can not realize simultaneously with the reduction conducting resistance, this has very big energy loss when just causing device under big voltage, to be worked.

The Chen Xing of University of Electronic Science and Technology assisted the academician when research Si base power MOSFET in 1989, had proposed a kind of Withstand voltage layer of super-junction structure, when substituting traditional drift layer with super-junction structure, can break through Si material conducting resistance and reverse withstand voltage limit relation, i.e. R On=0.83 * 10 -8* V B 2.5(Ω cm 2).After super-junction structure proposes, in theoretical and device manufacturing, carried out deep research very soon, the result shows that super-junction structure can break through the silicon limit really, can greatly reduce conducting resistance certain under reverse withstand voltage.In recent years; Because the inherent limitation of Si material, in the power MOSFET field, people have begun to make MOSFET with new material SiC; Continuous improvement along with SiC MOSFET manufacture craft; The conducting resistance of SiC MOSFET is approached towards the limiting value of SiC material, so also in continuous decline; Seeking new structure and method, to continue to reduce the conducting resistance of SiC MOSFET just very necessary, and it is exactly a kind of natural thinking that the super-junction structure that will on Si base power MOSFET, succeed is applied to SiC MOSFET.L.C.Yu; K.Sheng2006 is published in that the SiC MOSFET to super-junction structure has carried out theoretical simulation in " the Breaking the theoretical limit of SiC unipolar power device – A simulation study " literary composition in " Solid-State Electronics "; The result shows utilization technological level at that time, and the limiting value of the comparable SiC of its FOM value improves 300%.The key of ultra knot SiC MOSFET is to make the super-junction structure with high-aspect-ratio; Present technological level can only produce the super-junction structure that depth-to-width ratio is 4:1; Because area is limited in the circuit chip of reality, the transverse width of super-junction structure can not be excessive, and longitudinal thickness also just is restricted; And then determine that its voltage endurance capability can be too not high; This just causes in the circuit application of reality, existing process conditions place an order net income with the produced device of super-junction structure its withstand voltage do not reach side circuit use in needed withstand voltage, though and adopt the SiC MOSFET of traditional structure can satisfy withstand voltage demand merely; But its conducting resistance is bigger, and power consumption is bigger when causing the device forward conduction.

Summary of the invention

The objective of the invention is to deficiency to above-mentioned prior art; Based on the existing processes level; Silicon carbide MOSFET of a kind of half super-junction structure that combines based on super-junction structure and conventional Drift district and preparation method thereof is proposed; Further reduce conducting resistance under the prerequisite of withstand voltage demand satisfying, power consumption when reducing the device forward conduction.

For realizing above-mentioned purpose, device of the present invention comprises: source electrode 1, grid 2, SiO 2Medium of oxides 3, N +Source region 4, P +Ohmic contact regions 5, P trap 6, JFET zone 7, N -Epitaxial loayer 11, N +Substrate 12 and drain electrode 13 is characterized in that:

N-epitaxial loayer 11 tops are provided with current extending 10, the both sides of current extending 10 tops and under P trap 6, be provided with P +8, two P in post district +Post district (8) transverse width equates;

The below in JFET zone (13) is provided with N +Post district 9, this N +Post district 9 is positioned at two P +Between the post district 8, its width is two P +The width sum in post district 8;

Said P +Post district 8 and N +The doping content in post district 9 equates that being doping content is 1 * 10 16~ 3 * 10 17Cm -3Highly doped zone;

Said current extending 10 is 1 * 10 for doping content 17~ 5 * 10 17Cm -3The highly doped zone of N type, the path when vertically flowing to widen electric current.

For realizing above-mentioned purpose, the present invention is based on the silicon carbide MOSFET manufacture method of half ultra knot, comprise the steps:

(1) at N +Epitaxial growth thickness is 5 ~ 20 μ m on the front of silicon carbide substrates, and nitrogen ion doping concentration is 5 * 10 15~ 1 * 10 16Cm -3The N epitaxial loayer;

(2) at N -The surperficial epitaxial growth thickness of epitaxial loayer is 0.05 ~ 0.5 μ m, and nitrogen ion doping concentration is 1 * 10 17~ 5 * 10 17Cm -3N +Current extending;

(3) at N +Epitaxial growth thickness is that 5 ~ 20 μ m, nitrogen ion doping concentration are 1 * 10 on the current extending 16~ 3 * 10 17Cm -3N +Epitaxial loayer;

(4) adopt the ICP etching technics, to N +Etching is carried out in the both sides of epitaxial loayer, forms the P that treats extension +The post district, etching depth is 5 ~ 20 μ m;

(5) epitaxial growth thickness is that 5 ~ 20 μ m, aluminium ion doping content are 1 * 10 on the zone that etches 16~ 3 * 10 17Cm -3Epitaxial loayer form P +The post district;

(6) the positive epitaxial growth formation thickness at whole carborundum is that 0.5 μ m, aluminium ion doping content are 5 * 10 15Cm -3P trap epitaxial loayer;

(7) the zone line ion injection degree of depth at P trap epitaxial loayer is 0.5 μ m, and doping content is 1 * 10 17Cm -3The nitrogen ion form the JFET district;

(8) the fringe region ion injection degree of depth in P post district is 0.5 μ m, and doping content is 1 * 10 19Cm -3Aluminium ion form P +Ohmic contact regions;

(9) in the P trap near P +It is 0.25 μ m that the ohmic contact regions ion injects the degree of depth, and doping content is 1 * 10 19Cm -3The nitrogen ion, form N +The source region;

(10) technology that adopts dry-oxygen oxidation and wet-oxygen oxidation to combine at whole silicon carbide is carried out oxidation, forms the gate oxide of 50nm;

(11) whole silicon carbide use low pressure hot wall chemical vapor deposition method deposition thickness as the polysilicon of 150nm as grid, its deposition temperature is 600 ~ 700 ℃, pressure is 60 ~ 80Pa, reacting gas is silane and hydrogen phosphide, carrier gas is a helium;

(12) at P +Ohmic contact regions, N +Source region and whole carborundum back side deposition thickness are the Al/Ti alloy of 300nm/100nm, as the contact metal layer of source electrode and drain electrode, under 1100 ± 50 ℃ of temperature, in the nitrogen atmosphere whole carborundum annealing are formed Ohm contact electrode in 3 minutes then.

Chemical vapor deposition CVD method is all adopted in said step (1), (2), (3), and its process conditions are: epitaxial growth temperature is 1600 ℃, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Chemical vapor deposition CVD method is all adopted in said step (5), (6), and its process conditions are: epitaxial growth temperature is 1600 ℃, and pressure is 100mbar, and reacting gas is silane and propane, and carrier gas is a pure hydrogen, and impurity source is a trimethyl aluminium;

The related ICP etch technological condition of said step (4) is: ICP coil power 850W, source power 100W, reacting gas SF 6And O 2Be respectively 48sccm and 12sccm;

The related ion implantation technology condition of said step (8) is: implantation temperature: 650 ℃, and ion-activated annealing temperature: 1750 ℃, annealing time: 10min;

The related ion implantation technology condition of said step (9) is: implantation temperature: 500 ℃, and ion-activated annealing temperature: 1750 ℃, annealing time: 10min;

The related oxidation technology condition of said step (10) is: the dry-oxygen oxidation temperature: 1200 ℃, and wet-oxygen oxidation temperature: 950 ℃.

The present invention has following advantage:

The present invention makes the doping content in device P+ post district and N+ post district to improve greatly owing to introduce P+ post district and the super-junction structure of N+ post district formation, thereby makes that the conducting resistance of device is significantly reduced under the constant condition of puncture voltage; Owing between super-junction structure and conventional Drift district, added highly doped current extending, conducting resistance is further reduced simultaneously.

Description of drawings

Fig. 1 is traditional silicon carbide MOSFET structural representation;

Fig. 2 is the silicon carbide MOSFET structural representation that the present invention is based on half ultra knot;

Fig. 3 is a manufacture craft flow chart of the present invention.

Embodiment

With reference to Fig. 2, field-effect transistor device of the present invention comprises: source electrode 1, polysilicon gate 2, SiO 2Medium of oxides 3, N +Source region 4, P +Ohmic contact regions 5, P trap 6, JFET district 7, P+ post district 8, N+ post district 9, current extending 10, N -Epitaxial loayer 11, substrate 12 and drain 13.Wherein,

N +Substrate 12, for thickness is 200 ~ 500 μ m, nitrogen ion doping concentration is 5 * 10 18~ 1 * 10 20Cm -3N type silicon carbide substrates sheet;

N -Epitaxial loayer 11 is for thickness is that 5 ~ 20 μ m, nitrogen ion doping concentration are 5 * 10 15~ 1 * 10 16Cm -3N type silicon carbide epitaxial layers;

Current extending 10 is for thickness is that 0.05 ~ 0.5 μ m, nitrogen ion doping concentration are 1 * 10 17~ 5 * 10 17Cm -3N type silicon carbide epitaxial layers;

N +Post district 9, for thickness is 5 ~ 20 μ m, nitrogen ion doping concentration is 1 * 10 16~ 3 * 10 17Cm -3N type silicon carbide epitaxial layers;

P +Post district 8, for thickness is 5 ~ 20 μ m, the aluminium ion doping content is 1 * 10 16~ 3 * 10 17Cm -3P type silicon carbide epitaxial layers;

JFET district 7, for thickness is 0.5 μ m, nitrogen ion doping concentration is 1 * 10 17Cm -3N type carborundum, form through ion implantation technology;

P trap 6, for thickness is 0.5 μ m, the aluminium ion doping content is 5 * 10 15Cm -3P type silicon carbide epitaxial layers;

P +Ohmic contact regions 5, for thickness is 0.5 μ m, the aluminium ion doping content is 1 * 10 19Cm -3P type carborundum, form through ion implantation technology;

N +Source region 4, for thickness is 0.25 μ m, nitrogen ion doping concentration is 1 * 10 19Cm -3N type carborundum, form through ion implantation technology;

SiO 2Medium of oxides 3 is for thickness is 50nm SiO 2Dielectric layer, the technology that adds wet oxygen through dried oxygen forms;

Grid 2 for thickness is the polysilicon layer of 150nm, adopts low pressure hot wall chemical vapor deposition method to form;

Source electrode 1 is for by thickness being the alloy-layer that the Al/Ti of 300nm/100nm forms;

Drain electrode 13 is for by thickness being the alloy-layer that the Al/Ti of 300nm/100nm forms.

Described N +Above the substrate 12 is N-epitaxial loayer 11; N-epitaxial loayer 11 tops are current extending 10; Two P of bilateral symmetry distribution of current extending 10 tops +Post district 8; N +Post district 9 is positioned at two P +Between the post district 8; This N +The width in post district 9 is two P +The width sum in post district 8; Above P+ post district 8, be P trap 6; Above N+ post district 9, be JFET district 7; At the edge of P trap 6 is P +Ohmic contact regions 5; In P trap 6 near P +The position of ohmic contact regions 5 is N +Source region 4; On JFET district 7 SiO 2Spacer medium 3; SiO 2Above the spacer medium 3 is grid 2; At N +Source region 4 and P +Above the ohmic contact regions 5 is source electrode 1; N +The back side of substrate 12 is drain electrode 13.

With reference to Fig. 3, make the method for the above-mentioned device of the present invention, provide following three kinds of embodiment:

Embodiment 1

Step 1. is at N +Epitaxial growth N on the silicon carbide substrates sheet -Drift layer is like Fig. 3 a.

Be 200 μ m to thickness earlier, nitrogen ion doping doping content is 1 * 10 20Cm -3N +Type silicon carbide substrates sheet carries out the RCA standard cleaning, and on its front, using low pressure hot wall CVD method epitaxial growth thickness again is that 5 μ m, nitrogen ion doping concentration are 1 * 10 16Cm -3N -The extension drift layer, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen.

Step 2. is at N -Epitaxial growth N on the drift layer +Current extending is like Fig. 3 b.

At N -The surperficial epitaxial growth thickness of epitaxial loayer is 0.05 μ m, and nitrogen ion doping concentration is 1 * 10 17Cm -3N +Current extending, its epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step 3. is epitaxial growth N on current extending +Columnar region is like Fig. 3 c.

Using low pressure hot wall CVD method epitaxial growth thickness is that 5 μ m, nitrogen ion doping concentration are 3 * 10 17Cm -3N +Epitaxial loayer, epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step 4. adopts the ICP etching technics, to N +Etching is carried out in the both sides of epitaxial loayer, forms the P that treats extension +The post district, etching depth is 5 μ m; Like Fig. 3 d.

Adopt the ICP etching technics in the zone that etches, it is the P of 5 μ m that etching forms the degree of depth +Columnar region, the ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF 6And O 2Be respectively 48sccm and 12sccm.

Step 5. selective epitaxial growth P +The post district is like Fig. 3 e.

Using low pressure hot wall CVD method epitaxial growth thickness in the zone that etches is that 5 μ m, nitrogen ion doping concentration are 3 * 10 17Cm -3P +The post district, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a trimethyl aluminium.

Step 6. epitaxial growth p well area is like Fig. 3 f.

Positive epitaxial growth formation thickness at whole carborundum is that 0.5 μ m, aluminium ion doping content are 5 * 10 15Cm -3P trap epitaxial loayer, its epitaxial growth technology condition is: temperature is 1600 ℃, pressure 100mbar, reacting gas are silane and propane, carrier gas is a pure hydrogen, impurity source is a trimethyl aluminium.

Step 7. is 1 * 10 in the zone line employing nitrogen ion injection formation nitrogen ion doping concentration of P trap 17Cm -3The JFET district is like Fig. 3 g.

(7.1) using the low pressure chemical vapor deposition mode is the SiO of 0.2 μ m at whole silicon carbide deposit one layer thickness 2Passivation layer, deposition thickness is the barrier layer of the Al of 1 μ m as nitrogen ion injection in the JFET district again, forms the JFET injection region through photoetching and etching;

(7.2) under 500 ℃ ambient temperature, carry out 4 nitrogen ions and inject, successively inject energy and be respectively 380keV, 250keV, 150keV and 80keV, corresponding dosage is 1.66 * 10 12Cm -2, 1.30 * 10 12Cm -2, 1.02 * 10 12Cm -2With 7.23 * 10 11Cm -2The nitrogen ion;

(7.3) adopt the RCA standard of cleaning that silicon carbide is cleaned, do the protection of C film after the oven dry; In 1750 ℃ of argon atmospheres, carry out ion-activated annealing 15min then.

Step 8. adopts 4 selectivity aluminium ion injection technologies at the fringe region of P trap, forms P +Ohmic contact regions is like Fig. 3 h.

(8.1) using the low pressure chemical vapor deposition mode is the SiO of 0.2 μ m at whole silicon carbide deposit one layer thickness 2Passivation layer, deposition thickness is that the Al of 1.0 μ m is as P again +Ohmic contact regions 5 and the barrier layer that the nitrogen ion injects form P through photoetching and etching +The ohmic contact injection region;

(8.2) under 650 ℃ ambient temperature, carry out four aluminium ions and inject, inject energy and be respectively 280keV, 180keV, 100keV and 40keV, corresponding dosage is 4.8 * 10 14Cm -2, 4.0 * 10 14Cm -2, 3.5 * 10 14Cm -2With 2.7 * 10 14Cm -2

(8.3) adopt RCA standard cleaning epitaxial wafer, do the protection of C film after the oven dry, in 1700 ℃ of argon atmospheres, do ion-activated annealing, the time is 15min.

Step 9. is at P +The layer near P +Ohmic contact regions carries out repeatedly selectivity nitrogen ion and injects, and forms N +The source region is like Fig. 3 i.

(9.1) using the low pressure chemical vapor deposition mode is the SiO of 0.2 μ m at whole silicon carbide deposit one layer thickness 2Passivation layer, deposition thickness is that the Al of 0.5 μ m is used as N again +The barrier layer that the nitrogen ion injects in the source region 5 forms N through photoetching and etching +The injection region, source;

(9.2) under 500 ℃ ambient temperature, carry out 3 nitrogen ions and inject, inject energy and be respectively 180keV, 100keV and 30keV, corresponding dosage is 3.8 * 10 15Cm -2, 2.5 * 10 15Cm -2With 1.6 * 10 15Cm -2

(9.3) adopt the RCA standard of cleaning that silicon carbide is cleaned, do the protection of C film after the oven dry, in 1750 ℃ of argon atmospheres, make ion-activated annealing 15min.

Step 10. is carried out oxidation technology at whole silicon carbide, forms gate oxidation films, like Fig. 3 j.

Earlier 1200 ℃ of following dry-oxygen oxidations 1.5 hours,, form the gate oxidation films of 50nm, then through the SiO among photoetching, etching formation Fig. 2 again 950 ℃ of following wet-oxygen oxidations 1 hour 2Medium of oxides.

Step 11. deposit forms the heavily doped polysilicon gate of phosphonium ion, like Fig. 3 k.

With the polysilicon of low pressure hot wall chemical vapor deposition method at whole silicon carbide growth 150nm; Retain polysilicon on the gate oxidation films as grid through photoetching, etching then; The depositing technics condition is: deposition temperature is 600 ℃; Deposit pressure is 60Pa, and reacting gas adopts silane and hydrogen phosphide, and carrier gas adopts helium.

Step 12. formation source, leakage ohmic contact are like Fig. 3 l.

(12.1) resist coating in whole silicon carbide plate front forms N then through developing +And P +The ohmic contact zone, as source contacting metal district, the back side of whole carborundum is as the drain contact metal area;

(12.2) to the Al/Ti alloy of the obverse and reverse deposit 300nm/100nm of whole silicon carbide plate, peel off through ultrasonic wave afterwards and make positive formation source contact metal layer, the back side forms the drain contact metal level;

(12.3) under 1150 ℃ of temperature, to whole silicon carbide plate annealing 3 minutes, make source, drain contact metal level form ohmic contact in the nitrogen atmosphere.

Embodiment 2

Step 1. at N +Epitaxial growth N on the silicon carbide substrates sheet -Drift layer is like Fig. 3 a.

Be 500 μ m to thickness earlier, nitrogen ion doping doping content is 5 * 10 18Cm -3N +Type silicon carbide substrates sheet carries out the RCA standard cleaning, and on its front, using low pressure hot wall CVD method epitaxial growth thickness again is that 20 μ m, nitrogen ion doping concentration are 5 * 10 15Cm -3N -The extension drift layer, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen.

Step 2. at N -Epitaxial growth N on the drift layer +Current extending is like Fig. 3 b.

At N -The surperficial epitaxial growth thickness of epitaxial loayer is 0.5 μ m, and nitrogen ion doping concentration is 5 * 10 17Cm -3N +Current extending, its epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step 3. epitaxial growth N on current extending +Columnar region is like Fig. 3 c.

Using low pressure hot wall CVD method epitaxial growth thickness is that 20 μ m, nitrogen ion doping concentration are 1 * 10 16Cm -3N +Epitaxial loayer, epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step 4. adopt the ICP etching technics, to N +Etching is carried out in the both sides of epitaxial loayer, forms the P that treats extension +The post district, etching depth is 20 μ m; Like Fig. 3 d.

Adopt the ICP etching technics in the zone that etches, it is the P of 20 μ m that etching forms the degree of depth +The post district, the ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF 6And O 2Be respectively 48sccm and 12sccm.

Step 5. selective epitaxial growth P +The post district is like Fig. 3 e.

Using low pressure hot wall CVD method epitaxial growth thickness in the zone that etches is that 20 μ m, nitrogen ion doping concentration are 1 * 10 16Cm -3P +Epitaxial loayer, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a trimethyl aluminium.

Step 6 is identical with the step 6 of embodiment 1.

Step 7 is identical with the step 7 of embodiment 1.

Step 8 is identical with the step 8 of embodiment 1.

Step 9 is identical with the step 9 of embodiment 1.

Step 10 is identical with the step 10 of embodiment 1.

Step 11, deposit forms the heavily doped polysilicon gate of phosphonium ion, like Fig. 3 k.

With the polysilicon of low pressure hot wall chemical vapor deposition method at whole silicon carbide growth 150nm; Retain polysilicon on the gate oxidation films as grid through photoetching, etching then; The depositing technics condition is: deposition temperature is 700 ℃; Deposit pressure is 80Pa, and reacting gas adopts silane and hydrogen phosphide, and carrier gas adopts helium.

Step 12 is identical with the step 12 of embodiment 1.

Embodiment 3

Steps A. at N +Epitaxial growth N on the silicon carbide substrates sheet -Drift layer is like Fig. 3 a.

Be 350 μ m to thickness earlier, nitrogen ion doping doping content is 1 * 10 19Cm -3N +Type silicon carbide substrates sheet carries out the RCA standard cleaning, and on its front, using low pressure hot wall CVD method epitaxial growth thickness again is that 10 μ m, nitrogen ion doping concentration are 8 * 10 15Cm -3N -The extension drift layer, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen.

Step B. is at N -Epitaxial growth N on the drift layer +Current extending is like Fig. 3 b.

At N -The surperficial epitaxial growth thickness of epitaxial loayer is 0.1 μ m, and nitrogen ion doping concentration is 3 * 10 17Cm -3N +Current extending, its epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step C. is epitaxial growth N on current extending +Columnar region is like Fig. 3 c.

Using low pressure hot wall CVD method epitaxial growth thickness is that 10 μ m, nitrogen ion doping concentration are 1 * 10 17Cm -3N +Epitaxial loayer, epitaxial growth temperature are 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen;

Step D. adopts the ICP etching technics, to N +Etching is carried out in the both sides of epitaxial loayer, forms the P that treats extension +The post district, etching depth is 10 μ m; Like Fig. 3 d.

Adopt the ICP etching technics in the zone that etches, it is the P of 10 μ m that etching forms the degree of depth +The post district, the ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF 6And O 2Be respectively 48sccm and 12sccm.

Step e. selective epitaxial growth P +The post district is like Fig. 3 e.

Using low pressure hot wall CVD method epitaxial growth thickness in the zone that etches is that 10 μ m, nitrogen ion doping concentration are 1 * 10 17Cm -3P +The post district, its epitaxy technique condition is: temperature is 1600 ℃, and pressure 100mbar, reacting gas are silane and propane, and carrier gas is a pure hydrogen, and impurity source is a trimethyl aluminium.

Step F is identical with the step 6 of embodiment 1.

Step G is identical with the step 7 of embodiment 1.

Step H is identical with the step 8 of embodiment 1.

Step I is identical with the step 9 of embodiment 1.

Step J is identical with the step 10 of embodiment 1.

Step K. deposit forms the heavily doped polysilicon gate of phosphonium ion, like Fig. 3 k.

With the polysilicon of low pressure hot wall chemical vapor deposition method at whole silicon carbide growth 150nm; Retain polysilicon on the gate oxidation films as grid through photoetching, etching then; The depositing technics condition is: deposition temperature is 650 ℃; Deposit pressure is 70Pa, and reacting gas adopts silane and hydrogen phosphide, and carrier gas adopts helium.

Step L is identical with the step 12 of embodiment 1.

Claims (10)

1. the silicone carbide metal oxide semiconductor field effect pipe MOSFET based on half ultra knot comprises source electrode (1), grid (2), SiO 2Medium of oxides (3), N +Source region (4), P +Ohmic contact regions (5), P trap (6), JFET zone (7), N -Epitaxial loayer (11), N +Substrate (12) and drain electrode (13) is characterized in that:
N-epitaxial loayer (11) top is provided with current extending (10), the both sides of current extending (10) top and under P trap (6), be provided with P +Post district (8), two P +Post district (8) transverse width equates;
The below in JFET zone (7) is provided with N +Post district (9), this N +Post district (9) is positioned at two P +Between the post district (8), its width is two P +The width sum in post district (8);
Said P +Post district (8) and N +The doping content in post district (9) equates that being doping content is 1 * 10 16~ 3 * 10 17Cm -3Highly doped zone;
Said current extending (10) is 1 * 10 for doping content 17~ 5 * 10 17Cm -3The highly doped zone of N type, the path when vertically flowing to widen electric current.
2. the silicon carbide MOSFET device based on half ultra knot according to claim 1 is characterized in that: P +Post district (8) and N +The thickness in post district (9) equates, is 5 ~ 20 μ m.
3. the silicon carbide MOSFET device based on half ultra knot according to claim 1, it is characterized in that: the thickness of current extending (10) is 0.05 ~ 0.5 μ m.
4. the silicon carbide MOSFET device manufacture method based on half ultra knot comprises the steps:
(1) at N +Epitaxial growth thickness is 5 ~ 20 μ m on the front of silicon carbide substrates, and nitrogen ion doping concentration is 5 * 10 15~ 1 * 10 16Cm -3N -Epitaxial loayer;
(2) at N -The surperficial epitaxial growth thickness of epitaxial loayer is 0.05 ~ 0.5 μ m, and nitrogen ion doping concentration is 1 * 10 17~ 5 * 10 17Cm -3N +Current extending;
(3) at N +Epitaxial growth thickness is 5 ~ 20 μ m on the current extending, and nitrogen ion doping concentration is 1 * 10 16~ 3 * 10 17Cm -3N +Epitaxial loayer;
(4) adopt the ICP etching technics, to N +Etching is carried out in the both sides of epitaxial loayer, forms the P that treats extension +The post district, etching depth is 5 ~ 20 μ m;
(5) epitaxial growth thickness is 5 ~ 20 μ m on the zone that etches, and the aluminium ion doping content is 1 * 10 16~ 3 * 10 17Cm -3Epitaxial loayer form P +The post district;
(6) the positive epitaxial growth formation thickness at whole carborundum is 0.5 μ m, and the aluminium ion doping content is 5 * 10 15Cm -3P trap epitaxial loayer;
(7) the zone line ion injection degree of depth at P trap epitaxial loayer is 0.5 μ m, and doping content is 1 * 10 17Cm -3The nitrogen ion form the JFET district;
(8) at P +It is 0.5 μ m that the fringe region ion in post district injects the degree of depth, and doping content is 1 * 10 19Cm -3Aluminium ion form P +Ohmic contact regions;
(9) in the P trap near P +It is 0.25 μ m that the ohmic contact regions ion injects the degree of depth, and doping content is 1 * 10 19Cm -3The nitrogen ion, form N +The source region;
(10) technology that adopts dry-oxygen oxidation and wet-oxygen oxidation to combine at whole silicon carbide is carried out oxidation, forms the gate oxide of 50nm;
(11) whole silicon carbide use low pressure hot wall chemical vapor deposition method deposition thickness as the polysilicon of 150nm as grid, its deposition temperature is 600 ~ 700 ℃, pressure is 60 ~ 80Pa, reacting gas is silane and hydrogen phosphide, carrier gas is a helium;
(12) at P +Ohmic contact regions, N +Source region and whole carborundum back side deposition thickness are the Al/Ti alloy of 300nm/100nm, as the contact metal layer of source electrode and drain electrode, under 1100 ± 50 ℃ of temperature, in the nitrogen atmosphere whole carborundum annealing are formed Ohm contact electrode in 3 minutes then.
5. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4; Wherein chemical vapor deposition CVD method is all adopted in step (1), (2), (3); Its process conditions are: epitaxial growth temperature is 1600 ℃, and pressure is 100mbar, and reacting gas is silane and propane; Carrier gas is a pure hydrogen, and impurity source is a liquid nitrogen.
6. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4; Wherein chemical vapor deposition CVD method is all adopted in step (5), (6); Its process conditions are: epitaxial growth temperature is 1600 ℃, and pressure is 100mbar, and reacting gas is silane and propane; Carrier gas is a pure hydrogen, and impurity source is a trimethyl aluminium.
7. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4, wherein the related ICP etch technological condition of step (4) is: ICP coil power 850W, source power 100W, reacting gas SF 6And O 2Be respectively 48sccm and 12sccm.
8. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4, wherein the related ion implantation technology condition of step (8) is: implantation temperature: 650 ℃, ion-activated annealing temperature: 1750 ℃, annealing time: 10min.
9. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4, wherein the related ion implantation technology condition of step (9) is: implantation temperature: 500 ℃, ion-activated annealing temperature: 1750 ℃, annealing time: 10min.
10. the manufacture method based on the half ultra silicon carbide MOSFET device of tying according to claim 4, wherein the related oxidation technology condition of step (10) is: the dry-oxygen oxidation temperature: 1200 ℃, wet-oxygen oxidation temperature: 950 ℃.
CN2012103327533A 2012-09-10 2012-09-10 Silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) based on semi-super junction and manufacturing method CN102832248A (en)

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