CN113764510B - Low-turn-off-loss IGBT device with enhanced electron injection effect - Google Patents
Low-turn-off-loss IGBT device with enhanced electron injection effect Download PDFInfo
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- 238000002347 injection Methods 0.000 title claims abstract description 33
- 239000007924 injection Substances 0.000 title claims abstract description 33
- 230000000694 effects Effects 0.000 title claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- 238000009825 accumulation Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention discloses an electron injection effect enhanced IGBT device with low turn-off loss, which comprises: a collector, a P + collector region, an N + buffer region and a P + buried layer in the N + buffer region are sequentially grown from bottom to top; the N & lt- & gt drift region is positioned above the N & lt + & gt buffer region; a super junction structure consisting of first doping upright columns and second doping upright columns which are alternately arranged along a first direction is arranged in the N-drift region; a surface structure located over the N-drift region, the surface structure comprising: two trench gates; the P base region is positioned at the outer side of the trench gate, and the P-base region is positioned at the inner side of the trench gate; the first N + emitter and the first P + emitter are positioned in the P base region, and the first N + emitter is close to the trench gate; the second N + emitter and the second P + emitter are positioned in the P-base region, and the second N + emitter is close to the trench gate; the second N + emitter is symmetrically arranged on two sides of the second P + emitter; a top emitter connected to the second P + emitter.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an electron injection effect enhanced IGBT device with low turn-off loss.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a voltage-controlled power device, and since the IGBT has advantages of small driving power, reduced saturation voltage, and the like, it is widely used in various fields as a high-voltage switch.
The trench gate type structure IGBT can eliminate a parasitic Junction Field Effect Transistor (JFET) resistance of the planar gate type IGBT, and further reduce saturation voltage drop and on-state loss. In order to further reduce saturation voltage drop and on-state loss, injection-enhanced gate bipolar transistors (HIGT), electron injection-enhanced insulated gate bipolar transistors (IEGT), and wide-trench-gate-pitch or FP (Floating-Pbody) -IGBTs and the like have been proposed.
However, due to the negative gate capacitance effect of the FP-IGBT, the voltage generated in the FP structure changes when the device is turned on, and a displacement current is generated at the gate through the miller capacitance, which reduces the gate control capability of the IGBT and brings electromagnetic interference noise.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an electron injection effect enhanced IGBT device with low turn-off loss. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides an electron injection effect enhanced IGBT device with low turn-off loss, which comprises:
a collector structure comprising: a collector, a P + collector region, an N + buffer region and a P + buried layer in the N + buffer region are sequentially grown from bottom to top;
the N & lt- & gt drift region is positioned above the N & lt + & gt buffer region; a super junction structure is arranged in the N-drift region, and the super junction structure is a first doping upright column and a second doping upright column which are sequentially and alternately arranged along a first direction;
a surface structure located over the N-drift region, the surface structure comprising: two trench gates extending into the first doped column;
the P base region is positioned on the outer side of the trench gate, and the P-base region is positioned on the inner side of the trench gate;
the first N + emitter and the first P + emitter are positioned in the P base region, and the first N + emitter is close to the trench gate; the P base region corresponds to the first doping upright column in a first direction;
the second N + emitter and the second P + emitter are positioned in the P-base region, and the second N + emitter is close to the trench gate; the second N + emitter electrodes are connected through polycrystalline silicon and symmetrically arranged on two sides of the second P + emitter electrode; the P-base region, the second doping upright post and the P + buried layer correspond to each other in a second direction;
and the top emitter covers the P base region, the P-base region, the trench gate, the first N + emitter, the first P + emitter, the second N + emitter and the second P + emitter, and is connected with the second P + emitter.
Optionally, the first doped column is an N-type doped column; the second doped column is a P-type doped column.
Optionally, the length of the second doped column in the first direction is the same as the length of the P + buried layer in the first direction.
Optionally, the length of the P + buried layer in the first direction is 8 μm, and the doping concentration is 1 × 10 17 cm -3 ；
The length of the first doping upright post in the first direction is 8 mu m, and the doping concentration is 3 multiplied by 10 15 cm -3 。
Optionally, the length of the second doped column in the first direction is 8 μm, and the doping concentration is 3 × 10 15 cm -3 。
Optionally, the trench gate further includes; the gate structure comprises a gate groove, a gate oxide layer and a gate, wherein the gate oxide layer is used for isolating the gate and the P base region.
Optionally, the length of the gate trench in the second direction is 4 μm.
Optionally, the length of the second N + emitter in the second direction is 2 μm, and the doping concentration is 1.2 × 10 16 cm -3 。
Optionally, the doping concentration of the P base region is 2 × 10 17 cm -3 (ii) a The doping concentration of the P + collector is 1 multiplied by 10 17 cm -3 。
Optionally, the doping concentration of the N + buffer region is 5 × 10 16 cm -3 。
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the low turn-off loss electron injection effect enhanced IGBT device, the P + buried layer in the N + buffer area is heavily doped, amplification of hole current when the hole current passes through the P + buried layer is guaranteed, the electron injection effect of the device is further enhanced, and the saturation voltage drop of the device is reduced. Meanwhile, due to the amplification of the hole current, the injection efficiency of the hole is improved, the doping concentration of the P + collector electrode can be further reduced, and the leakage current of the device is further reduced, so that the low leakage current and the high reliability of the device are ensured. The P + buried layer is beneficial to reducing the possibility of secondary breakdown between the N & lt- & gt drift region and the N & lt + & gt buffer region when the device is blocked in the forward direction. Because of the current concentration phenomenon of the traditional IGBT, a new electric field peak value is formed between the N-type drift region and the N-type buffer layer of the device, secondary avalanche breakdown occurs, the breakdown voltage of the device is reduced, and the P + buried layer enables hole current injected from the collector electrode to be more uniform, so that the possibility of avalanche secondary breakdown is reduced.
According to the scheme provided by the invention, the P-channel JFET composed of the P-base region, the second N + emitter and the second P + emitter is used, when the device is conducted in the forward direction, the second N + emitter is very high in potential, the second N + emitter is depleted towards the P-base region to form a depletion layer, and a hole channel disappears, so that holes injected from the P + collector are accumulated below the second N + emitter, the electron injection effect of the device is enhanced, and the saturation voltage drop of the device is reduced.
In addition, the super-junction structure in the N-drift region is formed by sequentially and alternately arranging the N-type doped columns and the P-type doped columns, so that depletion regions can be formed in the super-junction structure due to mutual charge depletion, and the breakdown voltage of the device is improved. Meanwhile, the length of the P-type doped column in the first direction is the same as that of the P + buried layer in the first direction, and is above the P + buried layer, so that most of the hole current can be directed to the P-type doped column. When the device is in a forward conduction state, a PN junction is formed between the P + buried layer and the N + buffer region, the potential on the N-type doped stand column in the first direction is higher than that of the P-type doped stand column, so that a transverse electric field of the super junction structure is stronger, holes in the N-type stand column are extracted and flow to the P-type stand column, accumulation is carried out in the P-base region or below the P-base region, the electron injection effect of the device is further enhanced, and the saturation voltage drop of the device is further reduced. When the device is in an off state, particularly when the device is turned off through negative gate voltage, the P-base region and the second N + emitter form a positive bias structure, a hole channel of the P-channel JFET structure is opened, a part of holes flow into the top emitter from the second P + emitter, holes in the P-base region can be extracted, and then turn-off loss of the device is reduced.
The present invention will be described in further detail with reference to the drawings and examples.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of an electron injection effect enhanced IGBT device with low turn-off loss according to an embodiment of the present invention.
Detailed Description
In order to reduce turn-off loss of the IGBT device and enhance the electron injection effect of the device, embodiments of the present invention provide an electron injection effect enhanced IGBT device with low turn-off loss, and the scheme provided in the embodiments will be described in detail below with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
An embodiment of the present invention provides an electron injection effect enhanced IGBT device with low turn-off loss, and referring to fig. 1, fig. 1 is a schematic structural diagram of an electron injection effect enhanced IGBT device with low turn-off loss according to an embodiment of the present invention, including:
a collector structure comprising: a collector 111, a P + collector region 112, an N + buffer region 113, and a P + buried layer 114 in the N + buffer region 113, which are formed by growing in order from bottom to top.
For convenience of understanding, in the embodiment of the present invention, the first direction is a horizontal direction in fig. 1, and the second direction is a vertical direction in fig. 1.
The P + buried layer 114 is disposed in the N + buffer region 113, and does not contact the collector 111 and the P + collector region 112.
An N-drift region located above the N + buffer region 113; the N-drift region is provided with a super junction structure, and the super junction structure is a first doping upright post 101 and a second doping upright post 102 which are sequentially and alternately arranged along a first direction.
For example, in a cell structure, the N-drift region may include two first doped columns and one second doped column.
And a surface structure located on the N-drift region 113.
The surface structure includes: two trench gates 121, the trench gates 121 extending into the first doped column 101.
A P base region 141 and a P base region 142, wherein the P base region 141 is positioned at the outer side of the trench gate 121, and the P base region 142 is positioned at the inner side of the trench gate 121;
a first N + emitter 151 and a first P + emitter 152 in the P base region 141, wherein the first N + emitter 151 is close to the trench gate 121; the P-base region 141 corresponds to the first doped column 101 in the first direction.
A second N + emitter 153 and a second P + emitter 154 in the P-base region 142, wherein the second N + emitter 154 is close to the trench gate 121; the second N + emitter 153 is connected by polysilicon and symmetrically disposed on both sides of the second P + emitter 154; the P-base region 142, the second doped column 102, and the P + buried layer 114 correspond in a second direction.
A P-channel JFET consisting of a P-base region, a second N + emitter and a second P + emitter is arranged in the surface structure, and the device is uniformly doped.
The P base region 141, the trench gate 121, and the P-base region 142 are sequentially disposed in the first direction. The first doped column 101 corresponds to the P-base region 141 in the second direction, and the second doped column 102, the P-base region 142, and the P + buried layer 114 correspond in the second direction.
The first N + emitter 151 and the first P + emitter 152 are below the upper surface of the P base region 141; a second N + emitter 153 and a second P + emitter 154 are below the upper surface of the P-base region 142.
And a top emitter 161 covering the P base region 141, the P base region 142, the trench gate 121, the first N + emitter 151, the first P + emitter 152, the second N + emitter 153, and the second P + emitter 154, wherein the top emitter 161 is connected to the second P + emitter 154.
The top emitter 161 is located above the surface structure in the second direction.
According to the electric neutral principle, the IGBT needs to inject more electrons from the first N + emitter, namely the electron injection enhancement effect, and the electrons and holes are subjected to conductance modulation, so that the saturation conduction voltage drop of the device is reduced.
According to the low turn-off loss electron injection effect enhanced IGBT device provided by the embodiment of the invention, the P + buried layer in the N + buffer area is heavily doped, so that the hole current is amplified when passing through the P + buried layer, the electron injection effect of the device is enhanced, and the saturation voltage drop of the device is reduced. Meanwhile, due to the amplification of the hole current, the injection efficiency of the hole is improved, the doping concentration of the P + collector electrode can be further reduced, and the leakage current of the device is further reduced, so that the low leakage current and the high reliability of the device are ensured. The P + buried layer is beneficial to reducing the possibility of secondary breakdown between the N & lt- & gt drift region and the N & lt + & gt buffer region when the device is blocked in the forward direction. Because of the current concentration phenomenon of the traditional IGBT, a new electric field peak value is formed between the N-type drift region and the N-type buffer layer of the device, secondary avalanche breakdown occurs, the breakdown voltage of the device is reduced, and the P + buried layer enables hole current injected from the collector electrode to be more uniform, so that the possibility of avalanche secondary breakdown is reduced.
According to the scheme provided by the embodiment of the invention, the P-channel JFET formed by the P-base region, the second N + emitter and the second P + emitter is high in potential when the device is conducted in the forward direction, the second N + emitter is depleted towards the P-base region to form a depletion layer, and a hole channel disappears, so that a hole injected from the P + collector is accumulated below the second N + emitter, the electron injection effect of the device is enhanced, and the saturation voltage drop of the device is reduced. When the device is in an off state, particularly when the device is turned off through negative gate voltage, the P-base region and the second N + emitter form a positive bias structure, a hole channel of the P-channel JFET structure is opened, a part of holes flow into the top emitter from the second P + emitter, holes in the P-base region can be extracted, and then the turn-off loss of the device is reduced.
With continued reference to fig. 1, in the embodiment of the present invention, the first doped column 101 is an N-type doped column; the second doped column 102 is a P-type doped column.
In an embodiment of the present invention, the length of the second doped column 102 in the first direction is the same as the length of the P + buried layer 114 in the first direction.
The length of the super junction structure in the N-drift region in the first direction is the same as the width of a mesa of the device.
In the embodiment of the invention, the super junction structure in the N-drift region is formed by sequentially and alternately arranging the N-type doped stand columns and the P-type doped stand columns, so that a depletion region can be formed in the super junction structure due to mutual charge depletion, and the breakdown voltage of a device is improved. Meanwhile, the length of the P-type doped column in the first direction is the same as that of the P + buried layer in the first direction, and is above the P + buried layer, so that most of the hole current can be directed to the P-type doped column. When the device is in a forward conduction state, a PN junction is formed between the P + buried layer and the N + buffer area, so that conduction voltage drop of 0.7V is caused, the potential on the N-type doped stand column in the first direction is higher than that of the P-type doped stand column, a transverse electric field of the super junction structure is stronger, holes in the N-type stand column are extracted and flow to the P-type stand column, accumulation is carried out in the P-base area or below the P-base area, the electron injection effect of the device is further enhanced, and further the saturation voltage drop of the device is reduced.
Alternatively, the P + buried layer 114 has a length of 8 μm in the first direction and a doping concentration of 1 × 1017 cm-3.
The length of the first doped column 101 in the first direction is 8 μm and the doping concentration is 3 × 1015 cm-3.
In the embodiment of the present invention, the length of the second doped column 102 in the first direction is 8 μm, and the doping concentration is 3 × 1015 cm-3.
In the embodiment of the present invention, the trench gate 121 further includes; gate trench, gate oxide 131, gate oxide 131 is used for isolating gate and P base region 141.
Wherein the second N + emitter 153 is connected to the trench gate 121 through the gate oxide layer 131. The material of the gate oxide layer may comprise silicon dioxide.
In the embodiment of the invention, the length of the gate groove in the second direction is 4 μm.
In the embodiment of the present invention, the length of the second N + emitter 154 in the second direction is 2 μm, and the doping concentration is 1.2 × 1016 cm-3.
In the embodiment of the invention, the doping concentration of the P base region 141 is 2 multiplied by 1017 cm-3; the doping concentration of the P + collector 112 is 1 x 1017 cm-3.
In the embodiment of the invention, the doping concentration of the N + buffer region 113 is 5X 1016 cm-3.
Optionally, the semiconductor material used for the device provided by the embodiment of the present invention may include polysilicon and silicon carbide.
Compared with the traditional structure, the low turn-off loss enhanced IGBT device provided by the invention is additionally provided with the P + buried layer, and the collector current can be amplified, so that the doping concentration of the collector is reduced; the super junction structure is added, so that the breakdown voltage of the device can be improved, and the hole accumulation effect can be enhanced; the P-channel JFET structure is added, so that the hole accumulation effect of the device is stronger in a conducting state, and the holes are extracted through the second P + emitter in a switching-off state, so that the compromise between the conducting saturation voltage drop and the switching loss can be better realized.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (9)
1. An electron injection effect enhanced IGBT device with low turn-off loss, comprising:
a collector structure comprising: a collector, a P + collector region, an N + buffer region and a P + buried layer in the N + buffer region are sequentially grown from bottom to top;
the N & lt- & gt drift region is positioned above the N & lt + & gt buffer region; a super junction structure is arranged in the N-drift region, and the super junction structure is a first doping upright column and a second doping upright column which are sequentially and alternately arranged along a first direction; the first doped upright post is an N-type doped upright post; the second doped upright post is a P-type doped upright post;
a surface structure located over the N-drift region, the surface structure comprising: two trench gates extending into the first doped column;
the P base region is positioned on the outer side of the trench gate, and the P-base region is positioned on the inner side of the trench gate;
the first N + emitter and the first P + emitter are positioned in the P base region, and the first N + emitter is close to the trench gate; the P base region corresponds to the first doping upright column in a second direction;
the second N + emitter and the second P + emitter are positioned in the P-base region, and the second N + emitter is close to the trench gate; the second N + emitter is connected with the grid electrode through polycrystalline silicon and symmetrically arranged on two sides of the second P + emitter; the P-base region, the second doping upright post and the P + buried layer correspond to each other in a second direction;
and the top emitter covers the P base region, the P-base region, the trench gate, the first N + emitter, the first P + emitter, the second N + emitter and the second P + emitter, and is connected with the second P + emitter, the first N + emitter and the first P + emitter.
2. The low turn-off loss electron injection effect enhanced IGBT device of claim 1, wherein the length of the second doped column in the first direction is the same as the length of the P + buried layer in the first direction.
3. The low turn-off loss electron injection effect enhanced IGBT device according to claim 2,
the P + buried layer has a length of 8 μm in the first direction and a doping concentration of 1 × 10 17 cm -3 ；
The length of the first doping upright post in the first direction is 8 mu m, and the doping concentration is 3 multiplied by 10 15 cm -3 。
4. The low turn-off loss electron injection enhanced IGBT device of claim 1 wherein the second doped column has a length of 8 μ ι η in the first direction and a doping concentration of3×10 15 cm -3 。
5. The low turn-off loss electron injection enhanced IGBT device of claim 1 wherein the trench gate further comprises; the gate structure comprises a gate groove, a gate oxide layer and a gate, wherein the gate oxide layer is used for isolating the gate and the P base region.
6. The low turn-off loss electron injection enhanced IGBT device according to claim 5, wherein the gate trench has a length of 4 μm in the second direction.
7. The low turn-off loss electron injection enhanced IGBT device according to claim 1, wherein the second N + emitter has a length of 2 μm in the second direction and a doping concentration of 1.2 x 10 16 cm -3 。
8. The low turn-off loss electron injection enhanced IGBT device according to claim 1, wherein the doping concentration of the P base region is 2 x 10 17 cm -3 (ii) a The doping concentration of the P + collector is 1 multiplied by 10 17 cm -3 。
9. The low turn-off loss electron injection enhanced IGBT device according to claim 1, wherein the doping concentration of said N + buffer region is 5 x 10 16 cm -3 。
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