CN107507861B - Schottky contact injection enhanced SiC PNM-IGBT device and preparation method thereof - Google Patents
Schottky contact injection enhanced SiC PNM-IGBT device and preparation method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention relates to a novel Schottky contact injection enhancement type SiC PNM-IGBT device and a preparation method thereof. The preparation method comprises the following steps: continuously growing a transition layer, a first drift layer, a buffer layer and a collector layer on the SiC substrate; etching the first drift layer to form a first groove, and depositing a first oxide layer; growing a second drift layer; growing a P-type well region on the second drift layer, and forming a P + doped region, a P contact region and an N + emission region in the P-type well region; etching to prepare a second groove and form a buried oxide layer; growing a second oxide layer in the second groove, and depositing polycrystalline silicon; and depositing a metal layer to form an emitter ohmic contact electrode, an emitter Schottky contact electrode and a collector contact electrode respectively. The buried oxide layers are introduced into the two sides of the groove gate, and the Schottky contact electrode is introduced into the emitter, so that the conductance modulation effect is enhanced, the on-resistance is reduced, the turn-off time is not obviously increased, and the method is compatible with the conventional process in terms of process.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a Schottky contact injection enhancement type SiC PNM-IGBT device and a preparation method thereof.
Background
With the increasing demand of electronic products and the increasing demand of energy efficiency, power devices play an increasingly important role. The present invention relates to a device for use in almost all electronic manufacturing industries including the computer field, the network communication field, the consumer electronics field, and the industrial control field. The market of Chinese power devices keeps a faster development speed all the time, the novel power devices in China mainly comprise VDMOS (vertical double-diffused metal oxide semiconductor) and IGBT (insulated gate bipolar transistor) devices, and the novel material power devices mainly comprise SiC and GaN devices. The SiC is a typical wide-bandgap semiconductor material, has the characteristics of large forbidden band width, high critical electric field, high carrier saturation velocity, stable physicochemical properties, high hardness, good thermal stability, high thermal conductivity and the like, and is very suitable for manufacturing power devices with high temperature, radiation resistance, high frequency, high power and high density integration. An Insulated Gate Bipolar Transistor (IGBT) is a novel composite power device developed on the basis of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT), combines the advantages of the MOSFET and the BJT, has the functions of metal oxide semiconductor field effect transistor (MOS) input and Bipolar output, and integrates the advantages of the BJT device such as small on-state voltage drop, large current-carrying density, high voltage resistance, small driving power of the power MOSFET, high switching speed, high input impedance and good thermal stability.
The SiC IGBT integrates the characteristics of low power consumption, high breakdown voltage and high switching speed, has obvious advantages compared with SiC MOSFET and silicon-based devices such as IGBT, thyristor and the like, and is particularly suitable for the application fields of high-temperature, high-voltage, high-frequency and high-power systems. SiC MOS devices have been developed to provide devices with high breakdown voltage and low interface state density, which provides conditions for the development of SiC IGBTs. In recent years, with the increasing of energy saving and emission reduction and the continuous development of new energy fields, the IGBT as an energy-saving high-efficiency device has a wider development space.
Like other power devices, SiC IGBTs are primarily concerned with the effects of power consumption and voltage. To reduce the power consumption of the device, the on-resistance can be reduced, thus requiring a higher concentration of free carriers in the drift region of the device in the on-state. However, the large number of free carriers results in a device with a longer turn-off time, increasing the turn-off loss of the device, and causing a conflict between the on-resistance and the turn-off loss.
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides an injection enhancement type SiCPNM-IGBT device and a preparation method thereof.
Specifically, a method for manufacturing an injection enhancement type SiC PNM-IGBT device according to an embodiment of the present invention includes:
continuously growing a transition layer, a first drift layer, a buffer layer and a collector layer on the surface of the SiC substrate by using a hot wall LPCVD (low pressure chemical vapor deposition) process;
etching the first drift layer by utilizing a reactive ion etching process to form a first groove, and growing a first oxide layer in the first groove by utilizing a thermal oxidation process;
growing a second drift layer on the surfaces of the first drift layer and the first oxide layer by utilizing a hot-wall LPCVD (low pressure chemical vapor deposition) process;
growing a P-type well region on the surface of the second drift layer by utilizing a hot wall LPCVD (low pressure chemical vapor deposition) process;
forming a P + doped region, a P contact region and an N + emitter region in the P-type well region by using an ion implantation process;
etching the second drift layer and the first oxide layer by utilizing a reactive ion etching process to form a second groove so as to prepare a buried oxide layer; wherein the width of the second trench is smaller than the width of the first trench;
growing a second oxide layer in the second groove by utilizing a thermal oxidation process, and growing polycrystalline silicon on the second oxide layer by utilizing a CVD (chemical vapor deposition) process;
depositing a metal layer to form emitter ohmic contact electrodes in the N + emitter regions respectively and form emitter Schottky contact electrodes in the P contact regions;
the deposited metal layer forms a collector contact electrode.
In one embodiment of the present invention, growing a first oxide layer within the first trench using a thermal oxidation process includes:
continuously growing the first oxide layer in the first trench until the depth of the first oxide layer is flush with the first drift layer;
removing the first oxide layer on the first drift layer;
and carrying out planarization treatment on the first oxide layer and the first drift layer.
In an embodiment of the present invention, before growing the first oxide layer in the first trench by using a thermal oxidation process, the method further includes:
and removing the SiC substrate and the transition layer by utilizing a CMP process.
In one embodiment of the present invention, growing a P-type well region on the surface of the second drift layer by using a hot wall LPCVD process includes:
using a hot-wall LPCVD process in saidThe second drift layer has a growth depth of 0.5-2 μm and an aluminum ion doping concentration of 1 × 1017～1×1018cm-3The P-type well region.
In one embodiment of the present invention, forming a P + doped region, a P contact region, and an N + emitter region in the P-type well region by using an ion implantation process includes:
forming a depth of 0.1-0.5 μm and an aluminum ion doping concentration of 1 × 10 in the P-type well region by ion implantation19～1×1021cm-3The P + doped region of (a);
forming a depth of 0.01-0.1 μm and an aluminum ion doping concentration of 2 × 10 in the P-type well region by ion implantation17～1×1018cm-3The P contact region of (a);
forming a depth of 0.1-0.5 μm and a nitrogen ion doping concentration of 1 × 10 in the P-type well region by ion implantation18～1×1020cm-3The N + emitter region.
In one embodiment of the present invention, the width of the second trench is smaller than the width of the first trench.
In one embodiment of the present invention, depositing a metal layer to form an emitter ohmic contact electrode includes:
depositing photoresist on the surface of the whole device, developing to form an emitter ohmic contact metal window, depositing Ni/Ti/Al alloy on the surface of the whole device, and forming an emitter ohmic contact metal layer by utilizing an ultrasonic stripping process;
and annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃ to form the emitter ohmic contact electrode.
In one embodiment of the invention, depositing a metal layer to form an emitter schottky contact electrode includes:
and depositing photoresist on the surface of the whole device, developing to form an emitter Schottky contact metal window, depositing metal Ni on the surface of the whole device, and forming the emitter Schottky contact electrode by utilizing an ultrasonic stripping process.
In one embodiment of the present invention, depositing a metal layer to form a collector contact electrode includes:
depositing Ti/Al alloy on the lower surface of the collector layer to form collector contact metal;
the collector contact electrode was formed by annealing in a nitrogen atmosphere at a temperature of 1050 c for 3 minutes.
Another embodiment of the present invention provides an injection enhancement type SiC PNM-n-IGBT device, including: the injection enhancement type SiC PNM-IGBT device comprises a collector layer, a buffer layer, a drift layer, a P-type well region, a P + doped region, a P contact region, an N + emitter region, a buried oxide layer, an emitter ohmic contact electrode, an emitter Schottky contact electrode and a collector contact electrode, wherein the buried oxide layer is located in the drift layer, and the injection enhancement type SiC PNM-IGBT device is prepared by the method of the embodiment.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
FIG. 1 is a process flow diagram of an injection enhancement type SiC PNM-IGBT device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an injection enhanced SiC PNM-n-IGBT device provided by an embodiment of the invention;
3 a-3 q are schematic diagrams of a process for implanting an enhancement mode SiC PNM-n-IGBT device according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an injection enhanced SiC PNM-p-IGBT device provided by an embodiment of the invention;
fig. 5a to fig. 5n are schematic diagrams of a process for implanting an enhancement mode SiC PNM-p-IGBT device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Example one
Referring to fig. 1, fig. 1 is a process flow diagram of a schottky contact injection enhancement SiC PNM-IGBT device according to an embodiment of the present invention. The method comprises the following steps:
a, continuously growing a transition layer, a first drift layer, a buffer layer and a collector layer on the surface of the SiC substrate by using a hot-wall LPCVD (low pressure chemical vapor deposition) process;
b, etching the first drift layer by utilizing a reactive ion etching process to form a first groove, and growing a first oxide layer in the first groove by utilizing a thermal oxidation process;
c, growing a second drift layer on the surfaces of the first drift layer and the first oxide layer by utilizing a hot-wall LPCVD (low pressure chemical vapor deposition) process;
d, growing a P-type well region on the surface of the second drift layer by utilizing a hot wall LPCVD (low pressure chemical vapor deposition) process;
step e, forming a P + doped region, a P contact region and an N + emission region in the P-type well region by utilizing an ion implantation process;
f, etching the second drift layer and the first oxide layer by utilizing a reactive ion etching process to form a second groove so as to prepare a buried oxide layer;
step g, growing a second oxide layer in the second trench by utilizing a thermal oxidation process, and growing polycrystalline silicon on the second oxide layer by utilizing a CVD (chemical vapor deposition) process;
h, depositing a metal layer to form an emitter ohmic contact electrode, an emitter Schottky contact electrode and a collector contact electrode respectively;
wherein, for step b, the method can comprise the following steps:
continuously growing the first oxide layer in the first trench until the depth of the first oxide layer is flush with the first drift layer;
removing the first oxide layer on the first drift layer;
and carrying out planarization treatment on the first oxide layer and the first drift layer.
Further, before step b, the method may further include:
and removing the SiC substrate and the transition layer by utilizing a CMP process.
Wherein, for step d, may include:
growing the second drift layer to a depth of 0.5-2 μm and an aluminum ion doping concentration of 1 × 10 by hot wall LPCVD17～1×1018cm-3The P-type well region.
Wherein, for step e, may include:
forming a depth of 0.1-0.5 μm and an aluminum ion doping concentration of 1 × 10 in the P-type well region by ion implantation19～1×1021cm-3The P + doped region of (a);
forming a depth of 0.01-0.1 μm and an aluminum ion doping concentration of 2 × 10 in the P-type well region by ion implantation17～1×1018cm-3The P contact region of (a);
forming a depth of 0.1-0.5 μm and a nitrogen ion doping concentration of 1 × 10 in the P-type well region by ion implantation18～1×1020cm-3The N + emitter region.
Wherein, for the second trench in step f, the method may include:
the width of the second trench is smaller than the width of the first trench.
Wherein, for the step h of depositing the metal layer to form the emitter ohmic contact electrode, the method may include:
depositing photoresist on the surface of the whole device, developing to form an emitter ohmic contact metal window, depositing Ni/Ti/Al alloy on the surface of the whole device, and forming an emitter ohmic contact metal layer by utilizing an ultrasonic stripping process;
and annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃ to form the emitter ohmic contact electrode.
Wherein, for the step h of depositing the metal layer to form the emitter schottky contact electrode, the method may include:
and depositing photoresist on the surface of the whole device, developing to form an emitter Schottky contact metal window, depositing metal Ni on the surface of the whole device, and forming the emitter Schottky contact electrode by utilizing an ultrasonic stripping process.
Wherein, for the step h of depositing the metal layer to form the collector contact electrode, the method may include:
depositing Ti/Al alloy on the lower surface of the collector layer to form collector contact metal;
the collector contact electrode was formed by annealing in a nitrogen atmosphere at a temperature of 1050 c for 3 minutes.
In this embodiment, the processing technology at least has the following advantages:
1) the introduction of the buried oxide layer is equivalent to thickening the bottom of the grid electrode, so that a bottleneck effect is brought, a hole blocking effect is achieved, a conductance modulation effect is enhanced, a device has smaller conduction voltage drop under large current, and current carriers on one side of the emitter can be quickly swept out under the action of a strong electric field during turn-off, so that the turn-off time is not obviously prolonged.
2) According to the invention, the potential of the base region is raised by the Schottky barrier, so that the effect of blocking holes is achieved, the conductance modulation effect is enhanced, the device has smaller conduction voltage drop under large current, and the turn-off loss is not increased due to the forward conduction characteristic of the Schottky diode in an exponential form.
3) Compared with other new structures improved for enhancing conductance modulation, the new structure provided by the invention is compatible with the traditional process in the manufacturing process and has higher feasibility.
Example two
Referring to fig. 2, fig. 2 is a schematic diagram of a schottky contact injection enhancement SiC PNM-n-IGBT device according to an embodiment of the present invention.
The device structure comprises a collector layer 201, a buffer layer 202, a drift layer 203, a P-type well region 204, a P + doped region 205, a P contact region 206, an N + emitter region 207, a buried oxide layer 208, an emitter ohmic contact electrode 209, an emitter Schottky contact electrode 210 and a collector contact electrode 211, wherein the buried oxide layer 208 is positioned in the drift layer.
Preferably, the collector layer 201 is a P + collector layer, the buffer layer 202 is an N + buffer layer, and the drift layer 203 is an N-drift layer.
The working principle and the beneficial effects of the invention are as follows:
the invention provides a Schottky contact injection enhancement type SiC PNM-IGBT device. Compared with the traditional SiC IGBT, the buried oxide layers are introduced at the two sides of the groove gate, namely the bottom of the gate is thickened, and due to the bottleneck effect, the device plays a role in blocking holes under the condition that the space between the groove gates is not required to be reduced, so that the conductivity modulation effect is enhanced, the on-resistance is reduced, and as the current carriers at one side of the emitter can be quickly swept out under the action of a strong electric field during turn-off, the turn-off time cannot be obviously prolonged, and the technology is compatible with the existing technology.
In addition, the emitter contact electrode is divided into two parts, the contact part of the metal and the N + emitter region is in ohmic contact, and the contact part of the metal and the P contact region is in Schottky contact. The Schottky barrier raises the potential of the P-type well region, and plays a role in blocking holes, so that the conductance modulation effect is enhanced, the resistance of the N-drift region is reduced, and the device has smaller conduction voltage drop under large current. In the turn-off process, the grid voltage is gradually reduced to 0, the partial pressure of the device is gradually increased along with the gradual reduction of the current, and due to the forward conduction characteristic of the Schottky diode in the form of the index, the holes cannot be blocked to flow out, but the holes flow out more quickly, so that the turn-off time cannot be increased, and the switching loss can be reduced. A layer of medium-concentration doped P contact region is arranged between the P + doped region and the metal and can be realized by regulating and controlling the ion implantation energy and the depth, and the medium-concentration doped P contact region is manufactured to form ideal Schottky contact.
EXAMPLE III
Referring to fig. 3a to fig. 3q, fig. 3a to fig. 3q are schematic process diagrams of a novel schottky contact injection enhancement SiC PNM-n-IGBT device according to an embodiment of the present invention, and on the basis of the above embodiment, the present embodiment will describe the process flow of the present invention in more detail. The method comprises the following steps:
s301, selecting an N + SiC substrate 001, and carrying out RCK standard cleaning on the N + SiC substrate 301, as shown in FIG. 3 a;
s302, growing a transition layer 302 with the thickness of 10-30 μm on the N + SiC substrate 301 by using a hot wall LPCVD process, wherein the thickness of the transition layer 302 can also be selected to be 20 μm, as shown in FIG. 3 b;
s303, extending the transition layer 302 by a hot wall LPCVD process to a thickness of 100-200 μm and a nitrogen ion doping concentration of 1 × 1014～1×1015cm-3Wherein the thick bottom of the first drift layer 303 can be 135 μm, and the doping concentration of nitrogen ions can be 2 × 1014cm-3As shown in fig. 3 c;
s304, extending the first drift layer 303 by a hot wall LPCVD process to a thickness of 1-10 μm and a nitrogen ion doping concentration of 1 × 1016～1×1018cm-3The thickness of the buffer layer 304 can be selected to be 3 μm, and the doping concentration of nitrogen ions can be selected to be 1 × 1017cm-3As shown in fig. 3 d;
s305, utilizing a hot wall LPCVD process to epitaxially grow a buffer layer 304 with a thickness of 3-5 μm and an aluminum ion doping concentration of 1 × 1018～1×1020cm-3The collector layer 305, wherein the doping concentration of aluminum ions can be selected to be 1 × 1019cm-3As shown in fig. 3 e;
s306, removing the SiC substrate 301 and the transition layer 302 by utilizing a CMP process, as shown in FIG. 3 f;
s307, etching the first drift layer 303 by using a reactive ion etching process to form a first groove 306 with the depth of 1-10 μm, as shown in FIG. 3 g;
s308, depositing a first oxide layer 307 on the first trench 306 by using a thermal oxidation process, grinding off the oxide on the first drift layer, only keeping the oxide inside the first trench, and performing planarization treatment on the surfaces of the first drift layer 303 and the first oxide layer 307, as shown in FIG. 3 h;
s309, epitaxially growing the first drift layer 303 and the first oxide layer 307 on the surfaces of the first drift layer 303 and the first oxide layer 307 by a hot-wall LPCVD process, wherein the thickness of the nitrogen is 1-20 mu mThe ion doping concentration is 1 × 1014～1×1015cm-3Wherein the thickness of the second drift layer 308 can be selected to be 5 μm, and the doping concentration of nitrogen ions can be selected to be 2 × 1014cm-3For convenience of illustration, the first drift layer 303 and the second drift layer 308 are collectively referred to as a drift layer 3001, as shown in fig. 3 i;
s310, epitaxially growing on the drift layer 3001 to a depth of 0.5-2 μm and an aluminum ion doping concentration of 1 × 10 by a hot wall LPCVD process17～1×1018cm-3The depth of the P-type well 309 can be selected to be 1 μm, 1.5 μm, and the doping concentration of aluminum ion can be selected to be 3 × 1017cm-3、8×1017cm-3As shown in FIG. 3 j;
s311, selectively implanting aluminum ions for multiple times in the P-type well region 309 by using an ion implantation process, and controlling the implantation dose and the corresponding energy to form a silicon-doped19～1×1021cm-3The P + doped region 310 is formed to have a thickness of 0.01 to 0.1 μm and an aluminum ion doping concentration of 2 × 1017～1×1018cm-3Wherein the concentration of the P contact region 311 is less than that of the P + doped region 310, as shown in fig. 3 k;
s312, selectively implanting nitrogen ions into the P-type well 309 multiple times by ion implantation process to form a depth of 0.1-0.5 μm and a nitrogen ion doping concentration of 1 × 1018～1×1020cm-3Wherein the depth of the N + emitter 312 is 0.15 μm, and the doping concentration of nitrogen ions is 1 × 1019cm-3As shown in FIG. 3 l;
s313, etching the drift layer 3001 and the first oxide layer 307 by using a reactive ion etching process, and preparing a second trench 313, where the width of the second trench 313 is smaller than that of the first trench 306, so as to form a buried oxide layer 314, where the buried oxide layer 314 is located in the drift layer 3001, and on both sides of the second trench 313, as shown in fig. 3 m;
s314, forming a second oxide layer 315 in the second trench 313 by using a thermal oxidation process, and depositing a polysilicon 316 in the second trench 313 by using a CVD process, as shown in fig. 3 n;
s315, depositing photoresist on the surface of the whole device (namely the N + emitting region 312, the P contact region 311, the second oxidation layer 315 and the polysilicon 316), developing the photoresist above the N + emitting region 312 to form an emitter ohmic contact metal window, depositing Ni/Ti/Al alloy on the surface of the whole device, and annealing for 5 minutes in nitrogen atmosphere at 900 ℃ by utilizing an ultrasonic stripping process to form an emitter ohmic contact electrode 317; as shown in fig. 3 o.
S316, depositing photoresist on the whole device surface (the N + emitting region 312, the P contact region 311, the second oxidation layer 315 and the polysilicon 316), developing the photoresist above the P contact region 311 to form an emitter Schottky contact metal window, depositing metal Ni on the whole device surface, and forming an emitter Schottky contact electrode 318 by using an ultrasonic stripping process; further, the emitter ohmic contact electrode 317 and the emitter schottky contact electrode 318 may be in a short state; as shown in figure 3 p.
And S317, depositing a collector contact metal layer. A Ti/Al alloy is deposited as collector contact metal on the lower surface of collector layer 305 and annealed at 1050 c for 3 minutes in a nitrogen atmosphere to form collector 319 as shown in figure 3 q.
Example four
Referring to fig. 4, fig. 4 is a schematic diagram of a schottky contact injection enhancement SiC PNM-p-IGBT device according to an embodiment of the present invention.
The device structure includes: the semiconductor device comprises a collector layer 401, a buffer layer 402, a drift layer 403, an N-type base region 404, an N + doped region 405, an N contact region 406, a P + emitter region 407, a buried oxide layer 408, an emitter ohmic contact electrode 409, an emitter Schottky contact electrode 410 and a collector contact electrode 411, wherein the buried oxide layer 408 is positioned in the drift layer.
Preferably, the collector layer 401 is an N + collector layer, the buffer layer 402 is a P + buffer layer, and the drift layer 403 is a P-drift layer.
EXAMPLE five
Referring to fig. 5a to 5n, fig. 5a to 5n are schematic process diagrams of a schottky contact implantation enhancement mode SiC PNM-p-IGBT device according to an embodiment of the present invention. The method comprises the following steps:
s501, selecting an N + SiC substrate 501, and carrying out RCK standard cleaning on the N + SiC substrate 501, as shown in FIG. 5 a;
s502, extending the N + SiC substrate 501 by a hot wall LPCVD process to a thickness of 1-10 μm and a nitrogen ion doping concentration of 1 × 1016～1×1018cm-3The thickness of the buffer layer 502 can be selected to be 3 μm, and the doping concentration of nitrogen ions can be selected to be 1 × 1017cm-3As shown in fig. 5 b;
s503, extending the buffer layer 502 by a hot wall LPCVD process to a thickness of 100-200 μm with an aluminum ion doping concentration of 1 × 1014～1×1015cm-3Wherein the thick bottom of the first drift layer 503 can be 135 μm, and the doping concentration of aluminum ions can be 2 × 1014cm-3As shown in fig. 5 c;
s504, etching the first drift layer 503 by using a reactive ion etching process to form a first groove 504 with the depth of 1-10 μm, as shown in FIG. 5 d;
s505, depositing a first oxide layer 505 in the first trench 504 by using a thermal oxidation process, grinding off the oxide on the first drift layer, leaving only the oxide inside the first trench, and performing planarization on the surfaces of the first drift layer 503 and the first oxide layer 505, as shown in fig. 5 e;
s506, utilizing a hot wall LPCVD process to epitaxially form a layer with a thickness of 1-20 μm on the surfaces of the first drift layer 503 and the first oxide layer 505 and an aluminum ion doping concentration of 1 × 1014～1×1015cm-3Wherein the thickness of the second drift layer 506 can be further selected to be 5 μm, and the doping concentration of aluminum ions can be further selected to be 2 × 1014cm-3For convenience of illustration, the first drift layer 503 and the second drift layer 506 are collectively referred to as a drift layer 5001, as shown in fig. 5 f;
s507, epitaxially growing a depth on the drift layer 5001 by a hot-wall LPCVD process0.5 to 2 μm, and a nitrogen ion doping concentration of 1X 1017～1×1018cm-3Wherein the depth of the N-type well region 507 can be selected to be 1 μm or 1.5 μm, and the doping concentration of nitrogen ions can be selected to be 3 × 1017cm-3、8×1017cm-3As shown in fig. 5 g;
s508, selectively implanting nitrogen ions into the N-type well region 507 for multiple times by using an ion implantation process, wherein the thickness of the N-type well region is 0.1-0.5 μm, the doping concentration of the nitrogen ions is 1 × 10, and the doping concentration of the nitrogen ions is controlled19～1×1021cm-3The N + doped region 508 is formed to have a thickness of 0.01 to 0.1 μm and a nitrogen ion doping concentration of 5 × 1017～1×1018cm-3The N contact region 509, wherein the concentration of the N contact region is less than the N + doped region, and the surface concentration of the N contact region is the lowest, as shown in fig. 5 h;
s509, selectively implanting aluminum ions into the N-type well region 507 for multiple times by using an ion implantation process to form aluminum ions with a depth of 0.1-0.5 μm and an aluminum ion doping concentration of 1 × 1018～1×1020cm-3The depth of the P + emitter 510 can be selected to be 0.15 μm, and the doping concentration of aluminum ion can be selected to be 1 × 1019cm-3As shown in fig. 5 i;
s510, etching the drift layer 5001 and the first oxide layer 505 by using a reactive ion etching process, and preparing a second trench 511, wherein the width of the second trench 511 is smaller than that of the first trench 504, so as to form a buried oxide layer 512, wherein the buried oxide layer 512 is located in the drift layer 5001, and two sides of the second trench 511 are shown in fig. 5 j;
s511, forming a second oxide layer 513 in the second trench 511 by using a thermal oxidation process, and depositing a polysilicon 514 in the second trench 511 by using a CVD process, as shown in fig. 5 k;
s512, depositing Ti/Al alloy on the whole device surface (namely the surfaces of the N contact region 509, the P + emitting region 510, the second oxidation layer 513 and the polycrystalline silicon 514), preparing an emitter ohmic contact metal layer by utilizing an ultrasonic stripping process, and annealing for 3 minutes in a nitrogen atmosphere at 1050 ℃ to form an emitter ohmic contact electrode 515 as shown in FIG. 5 l;
s513, depositing a photoresist on the entire device surface (i.e., the surfaces of the N contact region 509, the P + emitter region 510, the second oxide layer 513 and the polysilicon layer 514), developing the photoresist on the N contact region 509 to form an emitter schottky contact metal window, depositing a metal Ni on the entire device surface, and forming an emitter schottky contact electrode 516 by using an ultrasonic lift-off process, further, the emitter ohmic contact electrode 515 and the emitter schottky contact electrode 516 may be in a short-circuit state, as shown in fig. 5 m;
and S514, depositing to form a collector contact metal layer. A Ti/Al alloy is deposited on the lower surface of the collector layer 501 as collector contact metal and annealed at 900 c for 5 minutes in a nitrogen atmosphere to form the collector 517 as shown in fig. 5 n.
In summary, the specific examples are applied to illustrate the preparation method of the novel schottky contact injection enhancement type SiCPNM-IGBT device according to the present invention, and the above description of the examples is only used to help understanding the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.
Claims (8)
1. A preparation method of a Schottky contact injection enhancement type SiC PNM-IGBT device is characterized by comprising the following steps:
continuously growing a transition layer, a first drift layer, a buffer layer and a collector layer on the surface of the SiC substrate by using a hot wall LPCVD (low pressure chemical vapor deposition) process;
etching the first drift layer by utilizing a reactive ion etching process to form a first groove, and growing a first oxide layer in the first groove by utilizing a thermal oxidation process;
growing a second drift layer on the surfaces of the first drift layer and the first oxide layer by utilizing a hot-wall LPCVD (low pressure chemical vapor deposition) process;
growing a P-type well region on the surface of the second drift layer by utilizing a hot wall LPCVD (low pressure chemical vapor deposition) process;
forming a P + doped region, a P contact region and an N + emitter region in the P-type well region by using an ion implantation process;
etching the second drift layer and the first oxide layer by utilizing a reactive ion etching process to form a second groove so as to prepare a buried oxide layer; wherein the width of the second trench is smaller than the width of the first trench;
growing a second oxide layer in the second trench by using a thermal oxidation process, and growing polycrystalline silicon on the second oxide layer by using a CVD (chemical vapor deposition) process;
depositing a metal layer to form emitter ohmic contact electrodes in the N + emitter regions respectively and form emitter Schottky contact electrodes in the P contact regions;
the deposited metal layer forms a collector contact electrode.
2. The method of claim 1, wherein growing a first oxide layer within the first trench using a thermal oxidation process comprises:
continuously growing the first oxide layer in the first trench until the depth of the first oxide layer is flush with the first drift layer;
removing the first oxide layer on the first drift layer;
and carrying out planarization treatment on the first oxide layer and the first drift layer.
3. The method of claim 1, wherein prior to growing a first oxide layer within the first trench using a thermal oxidation process, further comprising:
and removing the SiC substrate and the transition layer by utilizing a CMP process.
4. The method of claim 1, wherein growing a P-type well region on the second drift layer surface using a hot wall LPCVD process comprises:
growing the second drift layer to a depth of 0.5-2 μm and an aluminum ion doping concentration of 1 × 10 by hot wall LPCVD17～1×1018cm-3The P-type well region.
5. The method of claim 1, wherein forming a P + doped region, a P contact region, and an N + emitter region in the P-type well region using an ion implantation process comprises:
forming a depth of 0.1-0.5 μm and an aluminum ion doping concentration of 1 × 10 in the P-type well region by ion implantation19～1×1021cm-3The P + doped region of (a);
forming a depth of 0.01-0.1 μm and an aluminum ion doping concentration of 2 × 10 in the P-type well region by ion implantation17～1×1018cm-3The P contact region of (a);
forming a depth of 0.1-0.5 μm and a nitrogen ion doping concentration of 1 × 10 in the P-type well region by ion implantation18～1×1020cm-3The N + emitter region.
6. The method of claim 1, wherein forming an emitter ohmic contact electrode in the N + emitter region comprises:
depositing photoresist on the surface of the whole device, developing to form an emitter ohmic contact metal window, depositing Ni/Ti/Al alloy on the surface of the whole device, and forming an emitter ohmic contact metal layer by utilizing an ultrasonic stripping process;
and annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃ to form the emitter ohmic contact electrode.
7. The method of claim 1, wherein forming an emitter schottky contact electrode in the P-contact region comprises:
and depositing photoresist on the surface of the whole device, developing to form an emitter Schottky contact metal window, depositing metal Ni on the surface of the whole device, and forming the emitter Schottky contact electrode by utilizing an ultrasonic stripping process.
8. The method of claim 1, wherein depositing a metal layer to form a collector contact electrode comprises:
depositing Ti/Al alloy on the lower surface of the collector layer to form collector contact metal;
the collector contact electrode was formed by annealing in a nitrogen atmosphere at a temperature of 1050 c for 3 minutes.
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| CN106409898A (en) * | 2016-11-01 | 2017-02-15 | 株洲中车时代电气股份有限公司 | Trench gate IGBT (Insulated Gate Bipolar Transistor) with buried oxide layers and fabrication method thereof |
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