CN103928320A - Method for preparing bipolar transistor of silicon carbide insulated gate of groove gate - Google Patents
Method for preparing bipolar transistor of silicon carbide insulated gate of groove gate Download PDFInfo
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- CN103928320A CN103928320A CN201410162752.8A CN201410162752A CN103928320A CN 103928320 A CN103928320 A CN 103928320A CN 201410162752 A CN201410162752 A CN 201410162752A CN 103928320 A CN103928320 A CN 103928320A
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 27
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 87
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000002360 preparation method Methods 0.000 claims description 13
- 102000029749 Microtubule Human genes 0.000 claims description 12
- 108091022875 Microtubule Proteins 0.000 claims description 12
- 210000004688 microtubule Anatomy 0.000 claims description 12
- -1 nitrogen ion Chemical class 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 239000012159 carrier gas Substances 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000003139 buffering effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000004026 adhesive bonding Methods 0.000 description 11
- 238000001459 lithography Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a method for preparing a bipolar transistor of a silicon carbide insulated gate of a groove gate. The method mainly solves the problem that an existing bipolar transistor of a silicon carbide insulated gate is extremely high in preparing cost. The method comprises the steps that 1, a P-type carbide silicon substrate with good structural performance is selected, cutting and thinning are conducted on the back face of the substrate, and an oxide cutting face is polished; an N well region, an N+ body contact region and a P well region are sequentially formed on the front face of the substrate through ion implantation; 3, grooves are etched in the front face of the substrate, a groove gate oxide layer then grows, polycrystalline silicon deposition is conducted, and the grooves are filled with polycrystalline silicon; 4, ions on the back face of the substrate are implanted into a buffering layer and a collector region; 5, high-temperature annealing is conducted and implanted impurities are activated; 6, a device electrode is prepared. Compared with an existing method, a pressure-resistant layer with over-thick epitaxial is not needed, a large amount of production cost is reduced, the technical processes are simplified, and the method can be applied to the fields of inverters, switching mode power supplies and lighting circuits.
Description
Technical field
The invention belongs to microelectronics technology, relate to the preparation method of semiconductor device, particularly a kind of trench gate structure SiC IGBT that utilizes substrate to serve as Withstand voltage layer, can be widely used in the fields such as frequency converter, inverter, Switching Power Supply, lighting circuit and motor.
Technical background
Carborundum insulated gate bipolar transistor, SiC IGBT, is the novel high pressure-resistant device growing up based on carbofrax material.The solid-state main flow device of field of power electronics application is at present Si IGBT, and its shutoff voltage is 0.6～6.5kV.Through the development of 30 years, Si IGBT reached the limit of performance and device architecture, and along with new application developments such as electric automobile, photovoltaic and wind energy green energy resource, intelligent grids, required leap new in power electronic device performance.The breakthrough of the SiC semiconductor material with wide forbidden band of low micropipe defects density, makes power electronic device of new generation become possibility.The material structure of broad stopband causes the improvement of the performances such as the low electric leakage of semiconductor device, elevated operating temperature and anti-irradiation.Wide bandgap semiconductor SiC has than the critical breakdown electric field of the high order of magnitude of Si, means that the shutoff drift layer of SiC power electronic device can be thinner and have higher doping content, causes SiC to compare the conducting resistance with a low magnitude with Si equivalent device; Higher carrier saturation velocity causes higher operating frequency; Higher thermal conductivity will be improved heat dissipation, make device can be operated in higher power density.
The mid-90 in 20th century has proposed a kind of new ideas, and IGBT adopts U-shaped trench gate structure, and it has adopted from large-scale integrated technique and has used for reference the silicon dry etching technology of coming.In trench gate IGBT, grid voltage forms electron accumulation layer in drift region, has strengthened the electronic injection in PIN diode, has improved surperficial carrier concentration.And MOS structure " T " font conductive path in original IGBT shortens to two parallel vertical conduction paths, raceway groove, from laterally becoming longitudinally, causes cell density to reduce, thereby has increased the channel area in unit device area, and then reduced channel resistance; And groove grid have eliminated JFET effect, there will not be electric current " bottleneck " region.So IGBT compares with planar gate, trench gate IGBT can significantly reduce on-state voltage drop, thereby reaches more excellent trading off between on-state voltage drop and shutoff energy.In addition, with respect to PNP transistor current, the increase of PIN diode electric current proportion can effectively suppress latching effect, so trench gate IGBT has larger SOA safety operation area than planar gate IGBT.
The processing step of traditional trench gate SiC IGBT is as follows: grown buffer layer on substrate silicon face first; Then the thick extension Withstand voltage layer of 50～200 μ m of growing on resilient coating; Then on Withstand voltage layer, by Implantation, form well region, emitter region and heavy doping body contact zone; Then at substrate face etching groove, growth groove gate oxide, depositing polysilicon groove grid; The Metal Contact of last deposit, lithographic device.This method is deposited deficiency both ways: the one, and preparation cost is high.For example, SiC epitaxial device is expensive, and epitaxial process power consumption is large etc.; The 2nd, grow large compared with the technical difficulty of thick SiC epitaxial loayer, for example, for the epitaxial loayer of growth 100 μ m and above thickness, its technological requirement is high, only have in the world top silicon carbide device company as Cree etc. so just can accomplish, therefore, technical bottleneck problem has limited the universal and application of high-power SiC IGBT.
Summary of the invention
The object of the invention is to propose a kind of novel preparation method of trench gate carborundum insulated gate bipolar transistor, high to solve prior art preparation cost, and the problem that technology difficulty is large realizes the universal and application of high-power SiC IGBT.
Technical scheme of the present invention comprises the following steps:
(1) select the P type SiC substrate of zero microtubule, its cardinal plane dislocation is 10
4/ cm
-3, substrate concentration is 3 * 10
14～8 * 10
14cm
-3, the back side cutting along this P type SiC substrate, makes it be thinned to 100 μ m, then cut surface is carried out successively polishing, oxidation and removes oxide layer;
(2) in the P type SiC substrate face of described zero microtubule, with nitrogen ion, carry out N trap Implantation twice: implantation dosage is 1.5 * 10 for the first time
12cm
-2～7.5 * 10
12cm
-2, Implantation Energy is 300～700Kev; Implantation dosage 8 * 10 for the second time
11cm
-2～4 * 10
12cm
-2implantation Energy is 200～450Kev, forms N well region;
(3) in N well region upper left side and top-right region, with nitrogen ion, carry out heavy doping N
+implantation: implantation dosage is 9 * 10
13～7 * 10
14cm
-2, Implantation Energy is 150～300Kev, organizator contact zone;
(4) at N well region top zone line, with Al ion, carry out Implantation: implantation dosage is 3 * 10
14cm
-2～1 * 10
15cm
-2, Implantation Energy is 150～300Kev, forms P well region;
(5) SiO that deposit a layer thickness is 0.2um on the P type SiC substrate of whole zero microtubule
2, the zone line photoetching trench openings on P well region, and this window bottom SiC substrate is carried out to etching groove, until groove is positioned at N trap below, P well region is spaced as left and right two parts, these left and right two parts become emitter region;
(6) bottom of the above-mentioned groove etching and sidewall are oxidized, form trench gate oxide layer;
(7) in growing the groove that has trench gate oxide layer, adopt low pressure hot wall chemical vapor deposition method growing polycrystalline silicon, until polysilicon fills up groove;
(8) at the back side of the P type SiC substrate of described zero microtubule, with aluminium ion, carry out Implantation, implantation dosage is 4 * 10
12cm
-2～3 * 10
13cm
-2, Implantation Energy is 400～600Kev, forms P type resilient coating;
(9) at P type SiC substrate back, with nitrogen ion, carry out N
+implantation, implantation dosage is 4 * 10
13～2 * 10
14cm
-2, Implantation Energy is 200～350Kev, forms collector region;
(10) the P type SiC substrate of described zero microtubule is placed at 1700 ℃ and carries out high annealing 8～15 minutes, activate all implanted dopants;
(11) in the P type SiC substrate face of described zero microtubule, etch the side wall of polysilicon gate, then deposit titanium coating and nickel metal layer successively in this substrate face, go forward side by side row metal photoetching and etching, draw emitter and grid;
(12) at above-mentioned P type SiC substrate back deposition thickness, be 1 μ m nickel metal layer, draw collector electrode;
(13) by completing substrate after above-mentioned steps metal sintering 4～7 minutes at 900 ℃ of temperature, complete element manufacturing.
The present invention does not have the P of micro-tubular structure type SiC substrate to prepare trench gate IGBT device owing to selecting, and without carrying out extension, can directly pass through Implantation fabricate devices; Simultaneously owing to having saved epitaxy technique, and then reduce preparation difficulty, saved preparation cost and time, greatly must save natural resources and energy resources.
Accompanying drawing explanation
Fig. 1 is existing trench gate carborundum insulated gate bipolar transistor structure chart;
Fig. 2 is the flow chart that the present invention prepares Fig. 1 device;
Fig. 3 is the process schematic representation that the present invention prepares Fig. 1 device.
Embodiment
The present invention's equipment used mainly contains thermal oxidation furnace, ion implantor, magnetic control sputtering device, polysilicon deposition apparatus.
As shown in Figure 1, the trench gate carborundum insulated gate bipolar transistor that the present invention will be prepared, its structure comprises P type SiC substrate 1, N well region 2, N
+body contact zone 3, emitter region 4, trench gate oxide layer 5, polysilicon groove grid 6, resilient coating 7, collector region 8, SiO
2side wall 9, titanium coating 10, nickel metal layer 11.Wherein, P type SiC substrate 1 is lightly doped substrate, the top of P type SiC substrate 1 is N well region 2, the upper left corner of N well region 2 and Shi Ti contact zone, the upper right corner 3, the central region of N well region 2 is polysilicon groove grid 6, trench gate oxide layer 5 is wrapped in bottom and the sidewall of polysilicon groove grid 6, emitter region 4 is positioned at substrate top, is clipped in polysilicon groove grid 6 the right and lefts, collector region 8 is positioned at the below of substrate, and resilient coating 7 is positioned at the top of collector region 8, SiO
2side wall 9 is positioned at the left and right sides of polysilicon groove grid 6 the tops, and titanium coating 10 lays respectively at N
+the top of body contact zone 3, emitter region 4, polysilicon groove grid 6, nickel metal layer 11 lays respectively at the below of collector region 8 and the top of titanium coating 10.
The present invention prepares the method for described trench gate carborundum insulated gate bipolar transistor, provides following three kinds of embodiment:
Embodiment 1: in cardinal plane dislocation, be 10
4/ cm
-3, substrate concentration is 3 * 10
14cm
-3zero micro-tubular structure P type SiC substrate on, preparation trench gate carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the performing step of the present embodiment is as follows:
Step 1: substrate processing.
Selecting cardinal plane dislocation is 10
4/ cm
-3, substrate concentration is 3 * 10
14cm
-3zero micro-tubular structure P type SiC substrate, along the back side cutting of this P type SiC substrate 1, make it be thinned to 100 μ m; After cut surface polishing, at 950 ℃, wet-oxygen oxidation is 20 minutes, then removes oxide layer, recovers cut surface structure and evenness.
Step 2:N trap Implantation.
(2.1) adopting low pressure chemical vapor deposition mode is the SiO of 0.1 μ m in the P type SiC substrate face deposit a layer thickness after above-mentioned processing
2, then deposition thickness be the Al of 1 μ m as the barrier layer of nitrogen Implantation, gluing makes N trap injection region window by lithography;
(2.2) N trap injection region window is carried out to Implantation twice: at 650 ℃, first adopt the Implantation Energy, 1.5 * 10 of 300Kev
12cm
-2implantation dosage carry out nitrogen Implantation one time, then adopt the Implantation Energy, 8 * 10 of 200Kev
11cm
-2implantation dosage carry out secondary nitrogen Implantation, form N well region 2, as a in Fig. 3.
Step 3: body contact zone Implantation.
Complete the P type SiC substrate face gluing of above-mentioned technique, making the upper left corner and the upper right corner window of N well region 2 by lithography, to these two windows, using nitrogen ion to carry out heavy doping N one time
+implantation, implantation dosage is 9 * 10
13cm
-2, Implantation Energy is 150Kev, organizator contact zone 3, as b in Fig. 3.
Step 4:P well region Implantation.
(4.1) at the P of occlusion body contact zone type SiC substrate face gluing, make the zone line window of N well region 2 by lithography, on this window, with aluminium ion, carry out P one time
+implantation, implantation dosage 3 * 10
14cm
-2, Implantation Energy is 150Kev, forms P well region, as c in Fig. 3;
(4.2) remove Al and the SiO of the deposit of P type SiC substrate face
2.
Step 5: etching groove.
(5.1) on the whole front of the P type SiC substrate through multistep Implantation, adopting low pressure chemical vapor phase method deposit a layer thickness is the SiO of 0.2 μ m
2layer;
(5.2) at above-mentioned SiO
2magnetron sputtering one deck on layer
ti film as ICP etch mask, then gluing, make trench openings by lithography, carry out ICP etching until N well region below forms the groove through P well region, as d in Fig. 3; Finally remove photoresist, remove etch mask and clean, the process conditions of ICP etching are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
(5.3) through the etching groove of P well region, P well region is divided into left and right two parts, with these left and right two parts as emitter region 4.
Step 6: the growth of trench gate oxide layer.
At 1200 ℃, to completing the P type SiC substrate face of etching groove, carry out dry-oxygen oxidation 2 hours, at channel bottom and sidewall, form the trench gate oxide layer 5 that thickness is 40nm; Then at the N of 1050 ℃
2under atmosphere, anneal, reduce SiO
2the roughness of film surface, as e in Fig. 3.
Step 7: groove polysilicon deposit.
The front that has the P type SiC substrate of trench gate oxide layer 5 in growth, adopts low pressure hot wall chemical vapor deposition method growing polycrystalline silicon, makes it fill up groove, as f in Fig. 3; Then gluing photoetching, etch polysilicon layer, forms polysilicon groove grid; Finally remove photoresist, clean, wherein, the process conditions of growing polycrystalline silicon are: ambient temperature is 650 ℃,
Deposit pressure is 80Pa, and reacting gas is silane and hydrogen phosphide, and carrier gas is helium.
Step 8: resilient coating Implantation.
P is carried out at the back side at P type SiC substrate
+implantation, implantation dosage is 4 * 10
12cm
-2, Implantation Energy is 400Kev, forms resilient coating 7, as g in Fig. 3.
Step 9: collector area Implantation.
At the P type SiC substrate back that contains resilient coating, with nitrogen ion, carry out N
+implantation, implantation dosage is 4 * 10
13cm
-2, Implantation Energy is 200Kev, forms collector area 8, as g in Fig. 3.
Step 10: above-mentioned prepared P type SiC substrate is placed in to the ar gas environment of 1700 ℃, carries out high annealing, the time is 15 minutes, activates implanted dopant.
Step 11: prepare emitter and grid in substrate face.
(11.1), in the front gluing photoetching of above-mentioned P type SiC substrate, etch the SiO of groove grid
2side wall 9, as h in Fig. 3;
(11.2) adopt the P type SiC substrate face of magnetron sputtering method after etching side wall 9 deposit titanium coating and nickel metal layer 11 successively, wherein, titanium coating thickness is 50nm, and nickel metal layer thickness is 150nm; Then gluing, development on metal level, carries out corrosion of metals and forms emitter and grid, then removes photoresist, cleans, as i in Fig. 3.
Step 12: prepare collector electrode at substrate back.
Completing P type SiC substrate back deposition thickness prepared by grid and emitter, be 1 μ m nickel metal layer, draw collector electrode, as i in Fig. 3;
Step 13: by completing substrate after above-mentioned steps metal sintering 4 minutes at 900 ℃ of temperature, complete element manufacturing.
Embodiment 2: in cardinal plane dislocation, be 10
4/ cm
-3, substrate concentration is 6 * 10
14cm
-3without on micro-tubular structure P type SiC substrate, preparation trench gate type carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the performing step of the present embodiment is as follows:
Steps A: substrate processing.
This step is identical with the step 1 of embodiment 1.
Step B:N trap Implantation.
(b1) this step is identical with the step (2.1) of embodiment 1;
(b2) N trap injection region window is carried out to Implantation twice: at 650 ℃, first adopt the Implantation Energy, 4.5 * 10 of 500Kev
12cm
-2implantation dosage carry out nitrogen Implantation one time, then adopt the Implantation Energy, 1 * 10 of 350Kev
12cm
-2implantation dosage carry out secondary nitrogen Implantation, form N well region 2, as a in Fig. 3.
Step C: completing the P type SiC substrate face gluing of above-mentioned technique, make N well region 2 upper left corners and upper right corner window by lithography, use nitrogen ion to carry out heavy doping N one time to these two windows
+implantation, implantation dosage is 3 * 10
14cm
-2, Implantation Energy is 250Kev, organizator contact zone 3, as b in Fig. 3.
Step D: at the P of occlusion body contact zone type SiC substrate face gluing, make the window of N well region 2 zone lines by lithography, carry out P one time with aluminium ion on this window
+implantation, implantation dosage 6 * 10
14cm
-2, Implantation Energy is 220Kev, forms P well region, as c in Fig. 3; Then remove Al and SiO except the deposit of P type SiC substrate face
2barrier layer.
Step e: etching groove.
This step is identical with the step 5 of embodiment 1.
Step F: at 1200 ℃, carry out dry-oxygen oxidation 3 hours to completing the P type SiC substrate face of etching groove, form at channel bottom and sidewall the trench gate oxide layer 5 that thickness is 60nm; Then at the N of 1050 ℃
2under atmosphere, anneal, reduce SiO
2the roughness of film surface, as e in Fig. 3.
Step G: groove polysilicon deposit.
This step is identical with the step 7 of embodiment 1.
Step H: P is carried out at the back side at P type SiC substrate
+implantation, implantation dosage is 8 * 10
12cm
-2, Implantation Energy is 500Kev, forms resilient coating 7, as g in Fig. 3.
Step I: carry out N with nitrogen at the P type SiC substrate back that contains resilient coating
+implantation, implantation dosage is 8 * 10
13cm
-2, Implantation Energy is 250Kev, forms collector area 8, as g in Fig. 3.
Step J: above-mentioned prepared P type SiC substrate is placed in to the ar gas environment of 1700 ℃, carries out high annealing, the time is 10 minutes, activates implanted dopant.
Step K: prepare emitter and grid in substrate face.
This step is identical with the step 11 of embodiment 1.
Step L: prepare collector electrode at substrate back.
This step is identical with the step 12 of embodiment 1.
Step M: by completing substrate after above-mentioned steps metal sintering 11 minutes at 900 ℃ of temperature, complete element manufacturing.
Embodiment 3: in cardinal plane dislocation, be 10
4/ cm
-3, substrate concentration is 8 * 10
14cm
-3without on micro-tubular structure P type SiC substrate, preparation trench gate carborundum insulated gate bipolar transistor.
With reference to Fig. 2 and Fig. 3, the performing step of the present embodiment is as follows:
The first step: substrate processing.
This step is identical with the step 1 of embodiment 1.
Second step: adopt low pressure chemical vapor deposition mode the P type SiC substrate face deposit a layer thickness through above-mentioned processing be the Al of 1.2 μ m as the barrier layer of nitrogen Implantation, gluing makes N trap injection region window by lithography; At 650 ℃, N well region window is carried out to Implantation twice, first use the Implantation Energy, 7.5 * 10 of 700Kev
12cm
-2implantation dosage carry out nitrogen Implantation one time, then use the Implantation Energy, 4 * 10 of 450Kev
12cm
-2implantation dosage carry out secondary nitrogen Implantation, form N well region 2, as a in Fig. 3.
The 3rd step: complete the P type SiC substrate face gluing of above-mentioned technique, making the upper left corner and the upper right corner window of N well region 2 by lithography, using nitrogen ion to carry out heavy doping N one time to these two windows
+implantation, implantation dosage is 7 * 10
14cm
-2, Implantation Energy is 300Kev, organizator contact zone 3, as b in Fig. 3.
The 4th step: at the P of occlusion body contact zone type SiC substrate face gluing, make the zone line window of N well region 2 by lithography, carrying out energy with aluminium ion on this window is 300Kev, dosage 1 * 10
15cm
-2a P
+implantation, forms P well region 4; Then remove the Al barrier layer of P type SiC substrate face deposit, as c in Fig. 3.
The 5th step: etching groove.
This step is identical with the step 5 of embodiment 1.
The 6th step: at 1200 ℃, carry out dry-oxygen oxidation 4 hours to completing the P type SiC substrate face of etching groove, form at channel bottom and sidewall the trench gate oxide layer 5 that thickness is 75nm; Then at the N of 1050 ℃
2under atmosphere, anneal, reduce SiO
2the roughness of film surface, as e in Fig. 3.
The 7th step: groove polysilicon deposit.
This step is identical with the step 7 of embodiment 1.
The 8th step: carrying out dosage at the back side of P type SiC substrate with aluminium ion is 3 * 10
13cm
-2, the energy P that is 600Kev
+implantation, forms resilient coating 7, as g in Fig. 3.
The 9th step: carrying out dosage at the P type SiC substrate back that contains resilient coating with nitrogen ion is 2 * 10
14cm
-2, the energy N that is 350Kev
+implantation, forms collector area 8, as g in Fig. 3.
The tenth step: the P type SiC substrate after above-mentioned steps is placed in to the ar gas environment of 1700 ℃, carries out high annealing, the time is 8 minutes, activates implanted dopant.
The 11 step: prepare emitter and grid in substrate face.
This step is identical with the step 11 of embodiment 1.
The 12 step: prepare collector electrode at substrate back.
This step is identical with the step 12 of embodiment 1.
The 13 step: by completing substrate after above-mentioned steps metal sintering 7 minutes at 900 ℃ of temperature, complete element manufacturing.
Claims (4)
1. a preparation method for trench gate carborundum insulated gate bipolar transistor, comprises the following steps:
(1) select the P type SiC substrate of zero microtubule, its cardinal plane dislocation is 10
4/ cm
-3, substrate concentration is 3 * 10
14～8 * 10
14cm
-3, the back side cutting along this P type SiC substrate, makes it be thinned to 100 μ m, then cut surface is carried out successively polishing, oxidation and removes oxide layer;
(2) in the P type SiC substrate face of described zero microtubule, with nitrogen ion, carry out N trap Implantation twice: implantation dosage is 1.5 * 10 for the first time
12cm
-2～7.5 * 10
12cm
-2, Implantation Energy is 300～700Kev; Implantation dosage 8 * 10 for the second time
11cm
-2～4 * 10
12cm
-2implantation Energy is 200～450Kev, forms N well region;
(3) in N well region upper left side and top-right region, with nitrogen ion, carry out heavy doping N
+implantation: implantation dosage is 9 * 10
13～7 * 10
14cm
-2, Implantation Energy is 150～300Kev, organizator contact zone;
(4) at N well region top zone line, with Al ion, carry out Implantation: implantation dosage is 3 * 10
14cm
-2～1 * 10
15cm
-2, Implantation Energy is 150～300Kev, forms P well region;
(5) SiO that deposit a layer thickness is 0.2um on the P type SiC substrate of whole zero microtubule
2, the zone line photoetching trench openings on P well region, and this window bottom SiC substrate is carried out to etching groove, until groove is positioned at N trap below, P well region is spaced as left and right two parts, these left and right two parts become emitter region;
(6) bottom of the above-mentioned groove etching and sidewall are oxidized, form trench gate oxide layer;
(7) in growing the groove that has trench gate oxide layer, adopt low pressure hot wall chemical vapor deposition method growing polycrystalline silicon, until polysilicon fills up groove;
(8) at the back side of the P type SiC substrate of described zero microtubule, with aluminium ion, carry out Implantation, implantation dosage is 4 * 10
12cm
-2～3 * 10
13cm
-2, Implantation Energy is 400～600Kev, forms P type resilient coating;
(9) at the P type SiC substrate back that contains P type resilient coating, with nitrogen ion, carry out N
+implantation, implantation dosage is 4 * 10
13～2 * 10
14cm
-2, Implantation Energy is 200～350Kev, forms collector region;
(10) the P type SiC substrate of described zero microtubule is placed at 1700 ℃ and carries out high annealing 8～15 minutes, activate all implanted dopants;
(11) in the P type SiC substrate face of described zero microtubule, etch the side wall of polysilicon gate, then deposit titanium coating and nickel metal layer successively in this substrate face, go forward side by side row metal photoetching and etching, draw emitter and grid;
(12) at above-mentioned P type SiC substrate back deposition thickness, be 1 μ m nickel metal layer, draw collector electrode;
(13) by completing substrate after above-mentioned steps metal sintering 4～7 minutes at 900 ℃ of temperature, complete element manufacturing.
2. the preparation method of trench gate carborundum insulated gate bipolar transistor according to claim 1, is characterized in that etching groove in described step (5), and its process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2flow is respectively 48sccm and 12sccm.
3. the preparation method of trench gate carborundum insulated gate bipolar transistor according to claim 1, is characterized in that trench gate oxide layer growth in described step (6), and its process conditions are: temperature is 1200 ℃, and the time is 2～4 hours.
4. the preparation method of trench gate carborundum insulated gate bipolar transistor according to claim 1, it is characterized in that employing low pressure hot wall chemical vapor deposition method growing polycrystalline silicon in described step (7), its process conditions are: deposition temperature is 650 ℃, deposit pressure is 80Pa, reacting gas is silane and hydrogen phosphide, and carrier gas is helium.
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| CN109244129A (en) * | 2018-11-09 | 2019-01-18 | 上海擎茂微电子科技有限公司 | A kind of trench-type insulated gate bipolar transistor device and preparation method |
| CN111490098A (en) * | 2020-04-17 | 2020-08-04 | 重庆伟特森电子科技有限公司 | Groove type SiC IGBT structure and preparation method thereof |
| CN113189637A (en) * | 2021-06-07 | 2021-07-30 | 杭州电子科技大学 | Silicon carbide neutron detector based on double-sided T-shaped grooves |
| CN113270492A (en) * | 2021-05-13 | 2021-08-17 | 重庆邮电大学 | Trench type GaN insulated gate bipolar transistor |
| CN113838756A (en) * | 2021-09-24 | 2021-12-24 | 南瑞联研半导体有限责任公司 | Device manufacturing method for improving micro-deformation of Trench-IGBT wafer |
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| CN113838756A (en) * | 2021-09-24 | 2021-12-24 | 南瑞联研半导体有限责任公司 | Device manufacturing method for improving micro-deformation of Trench-IGBT wafer |
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| WO2023155584A1 (en) * | 2022-02-21 | 2023-08-24 | 珠海零边界集成电路有限公司 | Insulated gate bipolar transistor, manufacturing method, electronic device, and storage medium |
| CN114975602A (en) * | 2022-07-29 | 2022-08-30 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
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