CN109244129A - A kind of trench-type insulated gate bipolar transistor device and preparation method - Google Patents
A kind of trench-type insulated gate bipolar transistor device and preparation method Download PDFInfo
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- CN109244129A CN109244129A CN201811333504.XA CN201811333504A CN109244129A CN 109244129 A CN109244129 A CN 109244129A CN 201811333504 A CN201811333504 A CN 201811333504A CN 109244129 A CN109244129 A CN 109244129A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 77
- 229920005591 polysilicon Polymers 0.000 claims abstract description 73
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000000227 grinding Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 6
- 230000000903 blocking effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 238000004544 sputter deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000003701 mechanical milling Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
This application discloses a kind of trench-type insulated gate bipolar transistor device and preparation method, including N-type base area, p-type base areas, polysilicon gate, N+ emitter, the contact zone P+, N-type field terminator and p-type collector, polysilicon gate protrude N+ emitter or the contact zone P+ surface 1-2um.Preparation method forms p-type base area in N-type base region surface；N+ emitter is formed in p-type base region surface；Silica is generated as barrier layer and digging groove forms polysilicon gate；Chemical mechanical grinding removes the polysilicon of silica surface, and grinding stops on silicon dioxide blocking layer, retains the polysilicon inside groove, so that polysilicon be made to protrude silicon face；The contact zone P+ is formed in N+ emitter；N-type field terminator is formed at the N-type base area back side；P-type collector is formed at the N-type field terminator back side.The application can reduce the vertical overlapping area of N+ emitter and polysilicon gate interpolar, reduce gate-source capacitance, it is ensured that conducting voltage consistency reduces switching delay time.
Description
Technical field
The application belongs to semiconductor power power electronic devices technical field, and in particular to a kind of groove-shaped insulated gate bipolar
Transistor npn npn device and preparation method.
Background technique
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT) is
It is a kind of to reach spirit what Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and bipolar junction transistor (BJT) combined
The semiconductor power device for structure of pausing, with voltage control, input impedance is big, driving power is small, conducting resistance is small, switching loss
The characteristics such as low and working frequency is high, are more satisfactory semiconductor power switch devices, switching frequency is in 10K-100K hertz
Between, there are wide development and application prospect.
Higher and higher now with the requirement of IGBT current density, the requirement to trench process is also higher and higher.Volume production at present
The trench gate of IGBT is all the growing polycrystalline silicon after etching groove completion, then carries out etching polysilicon.In etching polysilicon work
In order to ensure the polysilicon in surface of silicon is etched completely in skill, polysilicon over etching has usually all been carried out.Do so meeting
So that sunk shape is presented in polysilicon upper surface, cause between N+ emitter and trench gate that vertical overlapping area is less than normal, makes
It obtains conducting resistance to increase, to increase IGBT on-state loss.Prior art in order to solve this problem, is usually taken and increases N+ hair
Emitter injection energy, it is longer to push away the trap time, form deeper N+ emitter junction depth, ensures N+ emitter and polysilicon gate with this
It is extremely vertical overlapping, to form effective conducting channel.But it does so and often will increase grid source contact area, so that gate-source capacitance
It is excessive, increase the switching loss of IGBT.It is too short to also result in effective conducting channel length, channel resistance increases, break-over of device pressure
It drops excessively high.
Apply for content
The shortcomings that for the above-mentioned prior art or deficiency, the application technical problems to be solved are to provide a kind of groove-shaped exhausted
Edge grid bipolar transistor device structure and preparation method, by forming polycrystalline using chemical mechanical milling tech in the top of the groove
Silicon gate protrudes the grid structure of silicon face, so that polysilicon gate and N+ emitter are seamlessly connected in groove, reduces emitter
Overlapping area between polysilicon gate, reduces gate-source capacitance, reduces switching delay time, reduces the switch of device
Dynamic loss improves switching characteristic.The consistency for also ensuring IGBT conducting voltage simultaneously reduces the on-state damage of IGBT
Consumption.
A kind of trench-type insulated gate bipolar transistor device, comprising: N-type base area；P-type base area is formed in the N-type
Base region surface；Polysilicon gate is groove structure, through in the p-type base area and N-type base area, and protrudes from the p-type
The surface of base area；N+ emitter is formed in the p-type base region surface, and is connected with the two sides of the polysilicon gate；P+
Contact zone is formed in the p-type base region surface, and overlapping with the N+ emitter；N-type field terminator is formed in the N-type base
The area back side and p-type collector, with N-type field terminator rear-face contact；Wherein, the polysilicon gate protrudes the N+
Emitter or the contact zone P+ surface 1-2um.
The trench depth of the polysilicon gate is 3-6um, cross-sectional width 0.5-2um, and the groove is interior to be filled with N
The polysilicon of type high-dopant concentration.
The bottom surface and side of the polysilicon gate are additionally provided with gate oxide, the gate oxide with a thickness of
The polysilicon gate in the trench, is equipped with insulation between the polysilicon gate and the N+ emitter metal
Dielectric layer.
Collector electrode metal layer is additionally provided at the back side of the p-type collector.
The contact zone P+ and the overlapping setting of the N+ emitter.
The preparation method of trench-type insulated gate bipolar transistor device includes the following steps: to pass through in N-type base region surface
Ion implanting forms p-type base area with trap technique is pushed away；N+ emitter is formed by ion implanting in p-type base region surface；In above-mentioned knot
Structure surface grows silica as barrier layer, to deep-cut groove；The highly doped polysilicon of N-type is filled inside groove to be formed
Polysilicon gate；Chemical mechanical grinding is carried out, the polysilicon of silica surface is removed, chemical mechanical grinding stops at dioxy
SiClx barrier layer surface retains the polysilicon inside groove, and polysilicon is made to protrude N-type base region surface；Lead among N+ emitter
It crosses ion implanting and pushes away trap technique and form the contact zone P+, wherein the polysilicon gate protrudes the N+ emitter or the P+
Contact zone surface 1-2um；By ion implanting and trap technique formation N-type field terminator is pushed away at the N-type base area back side；In N-type base area
The back side forms p-type collector by ion implanting and activation technology.
It is grown in N-type base region surfaceSilica is then injected into energy and exists as ion implanting barrier layer
50-100kev, dosage are in 1E13-8E13cm-2Between boron ion, push away trap by high temperature, temperature is between 1000-1150 DEG C,
Time is 50-200min, forms p-type base area；The doping concentration of the N-type base area is 1E13-2E14cm-3；The p-type base area
Peak concentration is 1E17-8E17cm-3, junction depth is in 3um or more.
It is greater than 1E15cm in 50kev or more, dosage in the p-type base region surface Implantation Energy-2Arsenic ion, formed N+ hair
Emitter-base bandgap grading；The peak concentration of the N+ emitter is 1E19-4E20cm-3, junction depth 0.2-1um.
Boron ion is injected between the N+ emitter, forms the contact zone P+；The peak concentration of the contact zone P+ is
1E19-5E20cm-3, junction depth 0.2-1um.
The peak concentration of the p-type collector is 1E19-5E19cm-3, junction depth 0.2-1um；N-type field terminator
Peak concentration is 5E15-5E16cm-3, junction depth 1-2um.
Generate one layerBarrier layer of the silica as etching groove, carry out photoetching over the barrier layer
Then technique uses silica as barrier layer and carries out etching groove, to form multiple deep trench areas.
On the polysilicon gate, one layer of sacrificial oxide layer is grown by high temperature furnace pipe, and utilize wet etching sacrifice
Oxide layer, to ensure the smooth of channel bottom and side wall；High temperature furnace pipe grows trenched side-wall gate oxide；Then it carries out again
High temperature furnace pipe growing polycrystalline silicon, polysilicon with a thickness of 1-1.5um；Then chemical mechanical grinding is carried out, by silica surface
Polysilicon removal, be parked on silicon dioxide blocking layer, only retain groove inside polysilicon.
It is grown using silica film-forming process on the surface of the polysilicon gate and the N+ emitterSilicon dioxide insulator dielectric layer；Then photoresist coating, exposure contact domain, with mask are carried out
It performs etching；After the insulating film etching, photoresist, further progress silicon etching are removed, etching depth exists
Between.
Emitter metal is formed by physical sputtering metal above the contact zone P+.
Collector electrode metal layer is formed by physical sputtering at the p-type collector back side.
In order to solve the above technical problems, the application has following constitute:
The application forms the grid structure of polysilicon gate protrusion silicon face in the top of the groove using chemical mechanical milling tech,
Evade polysilicon gate in traditional handicraft completely and returns quarter uncontrollable risk；Using self-registered technology, polysilicon gate can be made
Pole and N+ emitter seamless interlinkage reduce this two layers of photoetching process in process and cover inclined risk；Simultaneously because the device can
To reduce the Implantation Energy of N+ emitter, to reduce the vertical overlapping area between N+ emitter and polysilicon gate, reduce
Gate-source capacitance, effectively improves the switching characteristic of IGBT and the stability of threshold voltage.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, the application's is other
Feature, objects and advantages will become more apparent upon:
Fig. 1: the sectional view of trench-type insulated gate bipolar transistor device in the application；
Fig. 2: partial structural diagram as shown in Figure 1.
Specific embodiment
It is described further below with reference to technical effect of the attached drawing to the design of the application, specific structure and generation, with
It is fully understood from the purpose, feature and effect of the application.
As depicted in figs. 1 and 2, the present embodiment trench-type insulated gate bipolar transistor device, comprising: N-type base area 240, P
Type base area 252, polysilicon gate 292, gate oxide 290, N+ emitter 280, insulating medium layer 270, the contact zone P+ 260, N-type
Field terminator 230, p-type collector 220 and collector electrode metal layer 210, wherein the p-type base area 252 is formed in the N-type
240 surface of base area；The polysilicon gate 292 is groove structure, through in the p-type base area 252 and N-type base area 240,
And protrude from the surface of the p-type base area 252；The N+ emitter 280 is formed in 252 surface of p-type base area, and with it is described
The two sides of polysilicon gate 292 are connected；The contact zone P+ 260 is formed in 252 surface of p-type base area, and with the N
+ emitter 280 is overlapping；N-type field terminator 230 is formed in 240 back side of N-type base area, the p-type collector with it is described
230 rear-face contact of N-type field terminator；Wherein, the polysilicon gate 292 protrudes the N+ emitter 280 or P+ contact
260 surface 1-2um of area.
Wherein, the trench depth of the polysilicon gate 292 is 3-6um, cross-sectional width 0.5-2um, the groove
The interior polysilicon filled with N-type high-dopant concentration.
The bottom surface and side of the polysilicon gate 292 are additionally provided with gate oxide 290, the thickness of the gate oxide 290
For
The polysilicon gate 292 is below emitter metal, in the polysilicon gate 292 and the emitter metal
Between be equipped with insulating medium layer 270, the insulating medium layer 270 is made of silica.
It is additionally provided with collector electrode metal layer 210 at the back side of the p-type collector 220, is realized and is carried on the back by physical sputtering technology
Face metallization.
The doping concentration of the N-type base area 240 is 1E13-2E14cm-3, it is ensured that IGBT device withstanding voltage.
252 junction depth of p-type base area is in 3um or more, peak concentration 1E17-8E17cm-3, concentration setting is in conjunction with polycrystalline
The thickness of 292 side wall gate oxide 290 of silicon gate, it is ensured that IGBT threshold voltage has enough safe clearances in 5V or more.
The peak concentration of the N+ emitter 280 is 1E19-4E20cm-3, junction depth 0.2-1um.Further, due to N+
Emitter and the contact zone P+ are overlapping, it is ensured that contact resistance is small.N+ emitter is connected to conducting channel, guarantees electronic current access.
The peak concentration of the contact zone P+ 260 is in 1E19-5E20cm-3, junction depth 0.2-1um.The contact zone P+ 260
Setting is overlapped with the N+ emitter 280, to ensure that contact resistance is sufficiently small.
The peak concentration of the p-type collector is 1E19-5E19cm-3, junction depth 0.2-1um reaches control hole emission
The effect of efficiency.
The peak concentration of N-type field terminator 230 is 5E15-5E16cm-3, junction depth 1-2um can reach improvement
IGBT compromise characteristic, the effect of current tail time when reducing IGBT shutdown.
The preparation method of the groove-shaped insulated gate bipolar transistor device of the present embodiment, comprising the following steps:
Step 1 by ion implanting and pushes away trap technique formation p-type base area 252 on 240 surface of N-type base area, specifically,
The growth of 240 silicon face of N-type base areaSilica is then injected into energy in 50- as ion implanting barrier layer
100kev, dosage are in 1E13-8E13cm-2Between boron ion, push away trap by high temperature, temperature is the time between 1000-1150 DEG C
For 50-200min, p-type base area 252 is formed.Wherein, the doping concentration of the N-type base area 240 is 1E13-2E14cm-3, it is ensured that
IGBT device withstanding voltage.The junction depth of the p-type base area 252 is in 3um or more, peak concentration 1E17-8E17cm-3, the concentration
Thickness in conjunction with 292 side wall gate oxide 290 of polysilicon gate is set, it is ensured that IGBT threshold voltage has enough in 5V or more
Safe clearance.
Step 2 forms N+ emitter 280 by ion implanting on the p-type base area 252 and specifically passes through injection
Energy is greater than 1E15cm in 50kev or more, dosage-2Arsenic ion, formed N+ emitter 280.Wherein, the N+ emitter 280
Peak concentration be 1E19-4E20cm-3, junction depth 0.5-1um.Further, it is set since N+ emitter and the contact zone P+ overlap
It sets, it is ensured that contact resistance is small.N+ emitter is connected to conducting channel, guarantees electronic current access.
Step 3, then above structure surface grows one layerSilica, as etching groove
Barrier layer carries out groove figure exposure, development in the barrier layer coated thereon photoresist, and carries out silica with glue
Etching, then removes photoresist.Silicon trench etching is carried out using the silica as barrier layer, that is, deep-cuts multiple grooves,
In, the trench depth of the polysilicon gate 292 is 3-6um, cross-sectional width 0.5-2um.
Further, one layer of sacrificial oxide layer is grown by high temperature furnace pipe, wet etching is recycled to fall sacrificial oxide layer, with
Ensure the smooth of channel bottom and side wall；High temperature furnace pipe grows trenched side-wall gate oxide 290, wherein the gate oxide
290 with a thickness ofAforesaid operations step is in order to reduce defect and impurity, so that it is preferable to grow compactness
Gate oxide 290；Then carry out high temperature furnace pipe growing polycrystalline silicon again, polysilicon with a thickness of 1-1.5um；Carry out chemical machinery
Grinding removes the polysilicon of silica surface, and grinding stops at silicon dioxide blocking layer surface, only retains inside groove
Polysilicon.
It is grown using silica film-forming process on the surface of the polysilicon gate 292 and the N+ emitter 280Silicon dioxide insulator dielectric layer 270；Then photoresist coating, exposure contact domain, with mask are carried out
Version performs etching removal photoresist to silicon dioxide insulator dielectric layer 270.
Step 4 forms the contact zone P+ 260 with trap technique is pushed away by ion implanting between N+ emitter 280, specifically,
Boron ion is injected between the N+ emitter 280, forms the contact zone P+ 260.Wherein, the peak value of the contact zone P+ 260 is dense
Degree is 1E19-5E20cm-3, junction depth 0.2-1um.The contact zone P+ 260 and the overlapping setting of the N+ emitter 280, with true
It is sufficiently small to protect contact resistance.
Further, emitter metal is formed by physical sputtering method above the contact zone P+ 260, specifically,
Metal sputtering is carried out, the photoetching of metal domain, exposure are then carried out, developing process uses wet process or dry etching with photoresist
Metal forms metal interconnection, and metal thickness is in 1-5um.
Step 5 by ion implanting and pushes away trap technique formation N-type field terminator 230 at 240 back side of N-type base area；The N
The peak concentration of type field terminator 230 is 5E15-5E16cm-3, junction depth 1-2um, can reach improves IGBT compromise characteristic, subtracts
The effect of current tail time when few IGBT shutdown.
Step 6 forms p-type collector, the P by ion implanting and activation technology at 230 back side of N-type field terminator
The peak concentration of type collector is 1E19-5E19cm-3, junction depth 0.2-1um, have the function that control hole emission efficiency.
Further, collector electrode metal layer 210 is formed by physical sputtering at the p-type collector back side, passes through physical sputtering
To make back metal.
The application forms the grid structure of polysilicon gate protrusion silicon face in the top of the groove using chemical mechanical milling tech,
Evade polysilicon in traditional handicraft completely and returns quarter uncontrollable risk.Using self-registered technology, polysilicon gate and N can be made
+ emitter seamless interlinkage reduces this two layers of photoetching process in process and covers inclined risk；Simultaneously because the device can be reduced
The Implantation Energy of N+ emitter reduces grid source to reduce the vertical overlapping area between N+ emitter and polysilicon gate
Capacitor effectively improves the switching characteristic of IGBT and the stability of threshold voltage.
Above embodiments are only to illustrate the technical solution of the application and non-limiting, referring to preferred embodiment to the application into
Detailed description is gone.Those skilled in the art should understand that the technical solution of the application can be modified or be waited
With replacement, without departing from the spirit and scope of technical scheme, should all cover within the scope of claims hereof.
Claims (10)
1. a kind of trench-type insulated gate bipolar transistor device characterized by comprising
N-type base area,
P-type base area is formed in the N-type base region surface；
Polysilicon gate is groove structure, through in the p-type base area and N-type base area, and protrudes from the p-type base area
Surface setting；
N+ emitter is formed in the p-type base region surface, and the two sides face contact with the polysilicon gate；
The contact zone P+ is formed in the p-type base region surface, and overlaps setting with the N+ emitter,
N-type field terminator is formed at the N-type base area back side,
And p-type collector, it is arranged with N-type field terminator rear-face contact；
Wherein, the polysilicon gate protrudes the N+ emitter or the contact zone P+ surface 1-2um setting.
2. device according to claim 1 or 2, which is characterized in that the bottom surface and side of the polysilicon gate are additionally provided with
Gate oxide, the gate oxide with a thickness of
3. device according to claim 1 or 2, which is characterized in that the contact zone P+ and the N+ emitter are overlapped and set
It sets.
4. the preparation method of device as described in any one of claims 1 to 3, which comprises the following steps:
By ion implanting and trap technique formation p-type base area is pushed away in N-type base region surface；
N+ emitter is formed by ion implanting in p-type base region surface；
On above structure surface, growth silica is as barrier layer, and is deep-cut in surface of silicon using the barrier layer multiple
Groove；
The highly doped polysilicon of N-type is filled inside groove, forms polysilicon gate；
Chemical mechanical grinding is carried out, the polysilicon of silica surface is removed, grinding stops at silicon dioxide blocking layer surface,
Retain the polysilicon inside groove, so that polysilicon be made to protrude silicon face；
The contact zone P+ is formed with trap technique is pushed away by ion implanting among N+ emitter, wherein the polysilicon gate protrusion
The N+ emitter or the contact zone P+ surface 1-2um setting；
By ion implanting and trap technique formation N-type field terminator is pushed away at the N-type base area back side；
P-type collector is formed by ion implanting and activation technology at the N-type field terminator back side.
5. the preparation method according to claim 4, which is characterized in that grown in N-type base area silicon faceDioxy
SiClx is then injected into energy in 50-100kev, dosage in 1E13-8E13cm as ion implanting barrier layer-2Between boron from
Son pushes away trap by high temperature, and temperature is between 1000-1150 DEG C, and time 50-200min forms p-type base area；Wherein, the N
The peak concentration of type base area is 1E13-2E14cm-3, the peak concentration of the p-type base area is 1E17-8E17cm-3, junction depth is in 3um
More than.
6. preparation method according to claim 5, which is characterized in that in the p-type base region surface Implantation Energy in 50kev
Above, dosage is greater than 1E15cm-2Arsenic ion, formed N+ emitter；The peak concentration of the N+ emitter is 1E19-
4E20cm-3, junction depth 0.2-1um.
7. according to preparation method described in claim 4 or 5 or 6, which is characterized in that between the N+ emitter inject boron from
Son forms the contact zone P+；The peak concentration of the contact zone P+ is 1E19-5E20cm-3, junction depth 0.2-1um；The p-type collection
The peak concentration of electrode is 1E19-5E19cm-3, junction depth 0.2-1um；The peak concentration of N-type field terminator is 5E15-
5E16cm-3, junction depth 1-2um.
8. the preparation method according to claim 4, which is characterized in that one layer of growthSilica make
For the barrier layer of etching groove, photoetching process is carried out over the barrier layer, is then used silica as barrier layer and is carried out groove
Etching, to form polysilicon gate.
9. the preparation method according to claim 4, which is characterized in that on the polysilicon gate, pass through high temperature furnace pipe
One layer of sacrificial oxide layer is grown, and falls sacrificial oxide layer using wet etching, to ensure the smooth of channel bottom and side wall；
High temperature furnace pipe grows trench wall gate oxide；Then carry out high temperature furnace pipe growing polycrystalline silicon again, polysilicon with a thickness of 1-
1.5um；Then chemical mechanical grinding is carried out, the polysilicon of silica surface is removed, mechanical lapping stops at silica
Barrier layer surface only retains the polysilicon inside groove.
10. according to preparation method described in claim 4 or 5 or 6 or 8 or 9, which is characterized in that utilize silica film forming work
Skill is grown on the surface of the polysilicon gate and the N+ emitterSilicon dioxide insulator medium
Layer；Then photoresist coating is carried out, exposure contact domain performs etching silicon dioxide insulator dielectric layer with mask.
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| CN109801911A (en) * | 2019-01-29 | 2019-05-24 | 上海擎茂微电子科技有限公司 | A kind of integrated IGBT device of mixing cellular type |
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