JPH0823092A - Semiconductor device and production process thereof - Google Patents

Abstract

PURPOSE:To provide a trench structured longitudinal MOS transistor improved so as to reduce the occupied area. CONSTITUTION:A gate insulation film 32 is formed on the inner wall faces of trenches 31 formed in a semiconductor substrate 1. Gate electrodes 34 are buried in the trenches 31 and protrudent up from the surface of the substrate 1. An insulation film 35 covers only the protrudent parts of the electrodes 34, without covering the surface region of the substrate 1. This device comprises a first impurity diffused layer 21 of a first conductivity type, first and second electrodes 41 and 42, third impurity diffused layer 11 of the first conduction type, and second impurity diffused layer 20 of a second conductivity type and operates the side faces of the trenches 31 as channels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to improvement of a power field effect transistor capable of passing a large current.
The present invention also relates to a method of manufacturing such a semiconductor device.

[0002]

2. Description of the Related Art FIG. 60 is a schematic view of US Pat.
A vertical field effect transistor having a trench structure, which is a first conventional example disclosed in US Pat.
It is sectional drawing of (it abbreviates as S).

Referring to FIG. 60, the semiconductor device has N
A + type single crystal silicon substrate 110 is provided. An N− type single crystal silicon epitaxial layer 111 is provided on the N + type single crystal silicon substrate 110. A trench 131 is formed in the N− type single crystal silicon epitaxial layer 111. The inner wall surface of the trench 131 is covered with a silicon oxide film 132 which is a gate insulating film. In the trench 131, polycrystalline silicon 134 containing N-type impurities, which serves as a gate electrode, is buried. The trench 1 is on the N− type single crystal silicon epitaxial layer 111.
P-type base diffusion layers 120 a and 120 b are provided on both sides of 31. In the P-type base diffusion layer 120a, N
A type source diffusion layer 121a is provided. An N-type source diffusion layer 121b is provided in the P-type base diffusion layer 120b. The insulating film 13 is formed on the gate electrode (134).
5 is covered. The source electrode 118 is connected to the N-type source diffusion layer 121a, and the source electrode 119 is connected to the N-type source diffusion layer 121b. A drain electrode 117 is connected to the back surface of the N + type single crystal silicon substrate 110.

Next, the operation will be described. Gate electrode 1
By applying a positive potential to 34, a channel is formed on the side surface of the trench 131. Arrow 122C1, 12
2C2, electrons move to the source electrode 11
A current flows between the drain electrodes 117 and the drain electrodes 117.

Such a trench MOS is a power MO.
It is called S, and can pass a large current and is used as a switch of a motor.

Next, a method of manufacturing the above trench MOS will be described. Referring to FIG. 61, an N− type single crystal silicon epitaxial layer 111 is formed on the entire upper surface of the N + type single crystal silicon substrate 110 by an epitaxial growth method, and subsequently, a photoengraving technique, an impurity ion implantation technique,
By repeating the impurity diffusion technique, the P-type base diffusion layer 120, N
The type source diffusion layer 121 is formed. Hereinafter, these are abbreviated as the silicon substrate 100. Then, the silicon substrate 10
A silicon oxide film 130 is formed on the surface of 0.

Next, referring to FIG. 62, the silicon oxide film 130 is patterned into a predetermined shape so as to serve as a mask for forming a trench later. Using the silicon oxide film 130 as a mask, a silicon etching technique is used to form an N-type source diffusion layer 121 in the silicon substrate 100.
And the trench 13 penetrating the P type base diffusion layer 120 and reaching the N − type single crystal silicon epitaxial layer 111.
1 is formed.

Referring to FIGS. 62 and 63, trench 13 is formed.
On the inner wall surface of No. 1, a silicon oxide film 13 to be a gate oxide film
Form 2

Next, referring to FIG. 64, the silicon substrate 10 is formed by using the CVD technique so that the polycrystalline silicon film 133 containing the N-type impurity is buried in the trench 131.
0, deposit.

64 and 65, the N-type polycrystalline silicon film 133 is formed until the upper surface thereof is located between the surface of the silicon substrate 100 and the lower surfaces of the N-type source diffusion layers 121a and 121b. Etch back. The upper surface 134a of the N-type polycrystalline silicon is located 0.25 to 0.5 μm below the surface of the silicon substrate 100. In this way,
A gate N-type polycrystalline silicon film 134 is formed.

Referring to FIG. 66, the surface of N-type polycrystalline silicon film 134 is oxidized to form silicon oxide film 135 on N-type polycrystalline silicon film 134. The silicon oxide film 135 is formed thicker than the oxide film 130 provided on the surface of the silicon substrate.
And the oxide film 130 formed on the surface of the silicon substrate 100.
Is almost flat. Even in this state, the upper surface 134a of the gate electrode (134) needs to be located below the surface of the silicon substrate 100 and above the lower surfaces of the N-type source diffusion layers 121a and 121b.

Finally, referring to FIGS. 66 and 67, silicon oxide film 130 formed on the surface of silicon substrate 100 is removed by etching, and P type base diffusion layer 120 is formed.
a, 120b and N-type source diffusion layers 121a, 121
Source electrodes 118 and 119 are formed on the silicon substrate 100 so as to be in contact with b. On the other hand, the drain electrode 117 is formed on the back surface of the N + type single crystal silicon substrate 110.

FIG. 68 is a second prior art trench MOS disclosed in US Pat. No. 4,767,722.
FIG. In FIG. 68, the same or corresponding parts as those of the semiconductor device shown in FIG. 67 are designated by the same reference numerals, and the description thereof will not be repeated.

In FIG. 68, reference numeral 123 represents a trench, reference numeral 124 represents a silicon oxide film serving as a gate insulating film, and reference numeral 125 represents N-type polycrystalline silicon of a gate electrode. The semiconductor device shown in FIG. 68 is different from the semiconductor device shown in FIG. 67 in that the gate N-type polycrystalline silicon 125 has a U-shaped cross section and the trench 123 is not completely filled. The point is that the crystalline silicon film 125 projects above the surface of the silicon substrate 100 and further extends laterally from the trench opening.

FIG. 69 shows an IEDM86P638-641.
FIG. 11 is a cross-sectional view of a third conventional trench MOS described in FIG. Parts which are the same as or correspond to those of the semiconductor device shown in FIG. 67 are designated by the same reference numerals, and description thereof will not be repeated. In FIG. 69, reference numeral 136 represents an interlayer insulating film for electrically separating the gate electrode 134 and the source electrode 118. The semiconductor device shown in FIG.
The difference from the semiconductor device shown in FIG. 60 is that the gate N-type polycrystalline silicon 134 projects above the surface of the silicon substrate 100 and further extends laterally from the trench opening.

The trench MOS shown in FIGS. 68 and 69.
The manufacturing method of is as follows. First, FIGS.
A process similar to the process shown in 4 is performed to form a trench, a gate oxide film, and an N-type polycrystalline silicon film. Subsequently, the gate N-type polycrystalline silicon film is patterned using a photolithography technique to form a U-shaped or T-shaped gate electrode laterally extending from the trench opening. Next, the interlayer insulating film 136 is formed, and the interlayer insulating film 136 is patterned by using a photolithography technique, thereby forming a contact region. Finally, a source electrode and a drain electrode are provided to complete the trench MOS.

FIG. 70 is a sectional view of a semiconductor device disclosed in Japanese Patent Laid-Open No. 17371/1992. A P-type diffusion region 2a is formed on an N-type silicon substrate 1a that serves as a drain. A high-concentration N-type diffusion region 3a serving as a source is formed inside the P-type diffusion region 2a. The trench 4 penetrates the N-type diffusion region 3a and the P-type diffusion region 2a.
a is formed. Gate oxide film 5a is formed on the sidewall of trench 4a. Gate electrode 6 is buried in trench 4a with gate oxide film 5a interposed. An interlayer insulating film 7 is provided on the silicon substrate 1a so as to cover the upper end portion of the gate electrode 6. The source electrode 8a is P
It is provided on the silicon substrate 1a so as to contact the type diffusion region 2a and the high-concentration N type diffusion region 3a. A drain electrode 9a is provided on the back surface of the silicon substrate 1a.

[0018]

[Problems to be Solved by the Invention] Conventional trench MOS
Had the following problems because it was configured as described above.

In the trench MOS shown in FIG. 60,
There are manufacturing problems. That is, referring to FIG.
The position of the upper surface 134a of the gate N-type polycrystalline silicon film 134 must be controlled accurately. This control requires expensive processing equipment and sophisticated processing technology. This is the first problem.

Further, referring to FIG. 66, the gate N-type polycrystalline silicon film 134 is oxidized to form the silicon oxide film 13.
In order to form No. 5, the position of the upper surface 134a of the gate N-type polycrystalline silicon film 134 is set in consideration of the amount of polycrystalline silicon consumed by this oxidation in advance from the film thickness of the silicon oxide film 135 and its forming conditions. There was the second problem that the decision had to be made accurately and with a margin.

If the position of the upper surface 134a of the gate N-type polycrystalline silicon film 134, which is the gate electrode, is not above the lower surfaces of the N-type source diffusion layers 121a and 121b, M
Since the function as the OS does not occur, the depth of the N-type source diffusion layers 121a and 121b is naturally determined, and as a result,
Third, it becomes difficult to reduce the size in the vertical direction (shallowness)
There was a problem. For this reason, since the P-type base diffusion layer and the trench depth cannot be made shallow, the capacitance between the gate electrode and the silicon substrate cannot be reduced.

In the trench MOS shown in FIG. 68,
Although there are no first, second and third problems described above, there is a fourth problem that the resistance of the gate electrode becomes high.

In addition, the gate N-type polycrystalline silicon film 125
Has a fifth problem in that it is difficult to reduce the size of the chip because it extends laterally from the trench opening.
That is, in the conventional manufacturing method, the formation of the trench, the formation of the gate electrode, and the formation of the contact region are performed by photolithography using their own masks. Therefore, a margin for mask alignment and a margin for processing (process margin such as etching) are required between the trench and the gate electrode and between the gate electrode and the contact region, which hinders the reduction of the chip. Become.

The trench MOS shown in FIG. 69 does not have the above-mentioned first, second, third and fourth problems, but has the above-mentioned fifth problem.

In the trench MOS shown in FIG. 70, since the end portion of the interlayer insulating film 7a is formed so as to spread in the horizontal direction, there is a problem in that high integration is hindered.

Therefore, an object of the present invention is to provide a trench MOS which can be manufactured without using expensive processing equipment or advanced processing technology.

Another object of the present invention is to improve the trench MO so that it can be easily downsized in the vertical direction.
To provide S.

Still another object of the present invention is to improve the trench MOS so that the resistance of the gate electrode does not become high.
Is to provide.

Still another object of the present invention is to provide an improved trench MOS which facilitates chip miniaturization.

Still another object of the present invention is to provide a method of manufacturing such a trench MOS.

[0031]

A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a front surface and a back surface. A trench is provided in the surface of the semiconductor substrate. The inner wall surface of the trench is covered with a gate insulating film. A gate electrode is embedded in the trench. The gate electrode is above the surface of the semiconductor substrate,
It is protruding. The width of the protruding portion of the gate electrode is equal to or less than the width of the portion of the gate electrode embedded in the trench. The semiconductor device further includes an insulating film provided so as to cover only the protruding portion of the gate electrode. The semiconductor device operates by using the side surface of the trench as a channel.

A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate having a front surface and a back surface. A trench is provided in the surface of the semiconductor substrate. The inner wall surface of the trench is covered with a gate insulating film. A gate electrode is embedded in the trench. The gate electrode projects above the surface of the semiconductor substrate. The protruding portion of the gate electrode is, as it goes upward,
Its width is narrowed. The device further includes an insulating film which is provided so as not to cover the surface region of the semiconductor substrate but to cover only the protruding portion of the gate electrode. The semiconductor device operates by using the side surface of the trench as a channel.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, first, a silicon substrate is prepared. A silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on the surface of the silicon substrate to form a three-layer film of these. The three-layer film is patterned, and then the patterned three-layer film is used as a mask to form a trench in the surface of the silicon substrate. A silicon oxide film serving as a gate oxide film is formed in the trench while leaving the three-layer film, and then polycrystalline silicon is deposited in the trench and on the surface of the silicon substrate. The polycrystalline silicon is etched back until the surface of the polycrystalline silicon is located above the surface of the silicon substrate and below the upper silicon oxide film of the three-layer film. The upper silicon oxide film of the three-layer film is etched so that the upper portion of the polycrystalline silicon is projected above the surface of the silicon substrate. The protruding polycrystalline silicon is oxidized to form a silicon oxide film thicker than the lower silicon oxide film of the three-layer film so as to surround the upper portion of the polycrystalline silicon. The silicon nitride film is removed by etching without using a mask. Leaving the silicon oxide film surrounding the upper part of the protruding polycrystalline silicon,
The silicon oxide film on the surface of the silicon substrate is completely removed, thereby forming a contact region. Form the desired electrode.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, first, a silicon substrate is prepared.
A silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially formed on the silicon substrate to form a three-layer film of these. The three-layer film is patterned so as to serve as a mask when forming a later trench,
Thereby, an opening having a predetermined shape is formed in the three-layer film. A trench is formed in the semiconductor substrate by using the patterned three-layer film as a mask. The side wall of the opening of the upper silicon oxide film in the three-layer film is etched to make the width of the opening wider than the width of the opening of the trench. A silicon oxide film serving as a gate oxide film is formed in the trench while leaving the three-layer film, and then polycrystalline silicon is deposited in the trench and on the surface of the silicon substrate. The upper surface of the polycrystalline silicon is above the surface of the silicon substrate, and until it is located below the uppermost silicon oxide film of the three-layer film,
Etch back the polycrystalline silicon. The uppermost silicon oxide film of the three-layer film is etched so that the upper portion of the polycrystalline silicon projects above the surface of the silicon substrate and laterally overhangs from the opening of the trench. The top of the crystalline silicon is exposed. The portion of the upper portion of the polycrystalline silicon which is laterally overhanging from the opening of the trench is oxidized, whereby the upper portion of the polycrystalline silicon is not laterally overhanging from the opening of the trench. Further, a silicon oxide film having a shape protruding above the surface of the silicon substrate and thicker than the lower silicon oxide film of the three-layer film is formed so as to surround the upper portion of the polycrystalline silicon. The silicon nitride film is removed by etching without using a mask. All the silicon oxide film on the surface of the silicon substrate is removed so that the silicon oxide film surrounding the upper portion of the protruding polycrystalline silicon is left, thereby forming a contact region. Form the desired electrode.

In the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, first, a silicon substrate is prepared.
A silicon oxide film is formed on the surface of the silicon substrate.
The silicon oxide film is patterned so as to serve as a mask for forming a later trench, thereby forming an opening having a predetermined shape in the silicon oxide film. A trench is formed in the semiconductor substrate by using the patterned silicon oxide film as a mask. The sidewall of the opening of the silicon oxide film is etched, thereby making the width of the opening wider than the width of the opening of the trench. While leaving the silicon oxide film, a silicon oxide film to be a gate oxide film is formed in the trench,
Then, polycrystalline silicon is deposited in the trench and on the surface of the silicon substrate. The polycrystalline silicon is etched back until the upper surface of the polycrystalline silicon is located above the surface of the silicon substrate and below the silicon oxide film formed on the semiconductor substrate. The silicon oxide film on the surface of the silicon substrate is etched so that the upper portion of the polycrystalline silicon projects above the surface of the silicon substrate and laterally projects from the opening of the trench. Expose the top. The upper portion of the polycrystalline silicon, and oxidize the portion laterally overhanging from the opening of the trench, thereby not laterally overhanging from the opening of the trench, and from the surface of the silicon substrate Polycrystalline silicon having a shape protruding upward is formed, and a silicon oxide film surrounding the upper portion of the polycrystalline silicon is formed. A contact region is formed, and then a desired electrode is formed.

[0036]

According to the semiconductor device of the first aspect of the present invention, the insulating film covering the protruding portion of the gate electrode does not cover the surface region of the semiconductor substrate but covers only the protruding portion of the gate electrode. Therefore, the insulating film does not spread in the horizontal direction.

According to the semiconductor device of the second aspect of the present invention, since the width of the protruding portion of the gate electrode is narrowed in the upward direction, the step coverage of the first electrode is improved.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the silicon nitride film is removed by etching without using a mask, mask alignment becomes unnecessary and the process is simplified.

According to the semiconductor device according to the fourth aspect of the present invention, the silicon oxide film on the surface of the silicon substrate is etched without using a mask, whereby the upper portion of the polycrystalline silicon is located above the surface of the silicon substrate. Since it is projected to the side, mask alignment becomes unnecessary, and the process is simplified.

According to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, since the silicon nitride film is removed by etching without using a mask, mask alignment becomes unnecessary, and the process is simplified.

[0041]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 1 is a sectional view of a trench MOS according to Example 1.

Referring to FIG. 1, an N− type single crystal silicon epitaxial layer 11 is formed on an N + type single crystal silicon substrate 10, and a P type base diffusion layer is formed on the N− type single crystal silicon epitaxial layer 11. The layer 20 is formed, and the N-type source diffusion layer 21 is formed in the surface of the P-type base diffusion layer 20. Hereinafter, these are referred to as the silicon substrate 1.
A trench 31 is formed in the silicon substrate 1 so as to penetrate the N-type source diffusion layer 21 and the P-type base diffusion layer 20 and reach the N − type single crystal silicon epitaxial layer 11. The inner wall surface of the trench 31 is covered with the gate insulating film 32. A gate electrode 34 formed of polycrystalline silicon containing N-type impurities is buried in the trench 31. The gate electrode 34 projects above the surface of the silicon substrate 1. The surface region of the silicon substrate 1 is not covered, and only the protruding portion of the gate electrode 34 is covered with the insulating film 35. A source electrode 41 is formed on the silicon substrate 1 so as to cover the gate electrode 34 and contact the N-type source diffusion layer 21 and the P-type base diffusion layer 20. A drain electrode 42 is provided on the back surface of the silicon substrate 1.

Next, the operation will be described. Gate electrode 3
By applying a positive potential to No. 4, a channel is formed on the side surface of the trench 31, electrons move along the path indicated by the arrow, and a current flows between the source electrode 41 and the drain electrode 42.

According to the embodiment, the insulating film 35 covering the protruding portion of the gate electrode 34 does not cover the surface region of the silicon substrate 1 but covers only the protruding portion of the gate electrode 34. Since 35 does not spread in the horizontal direction, the occupied area can be reduced. As a result, the size of the chip can be reduced.

FIG. 2 is a perspective view showing only the trench portion in the trench MOS shown in FIG. 1 by extracting it. FIG.
FIG. The trenches 31 are thus formed in stripes.

FIG. 4 is a plan view showing another shape of the trench used in the present invention. The trench 31 may be formed in a polygonal shape as shown in FIG.

Next, a method of manufacturing the trench MOS according to the first embodiment will be described. Referring to FIG. 5, N− type single crystal silicon epitaxial layer 11 is formed on N + type single crystal silicon substrate 10. A P-type base diffusion layer 20 is formed on the N− type single crystal silicon epitaxial layer 11. An N-type source diffusion layer 21 is formed in the surface of the P-type base diffusion layer 20. Hereinafter, the N + type single crystal silicon substrate 10, the N− type single crystal silicon epitaxial layer 11 and the P
The type base diffusion layer 20 and the N type source diffusion layer 21 are collectively referred to as a silicon substrate 1. On the surface of the silicon substrate 1,
The silicon oxide film 37 having a film thickness of 300Å is formed by, for example, thermal oxidation. Subsequently, a silicon nitride film 38 having a film thickness of 1000 Å is formed on the silicon oxide film 37 by, for example, CVD.
Deposited by the method. Subsequently, a silicon oxide film 30 having a film thickness of 8000Å is formed on the silicon nitride film 38 by, for example, CVD.
Deposited by the method. The silicon oxide film 30 serves as a mask during etching for forming a trench which will be performed later, and its film thickness may be a film thickness that can withstand this etching.

Referring to FIG. 6, silicon oxide film 30, silicon nitride film 38 and silicon oxide film 37 are patterned into a predetermined shape so as to serve as a mask for a trench to be formed later. Patterned silicon oxide film 30
With the mask as a mask, the trench 3 penetrating the N-type source diffusion layer 21 and the P-type base diffusion layer 20 in the silicon substrate 1 and reaching the N − -type single crystal silicon epitaxial layer 11
1 is formed.

Referring to FIG. 7, the inner wall surface of trench 31 is covered with a silicon oxide film 32 having a film thickness of 500 Å to be a gate oxide film. Then, a polycrystalline silicon film 33 containing N-type impurities is deposited on the silicon substrate 1 so as to be buried in the trench 31. The film thickness of the gate oxide film (32) can be appropriately changed according to the required electrical characteristics.

Referring to FIGS. 7 and 8, N-type polycrystalline silicon film 33 is etched back. At this time, etching is performed for a time longer than the time for completely etching the N-type polycrystalline silicon 33 on the silicon oxide film 30.
When the etching time is properly selected, the upper surface 34a of the N-type polycrystalline silicon 34 which will be the gate electrode is formed on the silicon oxide film 3
0 between the upper and lower surfaces. The position of the upper surface 34a of the N-type polycrystalline silicon 34 is preferably 2000 Å below the surface of the silicon oxide film 30. The etch back amount of the N-type polycrystalline silicon film 33 is 2000Å.

Referring to FIGS. 8 and 9, silicon oxide film 3 is formed.
0 is removed by etching, and the gate N-type polycrystalline silicon film 3
Expose the top of 4. At this time, the gate N-type polycrystalline silicon 34 projects upward from the surface of the silicon substrate 1 by about 7,000 Å.

Referring to FIGS. 9 and 10, a film thickness of 1000 is formed on the surface of the protruding portion of gate N-type polycrystalline silicon 34.
The Å silicon oxide film 35 is formed by a thermal oxidation method.
At this time, the position of the upper surface 34a of the N-type polycrystalline silicon film 34 projects from the surface of the silicon substrate 1 by about 6500Å. The protrusion amount t ₁ is determined by the film thickness of the silicon oxide film 30, the etching amount of the N-type polycrystalline silicon film 34, and the thickness of the silicon oxide film 35.
_It is preferable to change each condition so that it becomes ₁ . However, considering the subsequent steps, the gate oxide film 32
The film thickness t ₃₂ , the film thickness t ₃₇ of the silicon oxide film _37, and the film thickness t ₃₅ of the silicon oxide film 35 must be selected so as to satisfy the following inequalities.

T ₃₂ + t ₃₇ <t ₃₅ Referring to FIGS. 10 and 11, the silicon nitride film 38 and the silicon oxide film 37 are removed by etching without using a mask. The etching time of the silicon oxide film 37 depends on the film thickness t.
If it is done in a time suitable for ₃₇ , the film thickness of the silicon oxide film 35 becomes t ₃₅ -t ₃₇ (t ₃₅ -t ₃₇ > t ₃₂ ), and the withstand voltage between the gate and the source is more than that of the gate oxide film. To be kept.

Referring to FIG. 12, source electrode 41 is formed on the front surface of silicon substrate 1, and drain electrode 42 is provided on the back surface of silicon substrate 1 to complete the trench MOS.

Trench MOS configured in this way
Then, the problems found in the conventional trench MOS are solved, and the following effects are further provided.

The first effect is that the gate N-type polycrystalline silicon can be formed without using a sophisticated processing technique and without strict control. The second effect is that the depth of the N-type source diffusion layer 21 can be independently determined without being affected by other factors, and thus shallowing is easy. A third effect is that the trench, the gate electrode, and the contact region can be formed by self-alignment, so that there is no need for a mask alignment margin or a processed margin between the trench and the gate electrode and between the gate electrode and the contact region. Consequently, it is easy to downsize the chip. The fourth effect is that the resistance value of the gate electrode does not increase.

In the above embodiment, referring to FIG. 7, total thickness t _{10 of} silicon oxide film 30, silicon nitride film 38, and silicon oxide film 37, depth d _{10 of} trench 31, and trench ₁₀ are shown. The width w _{10 of} 31 preferably satisfies the following inequality.

(T ₁₀ + d ₁₀ ) / w ₁₀ ≦ 12 The above relationship is based on the relationship between the N-type polycrystalline silicon film 33 in FIG.
The relationship called the aspect ratio during the deposition of
_{When 10} + d ₁₀ ) / w ₁₀ > 12, it becomes difficult to completely fill the N-type polycrystalline silicon 33 to the bottom of the trench 31 or a cavity is formed in the N-type polycrystalline silicon. Cause The thickness t ₃₂ of the gate oxide film 32 of a general MOS satisfies the following inequality.

T ₃₂ << d ₁₀ , t ₃₂ << w ₁₀ Referring to FIGS. 7 and ₁ , the relationship between the trench depth d ₁ and the trench width w ₁ is as follows.

D ₁ ≡d ₁₀ , w ₁ ≡w ₁₀ Therefore, it is concluded that the relationship between t ₁₀ , d ₁ and w ₁ is preferably

(T_Ten+ D_Ten) / W_Ten≦ 12 Furthermore, referring to FIG. 1, gate N-type polycrystalline silicon
Protrusion t₁Considering its manufacturing method,₁≤t_TenWhen
Therefore, the protrusion amount t of the N-type polycrystalline silicon is ₁And training
Depth d₁And trench width w₁The relationship is
It would be desirable to satisfy the formula.

(T ₁ + d ₁ ) / w ₁ ≦ 12 Further, referring to FIG. 1, the protrusion amount t _{1 of the} polycrystalline silicon film is
The relationship between the trench width and the trench spacing w ₃ preferably satisfies the following inequality.

T ₁ / w ₃ ≦ 2 If the above relational expression is satisfied, the step coverage of the source electrode 41 is good, which leads to disconnection at the step portion,
There is no problem such as thinning and increase in resistance value.

In the above embodiment, the case of the MOS is illustrated, but the present invention is not limited to this, and GT
The present invention can also be applied to thyristors such as O, MCT and BRT.

Second Embodiment FIG. 13 is a sectional view of a trench MOS according to a second embodiment. Although the vertical MOS having a trench structure is illustrated in the first embodiment, the present invention is not limited to this, and the present invention also includes a lateral MOS transistor having a trench structure as shown in FIG. That is, the present invention can be applied to all semiconductor devices in which a channel is formed on the side surface of the trench and a current is passed in the vertical direction of the trench.

Referring to FIG. 13, trench 31 is provided in the surface of semiconductor substrate 1. The semiconductor substrate 1 includes a P-type base diffusion layer 20. The inner wall surface of the trench 31 is covered with the gate insulating film 32. In the trench 31, polycrystalline silicon 34, which is a gate electrode and contains N-type impurities, is formed.
Is embedded. The gate electrode 34 projects above the surface of the semiconductor substrate 1. The width of the protruding portion of the gate electrode 34 is made equal to the width of the portion embedded in the trench 31. The surface region of the semiconductor substrate 1 is not covered, and only the protruding portion of the gate electrode 34 is covered with the insulating film 35. In the surface of the semiconductor substrate 1 and the trench 31
An N-type source diffusion layer 21 and an N-type drain diffusion layer 22 are formed separately from each other on both sides. The source electrode 41 is connected to the N-type source diffusion layer 21. The drain electrode 42 is connected to the N-type drain diffusion layer 22.
The P-type base diffusion layer 20 operates as a channel.

By applying a positive potential to the gate electrode 34, a channel is formed on the side surface of the trench 31 and a current flows between the source electrode 41 and the drain electrode 42.

Example 3 FIG. 14 is a cross-sectional view of a vertical insulating film gate bipolar transistor having a trench structure (hereinafter referred to as trench IGBT) according to Example 3. The trench IGBT according to the third embodiment includes the P + type single crystal silicon substrate 12 and the N +.
Type single crystal silicon epitaxial layer 13, N-type single crystal silicon epitaxial layer 11 and P type base diffusion layer 20
And a silicon substrate 1 including. P-type base diffusion layer 2
An N-type emitter diffusion layer 23 is provided in the surface of 0. In the silicon substrate 1, the N-type emitter diffusion layer 23 and P
A trench 31 penetrating the type base diffusion layer 20 and reaching the N − type single crystal silicon epitaxial layer 11 is provided. The inner wall surface of the trench 31 is covered with the gate insulating film 32. N which is the gate electrode 34 in the trench 31
A polycrystalline silicon film containing type impurities is buried.
The gate electrode 34 projects above the surface of the semiconductor substrate 1. The width of the protruding portion of the gate electrode 34 is made equal to the width of the portion embedded in the trench 31. The surface area of the semiconductor substrate 1 is not covered, and only the protruding portion of the gate electrode 34 is covered with the insulating portion 35. Gate electrode 34
Of the N-type emitter diffusion layer 23 so as to cover the protruding portion of
An emitter electrode 43 is provided on the semiconductor substrate 1 so as to be in contact with the P-type base diffusion layer 20. A collector electrode 44 is provided on the back surface of the semiconductor substrate 1.

By applying a positive potential to the gate electrode 34, a channel is formed on the side surface of the trench 31 and a current flows between the emitter electrode 43 and the collector electrode 44.

Embodiment 4 This embodiment relates to another method of manufacturing the trench MOS shown in FIG.

Referring to FIG. 15, N− type single crystal silicon epitaxial layer 11 is formed on N + type single crystal silicon substrate 10, followed by P type base diffusion layer 20 and a plurality of N type source diffusion layers. 21 is formed. N + type single crystal silicon substrate 10, N− type single crystal silicon epitaxial layer 11, P type base diffusion layer 20, and N type source diffusion layer 21.
Hereinafter, the silicon substrate 1 will be collectively referred to as the silicon substrate 1.

A film thickness of 300Å is formed on the surface of the silicon substrate 1.
The silicon oxide film 37 is formed by, for example, a thermal oxidation method. Then, a film thickness of 1000 is formed on the silicon oxide film 37.
The Å silicon nitride film 38 is deposited by, for example, the CVD method. A silicon oxide film 30 having a film thickness of 8000Å is deposited on the silicon nitride film 38 by, for example, the CVD method. The silicon oxide film 30 serves as a mask at the time of etching for forming the trench, and its film thickness may be a film thickness that can withstand the etching at that time.

Referring to FIG. 16, the three-layer film formed of silicon oxide film 30, silicon nitride film 38, and silicon oxide film 37 is formed into a predetermined shape so as to serve as a mask for forming a trench later. Pattern. Silicon substrate 1 using patterned silicon oxide film 30 as a mask
And penetrates the N-type source diffusion layer 21 and the P-type base diffusion layer 20 into the N-type single crystal silicon epitaxial layer 11
A trench 31 extending to the above is formed.

Next, in order to remove the etching damage in the trench 31, the inner wall surface of the trench 31 is thermally oxidized,
A silicon oxide film (not shown; hereinafter referred to as a sacrificial oxide film) having a film thickness of 1000 Å is formed on the inner wall surface of the trench 31.

Thereafter, referring to FIG. 17, when removing the sacrificial oxide film, silicon oxide film 30 is simultaneously etched, and the surface of silicon oxide film 30 recedes from position 30a to position 30b. When the etching is performed by a wet method using, for example, hydrogen fluoride water, the silicon oxide film 30
Are etched by the same amount in the thickness and lateral directions. The etching amount is controlled by the etching time. For example, if only 2000Å is etched, the film thickness of the silicon oxide film 30 is 6000Å
Therefore, the side wall 30e of the opening of the silicon oxide film 30 is
It moves backward from the position of the side wall of the opening of the trench 31 by 2000 Å.

Referring to FIG. 18, the inner wall surface of trench 31 is covered with a silicon oxide film 32 having a film thickness of 500 Å to be a gate oxide film. Then, polycrystalline silicon 33 containing N-type impurities is deposited on the silicon substrate 1 so as to be buried in the trench 31.

Referring to FIGS. 18 and 19, the N-type polycrystalline silicon film 33 is etched back. At this time, etching is performed for a time longer than the time for completely removing the N-type polycrystalline silicon film 33 on the silicon oxide film 30 by etching.
That is, the polycrystalline silicon film 33 is etched back until its upper surface is located between the upper surface and the lower surface of the silicon oxide film 30. The position of the upper surface 34a of the N-type polycrystalline silicon 34 is 2000 from the position of the surface of the silicon oxide film 30.
Å It is preferable to be below.

Referring to FIGS. 19 and 20, silicon oxide film 30 is removed by etching. By this, the gate N
The type polycrystalline silicon film 34 protrudes above the surface of the silicon nitride film 38 by about 4000 Å, and extends over the opening of the trench 31 by about 2000 Å. This allows
A gate structure having a T-shaped cross section can be obtained.

Referring to FIGS. 20 and 21, the protruding portion of gate N-type polycrystalline silicon film 34 is thermally oxidized to form silicon oxide film 35. Silicon oxide film 3
The thickness of No. 5 is set to be equal to or larger than the thickness that oxidizes all the laterally protruding portions of the N-type polycrystalline silicon oxide film 34. For example, when the amount of overhang is 2000 Å, if the film thickness of the silicon oxide film 35 is set to about 4000 Å, the overhanging portion can be entirely oxidized, and as a result, the gate N-type polycrystalline silicon width is set to the opening of the trench 31. Can be equal to or less than the width of. By the thermal oxidation as described above, the gate having the T-shaped cross section becomes the gate having the I-shaped cross section. Since the silicon oxide film 35 serves as an interlayer insulating film between the source electrode and the gate electrode, it is advantageous that it is thick. However, since there is a trade-off relationship with the step coverage of the emitter electrode, the film thickness must be comprehensively considered. The film thickness of the silicon oxide film 35 is determined by the lateral extension of the gate N-type polycrystalline silicon film 34. However, the film thickness immediately after the deposition of the silicon oxide film 30, the etching amount of the silicon oxide film 30, the N-type polycrystalline silicon film 3 is taken into consideration while taking the protrusion amount t ₁ into consideration.
It is possible to freely select the film thickness of the silicon oxide film 30 by changing the conditions such as the etching amount (34a) of No. 4 and the like.

It is also possible to reduce the film thickness by forming the silicon oxide film 35 and then etching the entire surface again. However, given the subsequent steps, the relationship between the thickness t ₃₅ of the thickness t ₃₇ and silicon oxide film 35 having a thickness t ₃₂ and lower silicon oxide film 37 of the gate oxide film 32, to satisfy the following inequality Need to choose.

T ₃₂ + t ₃₇ <t ₃₅ Referring to FIGS. 21 and 22, the silicon nitride film 38 and the silicon oxide film 37 are etched without using a mask. If the etching time of the silicon oxide film 37 is set to a time suitable for the film thickness t ₃₇ , the silicon oxide film 3
5 of film thickness, made in _{t 35 -t 37 (t 35 -t} 37> t 32),
Since the withstand voltage between the gate and the source is kept higher than that of the gate oxide film, there is no problem in the characteristics of the semiconductor device.

Referring to FIG. 23, when source electrode 41 is formed on the front surface of silicon substrate 1 and drain electrode 42 is formed on the back surface of silicon substrate 1, trench MOS is completed.

According to the present embodiment, the trench MO is added by adding the step of sacrificial oxidation for removing the damage and the contamination generated during the etching for forming the trench.
The fifth effect of improving the electrical characteristics of S and the first to fourth effects produced in the first embodiment are obtained.

In the above embodiment, an example in which the present invention is applied to a vertical MOS having a trench structure has been shown, but the present invention is not limited to this, and a horizontal MOS having a trench structure and a vertical IGBT having a trench structure can be used. The present invention can be applied to all semiconductor devices in which a channel is formed on the side surface of a trench and a current is passed in the vertical direction of the trench.

Also in this embodiment, as in the first embodiment,
The following inequalities are preferably satisfied.

(T ₁ + d ₁ ) / w ₁ ≦ 12, t ₁ / w ₃ ≦ 2 Example 5 This example relates to still another manufacturing method of the trench MOS.

Referring to FIG. 24, N-type single crystal silicon epitaxial layer 11 is formed on N + type single crystal silicon substrate 10, and subsequently P type base diffusion layer 20 is formed thereon.
And a plurality of N-type source diffusion layers 21 are formed. Hereinafter, this is referred to as a silicon substrate 1.

On the surface of the silicon substrate 1, a film thickness of 8000Å
The silicon oxide film 30 is formed by, for example, the CVD method. The silicon oxide film 30 serves as a mask during etching for forming a trench, and its film thickness is
The film thickness may be enough to withstand the etching at that time.

Referring to FIG. 25, silicon oxide film 30
As a mask when forming a trench later,
Patterning into a predetermined shape. A trench 31 that penetrates the N-type source diffusion layer 21 and the P-type base diffusion layer 20 and reaches the N − -type single crystal silicon epitaxial layer 11 in the silicon substrate 1 by using the patterned silicon oxide film 30 as a mask. To form.

Referring to FIG. 26, for the purpose of removing etching damage in trench 31, a sacrificial oxide film having a film thickness of 1000 Å is formed in trench 31 by a thermal oxidation method (not shown). Thereafter, when the sacrificial oxide film is removed, the silicon oxide film 30 serving as an etching mask for forming the trench is also etched at the same time, and the surface thereof recedes from the position 30a to the position 30b. When this etching is performed by a wet method using hydrogen fluoride water,
The silicon oxide film 30 is etched by the same amount in the thickness direction and the lateral direction. This etching amount is controlled by the etching time. 200 for the silicon oxide film 30
If only 0Å is etched, the film thickness of the silicon oxide film 30 becomes 6000Å, and the side wall 30e of the opening of the silicon oxide film 30 recedes from the side wall surface of the trench 31 by 2000Å.

Referring to FIG. 27, a silicon oxide film 32 having a film thickness of 500 Å to be a gate oxide film is formed on the inner wall surface of trench 31. Then, a polycrystalline silicon film 33 containing N-type impurities is deposited on the silicon substrate 1 so as to be buried in the trench 31. Gate oxide film (32)
The film thickness of is properly changed according to the characteristics to be required.

Referring to FIGS. 27 and 28, N type polycrystalline silicon film 33 is etched back. At this time, etching is performed for a time longer than the time for completely etching the N-type polycrystalline silicon film 33 on the silicon oxide film 30. That is, etching is performed such that the position of the upper surface 34a of the N-type polycrystalline silicon film 34 is located 2000 Å below the surface of the silicon oxide film 30.

Referring to FIGS. 28 and 29, when the silicon oxide film 30 is removed by etching, the gate N-type polycrystalline silicon film 34 projects above the surface of the silicon substrate 1 by about 4000 Å, and from the opening of the trench 31. Next to 2000
A gate structure with an overhang of about Å and a T-shaped cross section can be obtained.

Referring to FIG. 30, the surface of the protruding portion of N-type polycrystalline silicon film 34 is oxidized by a thermal oxidation method to form silicon oxide film 35. The film thickness of the silicon oxide film 35 is set to be equal to or larger than the film thickness that oxidizes all the laterally overhanging portions of the N-type polycrystalline silicon film 34. For example, when the overhang is 2000 Å, the silicon oxide film 35
If the film thickness is set to about 4000Å, the overhanging portion can be entirely oxidized, and as a result, the width of the gate N-type polycrystalline silicon film is equal to or smaller than the width of the opening of the trench 31. Become. Further, on the upper surface of the gate N-type polycrystalline silicon film 34, the silicon oxide film 35 of the same thickness is also formed.
Is formed. The silicon oxide film 35 may be in the state as it is, or the entire film may be etched to reduce the film thickness or completely remove it.

The thickness of the silicon oxide film 35 is determined by the amount of lateral extension of the gate N-type polycrystalline silicon film 30, but the silicon oxide film 30 should be formed in consideration of the protruding portion t ₁ . It can be freely selected by changing conditions such as the film thickness immediately after the deposition, the etching amount of the silicon oxide film 30 and the etching amount (34a) of the N-type polycrystalline silicon film 34.

Referring to FIG. 31, an interlayer film having a film thickness of 8000Å is deposited on the surface of silicon substrate 1 by the CVD method.

Referring to FIG. 32, the interlayer film 36 is patterned by photolithography to form a contact region on the surface of the silicon substrate 1.

Finally, referring to FIG. 33, the source electrode 41 is formed on the front surface of the silicon substrate 1, and the drain electrode 42 is formed on the back surface of the silicon substrate 1 to complete the trench MOS.

According to the present embodiment, by adding a sacrificial oxidation step for removing damage and contamination caused during etching when forming a trench, the trench MOS is formed.
The fifth effect of improving the electrical characteristics of

In the present embodiment, an example in which the present invention is applied to a vertical MOS having a trench structure has been shown, but the present invention is not limited to this, and a horizontal MOS having a trench structure and a vertical IGBT having a trench structure can be used. The present invention can be applied to all semiconductor devices in which a channel is formed on the side surface of a trench and a current is passed in the vertical direction of the trench.

Also in this embodiment, as in the first embodiment,
The following inequalities are preferably satisfied.

(T ₁ + d ₁ ) / w ₁ ≦ 12, t ₁ / w ₃ ≦ 2 Example 6 FIG. 34 is a sectional view of a trench MOS according to Example 6.

Referring to FIG. 34, the trench MOS is concerned.
Comprises a silicon substrate 1. Silicon substrate 1 is N +
It includes a type single crystal silicon substrate 10, an N− type single crystal silicon epitaxial layer 11, a P type base diffusion layer 20, and an N type source diffusion layer 21. Penetrating the N-type source diffusion layer 21 and the P-type base diffusion layer 20 in the silicon substrate 1,
In addition, a trench 31 reaching the N − type single crystal silicon epitaxial layer 11 is formed. The inner wall surface of the trench 31 is covered with the gate insulating film 32. Trench 31
A gate electrode 34 protruding above the surface of the silicon substrate 1 is embedded therein. The width of the protruding portion of the gate electrode 34 becomes narrower in the upward direction. The surface region of the silicon substrate 1 is not covered, and only the protruding portion of the gate electrode 34 is covered with the insulating film 35. A source electrode 41 is formed on the front surface of the silicon substrate 1, and a drain electrode 42 is formed on the back surface of the silicon substrate 1.

According to the present embodiment, since the width of the protruding portion of the gate electrode 34 is narrowed as it goes upward, there is an advantage that the step coverage of the source electrode 41 is improved.

Next, a method of manufacturing the trench MOS shown in FIG. 34 will be described. First, the same processing as that shown in FIGS. 5 to 8 is performed.

Referring to FIG. 35, silicon oxide film 30
Is etched by 4000 Å, and the gate N-type polycrystalline silicon film 34 is projected above the surface of the silicon oxide film 30 by about 2000 Å. In the first embodiment, the silicon oxide film 30
However, in the present embodiment,
The feature is that the silicon oxide film 30 is left.

Referring to FIG. 36, the surface of the protruding portion of gate electrode 34 is oxidized by a thermal oxidation method to obtain a film thickness of 100.
A 0Å silicon oxide film 35a is formed.

Referring to FIGS. 36 and 37, silicon oxide film 30 and silicon oxide film 35a are etched. The etching amount is set so that the remaining film of the silicon oxide film 30 is about 2000 Å. At this time, the surface of the gate N-type polycrystalline silicon film 34 is consumed by oxidation, and a step is formed on the surface.

37 and 38, the surface of the protruding portion of gate electrode 34 is further oxidized by the thermal oxidation method to form a silicon oxide film 35b having a film thickness of 1000 Å.

Referring to FIGS. 38 and 39, silicon oxide film 30 and silicon oxide film 35b are all removed by etching.

Referring to FIG. 40, using the thermal oxidation method,
The protruding portion of the gate electrode 34 is further oxidized, and the film thickness is reduced to 1 again.
A 000Å silicon oxide film 35c is formed.

Referring to FIGS. 40 and 41, silicon nitride film 38 and silicon oxide film 37 are removed by etching without using a mask. The source electrode 41 is formed on the front surface of the silicon substrate 1, and the drain electrode 4 is formed on the back surface of the silicon substrate 1.
When 2 is formed, the trench MOS is completed.

According to the present embodiment, the surface of the gate N-type polycrystalline silicon film 34 becomes stepwise by repeating the oxidation process and the etching process as shown in FIGS. 36 to 38, and eventually the gate N-type polysilicon film 34. The width of the upper end portion of the crystalline silicon film 34 is narrower than the width of the trench opening portion. The number of repetitions of the oxidation step and the etching step, the thickness of the oxide film,
The etching amount can be freely selected in consideration of the protrusion amount t ₁ .

By using the method according to the sixth embodiment, it is possible to form a trench MOS as shown in FIGS. 42 and 43.

In these figures, the same or corresponding portions as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals, and the description thereof will not be repeated.

Embodiment 7 This embodiment relates to another method for manufacturing a trench MOS in which the width of the protruding portion of the gate electrode is narrowed as it goes upward.

First, the same processing as that shown in FIGS. 5 to 8 is performed. Referring to FIGS. 8 and 44, silicon oxide film 30 is etched to leave about 2000 Å, and gate N-type polycrystalline silicon film 34 is projected above the surface of silicon oxide film 30 by about 4000 Å.

Referring to FIG. 45, when the ion sputter etching method is used, the corners of the upper end of the protruding portion of the gate N-type polycrystalline silicon film 34 are etched quickly, and a gate structure 34 having a rounded upper portion is obtained. .

When the gate N-type polycrystalline silicon film 34 is isotropically etched, the upper surface and side surface of the projecting portion of the gate N-type polycrystalline silicon film 34 are simultaneously etched, and as shown in FIG. Sloped gate structure 34
Is obtained. If these etchings are performed continuously,
A rounded gate structure with a slope can be obtained.
The etching of the gate N-type polycrystalline silicon film 34 is not limited to the above-described method, and the method is such that the width of the upper end of the protrusion of the gate N-type polycrystalline silicon film 34 becomes narrower than the width of the trench opening after etching. If so, either method can be used.

Referring to FIGS. 45 and 46, gate electrode 34 is formed after silicon oxide film 30 is completely removed by etching.
The surface of the projecting portion on the upper part of is oxidized by a thermal oxidation method to form a silicon oxide film 35 having a thickness of 1000Å.

After that, the silicon nitride film 38 and the silicon oxide film 37 are removed by etching. Referring to FIG. 47, when source electrode 41 is formed on the front surface of silicon substrate 1 and drain electrode 42 is formed on the back surface of silicon substrate 1, trench MOS is completed.

In this embodiment, referring to FIG. 45, the etching amount of the gate N-type polycrystalline silicon film 34 was changed by changing the etching amount of the silicon oxide film 30 and the film thickness of the silicon oxide film 35. Considering t ₁ ,
You can choose freely. The gate N-type polycrystalline silicon film 34 may be etched with the silicon oxide film 30 remaining, or with the silicon nitride film 38 removed and the silicon oxide film 37 exposed. May be.

Using the method according to Example 7, FIG.
It is also possible to manufacture a trench MOS as shown in FIGS. 50, 51 and 52. In these drawings, the same or corresponding portions as those of trench MOS shown in FIG. 1 are designated by the same reference numerals, and the description thereof will not be repeated.

Embodiment 8 This embodiment relates to the case where the manufacturing method described in Embodiment 4 is applied to the manufacture of a conventional trench MOS.

First, the trench 31 is formed by the method shown in FIGS. Next, as shown in FIG. 17, a silicon oxide film (not shown; sacrificial oxide film) having a film thickness of 2000 Å is formed in the trench 31 by a thermal oxidation method. Then, when the sacrificial oxide film is removed, the silicon oxide film 30 serving as a mask for forming the trench is also etched at the same time. When the etching is performed by a wet method using, for example, hydrogen fluoride water, the silicon oxide film 30 is etched by the same amount in the thickness direction and the lateral direction. This etching amount is controlled by the etching time. For example, if the silicon oxide film 30 is etched by 3000Å, the film thickness of the silicon oxide film 30 becomes 5000Å,
The side wall 30e is 3000 Å from the opening of the trench 31.
Just retreat.

Referring to FIG. 18, a silicon oxide film 32 having a film thickness of 500 Å to be a gate oxide film is formed in trench 31. Then, a polycrystalline silicon film 33 containing N-type impurities is deposited on the surface of the silicon substrate 1 so as to be buried in the trench 31.

Referring to FIGS. 18 and 19, the N-type polycrystalline silicon film 33 is etched back. At this time, etching is performed for a time longer than the time for completely etching the N-type polycrystalline silicon film 33 on the silicon oxide film 30. That is, etching back is performed so that the position of the upper surface 34a of the N-type polycrystalline silicon film 34 is located 2000 Å below the surface of the silicon oxide film 30.

Referring to FIGS. 19 and 20, when silicon oxide film 30 is removed by etching, gate N-type polycrystalline silicon film 34 is formed above the surface of silicon nitride film 38.
A gate 3 having a T-shaped cross-section that protrudes by about 00Å and overhangs by about 3000Å from the opening of the trench 31.
4.

Next, referring to FIG. 53, the gate electrode (3
The surface of the upper part of 4) is thermally oxidized to form a silicon oxide film 35 having a film thickness of 1000Å. By this thermal oxidation, the surface of the N-type polycrystalline silicon film 34 is consumed, and the protrusion amount and the protrusion amount are both about 2500 Å. The amount of protrusion t ₁ and the amount of protrusion are the film thickness of the silicon oxide film 30, the etching amount of the silicon oxide film, the etching amount of the N-type polycrystalline silicon film 34, and the thickness of the silicon oxide film 35 formed in this step. The conditions are appropriately changed so that the protrusion amount t ₁ and the overhang amount are desired.

However, considering the subsequent steps, the film thickness t ₃₂ of the gate oxide film 32 and the film thickness t 37 of the lower silicon oxide film _37.
And the film thickness t of the silicon oxide film 35 formed in this step
The relation with ₃₅ must be chosen to satisfy the following inequalities.

T ₃₂ + t ₃₇ <t ₃₅ Referring to FIGS. 53 and 54, the silicon nitride film 38 and the silicon oxide film 37 are etched without using a mask. If the etching time of the silicon oxide film 37 is set to a time which is suitable for the film thickness t ₃₇ , the film thickness of the silicon oxide film 35 becomes t ₃₅ −t ₃₇ (t ₃₅ −t ₃₇ > t ₃₂ ). Since the withstand voltage between the gate electrode and the source is kept higher than the gate oxide film, no problem occurs in the characteristics of the semiconductor device.

Referring to FIG. 55, the source electrode 41 is formed on the front surface of the silicon substrate 1, and the drain electrode 42 is formed on the back surface of the silicon substrate 1, whereby the trench MOS is completed.

The vertical MOS having the trench structure manufactured in this manner has the same effect as that of the fourth embodiment,
Since the gate N-type polycrystalline silicon film overhangs in the lateral direction, the effect of reducing the pattern is small. However, as compared with the conventional technique, the lateral projection amount of the gate electrode can be easily controlled by controlling the etching amount of the silicon oxide film.

The present method can also be applied to all lateral semiconductors having a trench structure and trench IGBTs, as well as all semiconductor devices in which a channel is formed on the side surface of the trench and a current is passed in the vertical direction of the trench. Also in this embodiment, it is desirable to satisfy the following inequalities.

(T ₁ + d ₁ ) / w ₁ ≦ 12 Further, assuming that the interval between the N-type polycrystalline silicon films 34 is w ₅ , considering the step coverage of the source electrode 41,
It is desirable to satisfy the following inequalities.

T ₁ / w ₅ ≦ 2 Example 9 This example relates to a method for forming a conventional trench MOS by the manufacturing method shown in Example 5.

First, the same processing as that shown in FIGS. 24 to 29 is performed. Referring to FIGS. 24 and 25, trench 31 is formed. Referring to FIG. 26, a silicon oxide film having a film thickness of 2000 Å is formed in the trench by a thermal oxidation method (not shown; this is referred to as a sacrificial oxide film). After that, when the sacrificial oxide film is removed, the silicon oxide film 35 is also etched at the same time. If this etching is performed by a wet method using hydrogen fluoride water, for example, the silicon oxide film 30
Are etched by the same amount in the thickness and lateral directions. This etching amount is controlled by the etching time. For example, if the silicon oxide film 35 is 3000 Å
If it is etched only, the film thickness of the silicon oxide film 30 becomes 5
The side wall 30e of the silicon oxide film 30 becomes
Retreat 3000 Å from the opening of the trench.

Referring to FIG. 27, a silicon oxide film 32 having a film thickness of 500 Å to be a gate oxide film is formed in trench 31. Then, a polycrystalline silicon film 33 containing N-type impurities is deposited on the surface of the silicon substrate 1 so as to be buried in the trench 31.

Referring to FIG. 28, all of N-type polycrystalline silicon film 33 on silicon oxide film 30 is removed by etching, and N-type polycrystalline silicon film 34 is formed on upper surface 3 thereof.
Etching is performed until 4a is located 2000 Å below the surface of the silicon oxide film 30.

Referring to FIGS. 28 and 29, when the silicon oxide film 30 is removed by etching, the gate N-type polycrystalline silicon film 34 is formed above the surface of the silicon substrate 1 by 300.
It protrudes about 0Å and is 300 at the side of the trench opening.
A gate structure with a T-shaped cross-section can be obtained by overhanging about 0Å.

Referring to FIG. 56, a silicon oxide film 35 having a film thickness of 1000 Å is formed by a thermal oxidation method so as to cover the protruding portion of N-type polycrystalline silicon film 34. The surface of the protruding portion of the N-type polycrystalline silicon film 34 is oxidized by this oxidation, and the protruding amount and the protruding amount are both 250.
It becomes 0Å. The amount of protrusion t ₁ and the amount of protrusion are the film thickness of the silicon oxide film 30, the etching amount of the silicon oxide film 30, N
It is determined by the etching amount of the type polycrystalline silicon film 34 and the silicon oxide film 35 formed in this step, and the respective conditions are appropriately set so that the desired protrusion amount t ₁ and the overhang amount can be obtained. Can be changed. The step of forming the silicon oxide film 35 can be omitted.

Referring to FIG. 57, a film thickness of 80 is formed by the CVD method.
An 00Å interlayer film 36 is deposited on the silicon substrate 1.

57 and 58, the interlayer film 36 is etched to form a contact region on the surface of the silicon substrate 1.

Referring to FIG. 59, when source electrode 41 is formed on the front surface of silicon substrate 1 and drain electrode 42 is formed on the back surface of the silicon substrate, trench MOS is completed.

The vertical MOS having a trench structure manufactured in this manner has the same effect as that of the fifth embodiment, but the gate N-type polycrystalline silicon film overhangs in the lateral direction, so that the pattern reducing effect is achieved. Less than in Example 5. However,
Compared to the conventional technology, the lateral overhang of the gate electrode is
It can be easily controlled by controlling the etching amount of the silicon oxide film.

This method can also be applied to all lateral semiconductors having a trench structure and trench IGBTs, as well as semiconductor devices in which a channel is formed on the side surface of the trench and a current is passed in the vertical direction of the trench.

Also in the present embodiment, it is preferable to implement so as to satisfy the following inequality.

(T ₁ + d ₁ ) / w ₁ ≦ 12 Further, when the interval between the N-type polycrystalline silicons 34 is w ₅ , considering the step coverage of the source electrode 41, it is preferable to satisfy the following relational expression. .

T ₁ / w ₅ ≤2 Embodiment 10 In the above embodiment, the cross-sectional view shows that the upper surface of the gate N-type polycrystalline silicon 34 is entirely flat.
The present invention is not limited to this. Trench 31
In the case where the film thickness of the N-type polycrystalline silicon film 33 for filling the gates is not reduced or is not sufficiently flattened, the upper surface of the gate N-type polycrystalline silicon film 34 has a concave shape. The same effect can be obtained in this state. In this case, there is an advantage that the film thickness of the N-type polycrystalline silicon 33 is thinned to improve productivity, and a planarization step can be omitted, and a drawback that the processing of the gate N-type polycrystalline silicon film 34 is slightly difficult. Both occur at the same time. Therefore, whether the upper surface of the gate N-type polycrystalline silicon 34 is a flat surface or a concave shape may be freely selected in consideration of the above advantages and disadvantages.

[0151]

As described above, according to the semiconductor device of the first aspect of the present invention, the insulating film covering the protruding portion of the gate electrode does not cover the surface region of the semiconductor substrate, and the protruding portion of the gate electrode is not covered. Since only the part is covered, the insulating film does not spread in the horizontal direction, and thus the occupied area can be reduced.

According to the semiconductor device of the second aspect of the present invention, the width of the projecting portion of the gate electrode is made narrower in the upward direction, so that the step coverage of the first electrode is improved. Play.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the silicon nitride film is removed by etching without using a mask, mask alignment becomes unnecessary, and the process is simplified.

According to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, the silicon oxide film on the surface of the silicon substrate is etched without using a mask, whereby the upper portion of the polycrystalline silicon is covered with the silicon substrate. Since it is projected above the surface, mask alignment is not necessary, and the process is simplified.

According to the method of manufacturing a semiconductor device according to the fifth aspect of the present invention, since the silicon nitride film is removed by etching without using a mask, mask alignment becomes unnecessary and the process is simplified.

[Brief description of drawings]

FIG. 1 is an MO of a trench structure according to an embodiment of the present invention.
It is sectional drawing of an S transistor.

FIG. 2 is a perspective view of a trench formed in the present invention.

FIG. 3 is a plan view of a trench formed in the present invention.

FIG. 4 is a plan view of another embodiment of the trench adopted in the present invention.

FIG. 5 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 6 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 7 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 8 is a cross-sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 9 is a sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 10 is a sectional view of the semiconductor device in a sixth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 11 is a cross-sectional view of the semiconductor device in a seventh step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 12 is a cross-sectional view of the semiconductor device in an eighth step of the order of the method for manufacturing the semiconductor device according to the first embodiment.

FIG. 13 is a sectional view of a MOS transistor having a trench structure according to a second embodiment.

FIG. 14 is a cross-sectional view of a trench-structure MOS transistor according to a third embodiment.

FIG. 15 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 16 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 17 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 18 is a cross-sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 19 is a sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 20 is a sectional view of the semiconductor device in a sixth step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 21 is a sectional view of the semiconductor device in a seventh step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 22 is a sectional view of the semiconductor device in an eighth step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 23 is a sectional view of the semiconductor device in a ninth step of the order of the method for manufacturing the semiconductor device according to the fourth embodiment.

FIG. 24 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 25 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 26 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 27 is a sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 28 is a sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 29 is a cross-sectional view of the semiconductor device in a sixth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 30 is a cross-sectional view of the semiconductor device in a seventh step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 31 is a sectional view of the semiconductor device in an eighth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 32 is a cross-sectional view of the semiconductor device in a ninth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 33 is a sectional view of the semiconductor device in a tenth step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 34 is a sectional view of the semiconductor device in a eleventh step of the order of the method for manufacturing the semiconductor device according to the fifth embodiment.

FIG. 35 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 36 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 37 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 38 is a sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 39 is a sectional view of the semiconductor device in a fifth step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 40 is a sectional view of the semiconductor device in a sixth step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 41 is a sectional view of the semiconductor device in a seventh step of the order of the method for manufacturing the semiconductor device according to the sixth embodiment.

FIG. 42 is a cross-sectional view of another vertical MOS transistor having a trench structure, which is manufactured by the method according to the sixth embodiment.

FIG. 43 is a cross-sectional view of still another vertical MOS transistor having a trench structure, which is manufactured by the method according to the sixth embodiment.

FIG. 44 is a sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 45 is a cross-sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 46 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 47 is a sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the seventh embodiment.

FIG. 48 is a cross-sectional view of another vertical MOS transistor having a trench structure, which is manufactured by the method of Example 7.

FIG. 49 is a cross-sectional view of still another vertical MOS transistor having a trench structure, which is manufactured by the method according to the seventh embodiment.

FIG. 50 is a cross-sectional view of still another vertical MOS transistor having a trench structure, which is manufactured by the method according to the seventh embodiment.

FIG. 51 is a cross-sectional view of still another vertical MOS transistor having a trench structure, which is manufactured by the method according to the seventh embodiment.

FIG. 52 is a cross-sectional view of still another vertical MOS transistor having a trench structure, which is manufactured by the method according to the seventh embodiment.

FIG. 53 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the eighth embodiment.

FIG. 54 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the eighth embodiment.

FIG. 55 is a cross-sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the eighth embodiment.

FIG. 56 is a cross-sectional view of the semiconductor device in a first step of the order of the method for manufacturing the semiconductor device according to the ninth embodiment.

FIG. 57 is a sectional view of the semiconductor device in a second step of the order of the method for manufacturing the semiconductor device according to the ninth embodiment.

FIG. 58 is a sectional view of the semiconductor device in a third step of the order of the method for manufacturing the semiconductor device according to the ninth embodiment.

FIG. 59 is a cross-sectional view of the semiconductor device in a fourth step of the order of the method for manufacturing the semiconductor device according to the ninth embodiment.

FIG. 60 is a sectional view of a conventional vertical MOS transistor having a trench structure.

FIG. 61 is a cross-sectional view of the semiconductor device in the first step of the order of the conventional method for manufacturing a semiconductor device.

FIG. 62 is a cross-sectional view of the semiconductor device in the second step of the order of the conventional method for manufacturing a semiconductor device.

FIG. 63 is a sectional view of a semiconductor device in a third step of the order of the conventional method for manufacturing a semiconductor device.

FIG. 64 is a sectional view of a semiconductor device in a fourth step of the order of the conventional method for manufacturing a semiconductor device.

FIG. 65 is a cross-sectional view of the semiconductor device in a fifth step of the order of the conventional method for manufacturing a semiconductor device.

FIG. 66 is a cross-sectional view of the semiconductor device in a sixth step of the order of the conventional method for manufacturing a semiconductor device.

67 is a sectional view of the semiconductor device in a seventh step of the order of the conventional method for manufacturing a semiconductor device. FIG.

FIG. 68 is a cross-sectional view of another conventional semiconductor device.

[FIG. 69] Yet another conventional vertical M having a trench structure.
It is sectional drawing of an OS transistor.

[FIG. 70] Yet another conventional vertical M having a trench structure
It is sectional drawing of an OS transistor.

[Explanation of symbols]

1 semiconductor substrate, 11 third impurity diffusion layer, 20 second impurity diffusion layer, 21 first impurity diffusion layer, 31
Trench, 32 gate insulating film, 34 gate electrode, 3
5 insulating film, 41 1st electrode, 42 2nd electrode.

Claims (18)

[Claims] 1. A semiconductor substrate, a trench provided on the surface of the semiconductor substrate, a gate insulating film that covers an inner wall surface of the trench, and a gate insulating film embedded in the trench and more than a surface of the semiconductor substrate. A gate electrode protruding upward, and a width of a protruding portion of the gate electrode is
The width is equal to or less than the width of the portion embedded in the trench, and the device further includes an insulating film provided so as to cover only the protruding portion of the gate electrode, A semiconductor device in which the side surface of the trench operates as a channel. 2. A first device provided on the surface of the semiconductor substrate.
Further, and a second electrode provided on the back surface of the semiconductor substrate, and a current is passed between the first electrode and the second electrode in a direction perpendicular to the semiconductor substrate. The semiconductor device according to claim 1. 3. The semiconductor device further comprises a first electrode and a second electrode formed on the semiconductor substrate and separated from each other, and a current flows from the first electrode to the second electrode. Item 2. The semiconductor device according to item 1. 4. A first conductive type first conductive layer provided in the surface of the semiconductor substrate so as to contact the first electrode, and on both sides of the gate electrode; A third conductive layer of a first conductivity type provided in the back surface of the semiconductor substrate so as to come into contact with the second electrode; and in the semiconductor substrate, the first conductive layer and the third conductive layer. A second conductive layer of a second conductivity type, which is provided between the conductive layer of the semiconductor substrate and the second conductive layer of the second conductive type, the trench extending from the surface of the semiconductor substrate into the third conductive layer. The semiconductor device according to claim 2, which has reached. 5. The semiconductor substrate is made of silicon, the gate insulating film is made of a silicon oxide film, and the gate electrode is made of polycrystalline silicon containing p-type or n-type impurities. The semiconductor device according to claim 1, which is provided. 6. The semiconductor device according to claim 4, wherein the first conductive layer is a source region, and the third conductive layer is a drain region. 7. A first conductivity type first region, which is an emitter region provided in the surface of the semiconductor substrate so as to contact the first electrode and on both sides of the gate electrode. A conductive layer, a second conductive type second conductive layer provided in the semiconductor substrate and in contact with the first conductive layer, and the semiconductor so as to contact the second electrode. A second conductive type fourth conductive layer, which is a collector region, provided in the back surface of the substrate; and the second conductive layer and the fourth conductive layer in the semiconductor substrate. The third of the first conductivity type provided between
3. The semiconductor device according to claim 2, further comprising: a conductive layer according to claim 2, wherein the trench extends from a surface of the semiconductor substrate into the third conductive layer. 8. A semiconductor substrate, a trench provided on a surface of the semiconductor substrate, a gate insulating film that covers an inner wall surface of the trench, and a gate insulating film embedded in the trench and more than a surface of the semiconductor substrate. A gate electrode protruding upward, and the width of the protruding portion of the gate electrode becomes narrower in an upward direction, and the device further covers the protruding portion of the gate electrode. A semiconductor device, comprising: an insulating film provided on a substrate, wherein the side surface of the trench operates as a channel. 9. A first device provided on the surface of the semiconductor substrate.
Further, and a second electrode provided on the back surface of the semiconductor substrate, and a current is applied between the first electrode and the second electrode in a direction perpendicular to the semiconductor substrate. 9. The semiconductor device according to claim 8, wherein the semiconductor device flows. 10. The semiconductor device further comprises a first electrode and a second electrode which are formed on the semiconductor substrate and are separated from each other, and a current flows from the first electrode to the second electrode. Item 9. The semiconductor device according to item 8. 11. The protrusion amount of the protrusion portion of the gate electrode is t ₁ , and the depth of the trench is d ₁ .
9. The semiconductor device according to claim 1, further satisfying the following inequality, where w ₁ is the width of the trench. (T ₁ + d ₁ ) / w ₁ ≦ 12 12. The following inequality is satisfied, where t ₁ is the amount of protrusion of the protruding portion of the gate electrode and w ₃ is the distance between the trench and an adjacent trench adjacent to the trench. Item 9. The semiconductor device according to item 1 or 8. t ₁ / w ₃ ≦ 2 13. A step of preparing a silicon substrate, a step of sequentially forming a silicon oxide film, a silicon nitride film, and a silicon oxide film on a surface of the silicon substrate to form a three-layer film thereof, the three-layer film Patterning the film, then using the patterned three-layer film as a mask to form a trench in the surface of the silicon substrate; and leaving the three-layer film, a gate oxide film in the trench. Forming a silicon oxide film, and then depositing polycrystalline silicon in the trench and on the surface of the silicon substrate; and an upper surface of the polycrystalline silicon above the surface of the silicon substrate, and Etching back the polycrystalline silicon until it is located below the upper silicon oxide film of the three-layer film; and etching the upper silicon oxide film of the three-layer film. And exposing the upper portion of the polycrystalline silicon so as to project above the surface of the silicon substrate, and oxidizing the projected polycrystalline silicon from the lower silicon oxide film of the three-layer film. A thicker silicon oxide film so as to surround the upper portion of the protruding polycrystalline silicon, a step of etching away the silicon nitride film without a mask, and a step of removing the upper portion of the protruding polycrystalline silicon. Manufacture of a semiconductor device including a step of removing the entire silicon oxide film on the surface of the silicon substrate so as to leave a surrounding silicon oxide film, thereby forming a contact region, and a step of forming a desired electrode. Method. 14. A step of preparing a silicon substrate, a step of sequentially forming a silicon oxide film, a silicon nitride film, and a silicon oxide film on the silicon substrate, thereby forming these three-layer films, Patterning the three-layer film so as to serve as a mask for forming a later trench, thereby forming an opening of a predetermined shape in the three-layer film, and the patterned three-layer film Using a mask as a mask, a step of forming a trench in the semiconductor substrate, etching the sidewall of the opening of the upper silicon oxide film in the three-layer film, the width of the opening is the width of the opening of the trench. A step of increasing the width, and a silicon oxide film to be a gate oxide film is formed in the trench while leaving the three-layer film, and then polycrystalline silicon is formed in the trench and the silicon base film. A step of depositing on the surface of the polycrystalline silicon, the upper surface of the polycrystalline silicon, above the surface of the silicon substrate, and until it is located below the uppermost silicon oxide film of the three-layer film, Etching back the polycrystalline silicon, etching the uppermost silicon oxide film of the three-layer film, the upper portion of the polycrystalline silicon protrudes above the surface of the silicon substrate, and from the opening of the trench Laterally overhanging, exposing the upper portion of the polycrystalline silicon, and oxidizing the portion of the upper portion of the polycrystalline silicon, which is laterally overhanging from the opening of the trench, thereby, The upper portion of the polycrystalline silicon is formed so as not to project laterally from the opening of the trench and protrudes above the surface of the silicon substrate, and the lower layer film of the three-layer film is formed. A step of forming a silicon oxide film thicker than a conoxide film so as to surround the upper portion of the polycrystalline silicon; a step of removing the silicon nitride film by etching without a mask; A step of removing all of the silicon oxide film on the surface of the silicon substrate so as to leave the surrounding silicon oxide film, thereby forming a contact region, and a step of forming a desired electrode. Production method. 15. A step of preparing a silicon substrate, a step of forming a silicon oxide film on a surface of the silicon substrate, and a step of patterning the silicon oxide film so as to serve as a mask for forming a trench later. , Thereby forming an opening of a predetermined shape in the silicon oxide film, forming a trench in the semiconductor substrate by using the patterned silicon oxide film as a mask, and the silicon oxide film Etching the side wall of the opening, thereby making the width of the opening wider than the width of the opening of the trench, and leaving the silicon oxide film in the trench,
A silicon oxide film to be a gate oxide film is formed, and then
Depositing polycrystalline silicon in the trench and on the surface of the silicon substrate, and the upper surface of the polycrystalline silicon is above the surface of the silicon substrate and the silicon formed on the semiconductor substrate. Etching back the polycrystalline silicon until it is located below the oxide film, and etching the silicon oxide film on the surface of the silicon substrate so that the upper portion of the polycrystalline silicon is above the surface of the silicon substrate. To expose the upper portion of the polycrystalline silicon so as to project laterally from the opening of the trench, and the upper portion of the polycrystalline silicon, and in the lateral direction from the opening of the trench. Oxidize the overhang, so that it does not overhang laterally from the opening of the trench and projects above the surface of the silicon substrate. Forming polycrystalline silicon having a different shape and forming a silicon oxide film surrounding the upper portion of the polycrystalline silicon; forming a contact region; and then forming a desired electrode. Manufacturing method of semiconductor device. 16. The method of manufacturing a semiconductor device according to claim 14, wherein the upper portion of the polycrystalline silicon projects above the surface of the silicon substrate and extends laterally from the opening of the trench. So as to expose the upper portion of the polycrystalline silicon, and a step of forming a silicon oxide film so as to surround the polycrystalline silicon, as a result, the upper portion of the polycrystalline silicon, A method of manufacturing a semiconductor device, which has a shape that laterally overhangs from an opening of a trench and projects above the surface of the silicon substrate. 17. The method of manufacturing a semiconductor device according to claim 13, wherein an upper portion of the polycrystalline silicon is projected above a surface of the silicon substrate, The step of oxidizing the polycrystalline silicon and etching the obtained oxide film is repeated, and as a result, the upper diameter of the polycrystalline silicon protruding above the surface of the silicon substrate is filled in the trench. A method for manufacturing a semiconductor device, wherein the diameter is smaller than the diameter of the embedded polycrystalline silicon. 18. The method of manufacturing a semiconductor device according to claim 13, wherein an upper portion of the polycrystalline silicon is projected above a surface of the silicon substrate. , (A) and (b) below
An etching step selected from the group consisting of, as a result, the diameter of the upper portion of the polycrystalline silicon protruding above the surface of the silicon substrate, the diameter of the polycrystalline silicon embedded in the trench A method for manufacturing a semiconductor device which is reduced in size. (A) Isotropically etching the polycrystalline silicon. (B) Etching for rounding the corners of the upper surface of the polycrystalline silicon.