TWI646606B - Grooved power transistor manufacturing method - Google Patents

Abstract

The invention relates to a trench type power transistor manufacturing method, in which a predetermined layer formed on a substrate is developed and etched by a general mask process, and the position of the reserved layer determines the conductive pillar trench ( Contact) and the position of the gate trenches in the substrate, which are not affected by the subsequent fabrication steps and cause offset problems to achieve precise control of the position of the conductive posts and gates; in the case of non-high-end machines High-density component arrangement with low-cost manufacturing process ensures the yield and stability of power transistors.

Description

Grooved power transistor manufacturing method

The invention relates to a power transistor manufacturing method, in particular to a groove type power transistor method with good alignment accuracy.

Trench power transistors mainly include metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). Currently, the output current of trench power transistors is improved. In the process, try to reduce the width of the cell pitch. When the cell pitch is smaller, it means that a larger number of trenches can be produced in a unit area, so that the trench power transistor Can output higher current.

At present, most manufacturers mainly manufacture trench power transistors with 6-inch and 8-inch wafers. But even with the high-end yellow light machine using DUV technology (Deep UV), the ability to make the smallest cell pitch is about 0.8μm, making it difficult to further shrink. Moreover, multiple exposure steps are involved in the yellow light process, which tends to cause accumulated alignment deviations, resulting in offsets in internal components (such as electrode regions) or inconsistent regional sizes, and the electrical characteristics of the product become unstable. The problem of low yield is generated. As shown in FIG. 16, the cell pitch is represented by P, and the gate pitch (mesas) is represented by M, and the widths of adjacent source regions are A and B, respectively. The position of the conductive pillars is offset, so the current I cannot be evenly distributed in the source region.

In addition, the high-end yellow light machine also needs to be used with a fine mask, so the production cost will inevitably increase.

The main purpose of this creation is to provide a "grooved power transistor manufacturing method" that can effectively reduce the gate spacing (mesas) below 0.8μm without using the DUV high-end yellow light machine. The accuracy of the alignment between the components.

The "grooved power transistor manufacturing method" of the present invention mainly comprises the following steps: a. preparing a substrate, forming a reserved layer on the top surface of the substrate; b. forming a hard mask layer in the reservation a top surface of the layer; c. defining and forming a plurality of first openings in the hard mask layer, the hard mask layer being divided into a plurality of mask blocks by the first openings; d. etching removal is not covered by the plurality a reserved layer covered by the cover block; e. forming a partition wall on each side of the mask block, the partition walls having the same width, and a space between the adjacent two partition walls; f. Each of the spaced locations forms a gate trench, each of the gate trenches extending downward from a top surface of the substrate, and a spacing between adjacent two gate trenches is less than 1 micrometer; g. in the gate trench Filling a conductive layer in the interior of the trench and each of the first openings; h. defining a gate bus region and a source implanted region in the conductive layer, and removing a portion of the conductive layer Forming a plurality of gate row openings and a planting zone opening, wherein a width of the opening of the implanting zone is greater than a width of the opening of the gate row; i. a plurality of source regions are formed inside the substrate of the opening of the cloth value region; j. comprehensively covering an insulating layer, and etching and removing a part of the insulating layer to form a plurality of upper pillars of the conductive pillars, and the center of the upper trenches of the conductive pillars Positioning is aligned with the center of the reserved layer; k. removing each of the reserved layer and the substrate below it to form a plurality of lower pillars of the conductive pillars, the lower trenches of each of the conductive pillars and the upper trench of the corresponding conductive pillar The slots are connected to form a conductive column trench; l. Filling a conductive material inside each of the conductive pillar trenches to form a plurality of conductive pillars, each conductive pillar and the insulating layer being coplanar.

The creation of the reserved layer position determines the position of the conductive column trench and the gate trench at the initial stage of the process, ensuring that the position is not affected by the subsequent fabrication steps, and the offset problem is achieved, and the conductive column and the gate are accurately controlled. position.

300‧‧‧ Reserved layer

303‧‧‧First insulation

306‧‧‧Second insulation

309‧‧‧ third insulation layer

310‧‧‧The upper groove of the conductive column

313‧‧‧Self-aligned docking area

316‧‧‧The lower groove of the conductive column

319‧‧‧Oxide layer

600‧‧‧ Conductive layer

603‧‧‧ gate oxide layer

606‧‧‧First gap

609'‧‧‧Oxide

609‧‧‧Second gap

610‧‧‧ corner

619‧‧‧Insulation

723‧‧‧ first opening

729‧‧‧Mask block

753‧‧‧ interval

726‧‧‧gate opening

756‧‧‧planting area opening

900‧‧‧Substrate

903‧‧‧Base area

906‧‧‧ source area

909‧‧‧Contact area

910‧‧ ‧ gate trench

913‧‧‧conductive column

916‧‧‧Surface metal layer

919‧‧‧P type doping

M‧‧‧ gate spacing

P‧‧‧cell spacing

Figure 1: Schematic representation of the creation of a reserved layer on the surface of a substrate.

Figure 2: Schematic representation of the creation of a hard mask layer on the reserved layer.

Figure 3: Schematic illustration of the etching of the hard mask layer.

Figure 4: Schematic diagram of etching the reserved layer by this creation.

Figure 5: Schematic representation of the creation of a first spacer.

6A-6B: Schematic diagram of the creation of a second spacer.

Figure 7: Schematic diagram of the gate trench formed by this creation.

Figure 8: Schematic diagram of the creation of a gate oxide layer.

Figure 9: Schematic diagram of the creation of a conductive layer in the gate trench.

Fig. 10 is a schematic view showing the creation of a source region in the first embodiment.

Figure 11 is a schematic view showing the creation of a source region in the second embodiment of the present invention.

Figure 12: Schematic representation of the creation of the upper trench of the conductive post.

Figure 13: Schematic representation of the creation of a complete conductive column trench.

Figure 14: Schematic representation of the creation of a complete conductive column.

Figure 15: Schematic representation of the creation of an IGBT.

Figure 16: Schematic diagram of the positional shift of the conductive column of a conventional power transistor.

Referring to FIG. 1 , the present invention firstly prepares a substrate 900. Here, the substrate 900 is exemplified by an N+ tantalum substrate. In order to fabricate a high voltage resistant power component, a surface is usually formed on the surface of the substrate 900. A seed layer (N epi) is formed on the surface of the substrate 900. The reserved layer 300 is a semiconductor layer. The preparation layer 300 is formed by a method including, but not limited to, poly deposition, single crystal germanium. Epitaxy, implantation, and the like.

Referring to FIG. 2, a hard mask layer is formed on the surface of the reserved layer 300, and the hard mask layer is a composite layer structure, which can provide high etching resistance, in this embodiment. The hard mask layer comprises a first silicon oxide layer 303, a second nitride layer 306 and a third silicon oxide layer 309 formed by sequentially depositing from bottom to top. Wherein, depending on the depth of the gate trench to be fabricated (refer to FIG. 7), the thickness of the foregoing layers may be appropriately determined. For example, the gate trench: the reserved layer 300: the first insulating layer 303: the second The insulating layer 306: the third insulating layer 309 may have a thickness ratio of 4.4:1.6:0.1:0.7:1.6.

Referring to FIG. 3, a first yellow light process is performed on the hard mask layer, and a first mask is used to define a position of the first opening 723 in the hard mask layer, and the first method is used to remove the first opening 723. An unmasked hard mask layer exposes the reserved layer 300; at the same time, the unetched hard mask layer is formed as a plurality of mask blocks 729, and the width of each of the mask blocks 729 determines the electrical The width of the conductive connection of the connection also indirectly determines the width of the gate trench, which will be further explained later. In this step, the width of the mask block 729 can be between 0.3 μm and 0.4 μm. Because the width of the first opening 723 is large, it is not necessary to use a special high-end groove mask and a high-end yellow light machine. Can save production costs.

Referring to FIG. 4, an anisotropic etching of the reserved layer 300 exposed at the first opening 723 is performed to expose the substrate 900. Each of the reserved layers 300 remaining on the substrate 900 will define the position of the contact silicon trench in this step, so that it is no longer necessary to use a yellow light process to determine the lower trench of the conductive pillar in a subsequent process. Location, you can avoid the traditional multi-channel yellow The optical process produces a problem of alignment offset, and the creation thus more accurately grasps the position of the lower trench of the conductive post.

5, 6A, and 6B illustrate how spacers are formed on the sides of the reserved layer 300 and the mask block 729. As shown in FIG. 5, after each layer is completely covered with an insulating layer, an anisotropic etching is performed, and the insulating layer and the second insulating layer 306 are made of the same material, and the insulating layer attached to the sidewall of the third insulating layer 309 is in progress. The non-isotropic etching will be removed, and the remaining insulating layer will constitute a first spacer spacer 606 and cover only the side of the reserved layer 300, the first insulating layer 303 and the second insulating layer 306. Wall. When the position of the first spacer 606 is controlled to cover only the same height as the second insulating layer 306, but not covered by the sidewall of the third insulating layer 309, the subsequent process can be avoided after the third insulating layer 309 is removed. A problem of residual insulating layer (nitride) is generated on the surface of the second insulating layer 306 to affect product quality. The main function of the first spacer 606 is to protect the reserved layer 300 and the first insulating layer 303 from being oxidized in a subsequent process.

As shown in FIG. 6A, an oxide layer 609' is deposited first in each region, and then anisotropic etching in the vertical direction is performed as shown in FIG. 6B, and the substrate 900 is etched down to expose the oxide layer 609'. A second spacer 609 is formed, wherein the oxide layer 609' is a deposited layer having a high step coverage, and can be equally thick or equidistantly covered on the surface of the region. As shown in FIG. 6B, the second spacer 609 is formed on the sidewalls of the third insulating layer 309 and the first spacer 606, so that the first spacer 606 and the second spacer 609 are formed together. A partition wall, the width of each partition wall is the sum of the widths of the first gap wall 606 and the second gap wall 609. A space 753 is exposed between the two adjacent second spacers 609 on the surface of the substrate 900. The width of the spacer 753 is the width of the gate trench. In other words, the width of the required gate trench can be first. The width of the opening 723 and the thickness of the second spacer 609 together determine that the gate trench width of 0.18 μm or less can be accurately achieved without the use of a high-end yellow process and a DUV mask. Moreover, if there is a deviation in the current end process, the thickness of the deposition of the second spacer 609 can be appropriately corrected to obtain the desired gate trench width.

As shown in FIG. 7, the substrate 900 is dry etched down at a space 753 to form a gate trench 910 having a circular arc bottom. Then, the second spacer 609 is further wet etched to expose the corner 610 of the upper edge of the gate trench 910. The purpose of exposing the corner 610 is to trim the edge of the arc in a subsequent process to avoid stress or discharge problems caused by the sharp corner shape.

As shown in FIG. 8, an oxide layer is grown on the surface of each region, and then the oxide layer is removed, and the third insulating layer 309 and the second spacer 609 of the same material are removed, and the gate is removed. Surface defects inside the pole trench 910. After removing the sacrificial oxide layer, a gate oxide 603 is grown on the surface of the gate trench 910 and the surface of the exposed substrate 900 by thermal oxidation or deposition. Wherein, the first spacer 606 protects the reserved layer 300 from oxidation during the process of fabricating the sacrificial oxide layer or the gate oxide layer, and prevents the width of the reserved layer 300 from changing. Since the position of the first spacer 606 is only covered at the same height as the second insulating layer 306, after the third insulating layer 309 is removed, no problem of residue is generated on the surface of the second insulating layer 306.

As shown in FIG. 9, the surface of the gate trench 910 and the surface of the gate oxide layer 603 are initially covered with a conductive layer 600. The conductive layer 600 is a polysilicon layer, and the height of the initially covered conductive layer 600 is slightly higher than that. The top surface of the second insulating layer 306. The conductive layer 600 is then etched using a resist-assisted etch back until the top surface of the conductive layer 600 is equal to the top surface of the second insulating layer 306. In another embodiment, the conductive layer 600 may also be removed by chemical mechanical polishing (CMP) to be at the same height as the second insulating layer 306. In this way, a flat surface is obtained to facilitate subsequent processes.

As shown in FIG. 10, a plurality of gate row openings 726 and a planting region opening 756 are etched on the conductive layer 600 by using a second mask to simultaneously define a gate bus region and a source cloth. Source implanted region, wherein the gate row opening 726 on the left side of the drawing is unetched Between the conductive layer 600 and the reserved layer 300, the opening width is small, and the implanting area opening 756 is between the adjacent reserved layers 300, and the opening width thereof is large. The first spacer 606 is then removed, and the exposed substrate 900 is subjected to substrate implantation and thermal annealing to form a substrate region 903. In this embodiment, the source region 903 may be source implanted in an oblique ion implantation manner to form the source region 906; on the other hand, in the gate busbar region because of the width of the gate row opening 726 The small, obliquely ejected ions (as indicated by the dashed arrows) are blocked by the conductive layer 600 and the reserved layer 300, and ions will not enter the base region 903.

As shown in FIG. 11, in another embodiment in which the source region 906 is formed, an oxide layer 319 may be completely covered first. Since the width of the gate row opening 726 is small, the gate row opening 726 is filled first. The oxide layer 319, while the implant region opening 756, due to its large width, only covers an oxide layer 319 of equal thickness. After the oxide layer 319 is isotropically etched, only the oxide layer in the implant region opening 756 is removed, but the oxide layer 319 of the gate row opening 726 is only partially removed from the surface, and remains substantially in the gate row opening. 726 is used as an implant mask. In this embodiment, the source region 903 of the implanted region opening 756 may be source implanted by a vertically downward ion implantation method (as indicated by a dashed arrow) to form a source region 906; Because the gate row opening 726 has an oxide layer 319 as an implant mask, the implant ions are blocked and will not enter the substrate region 903.

As shown in FIG. 12, the second insulating layer 306 is first removed, and then another insulating layer 619 is filled in all the openings, and the top surface of the insulating layer 619 is also subjected to a resist-assisted etch back. Or chemical mechanical polishing (CMP) to obtain an insulating layer 619 having a flat surface. Then, the insulating layer 619 is etched by using a third mask, and the insulating layer 619 is removed over the corresponding reserved layer 300 to form a conductive pillar upper trench 310. The unremoved insulating layer 619 is used as an internal dielectric layer. . The opening width of the upper pillar 310 of the conductive pillar is larger than the width of the reserved layer 300 to expose the reserved layer 300 and ensure that the subsequent layer 300 can completely remove the reserved layer 300. Since the material of the reserved layer 300 is different from the insulating layer 619 and its position is already defined, the alignment offset is not generated when the third mask etching operation is performed.

As shown in FIG. 13, after the conductive pillar upper trench 310 is formed, the reserved layer 300 is completely etched and continues to etch down into the base region 903 of the substrate 900. The location of the original reserved layer 300 is etched to form a self-aligned docking region 313, and the substrate region 903 is etched to form a conductive pillar lower trench 316 that communicates with the self-aligned docking region 313. A contact region 909 of a different conductivity type is formed in the interior of the substrate 900 below the trench 316 of the lower portion of the conductive pillar. Here, a P+ material implant is taken as an example, and the contact region 909 is used to reduce Contact resistance of metal and substrate 900 when two heterogeneous materials are mated.

As shown in FIG. 14, the conductive pillar upper trench 310, the self-aligned butted region 313, and the conductive pillar lower trench 316 are connected to form a conductive contact trench, and a conductive material (such as tungsten) is deposited therein. After the etchback is performed, a conductive pillar 913 is formed, the height of the conductive pillar 913 is equal to the height of the insulating layer 619, and finally a surface metal is deposited on the top surface of the conductive pillar 913 and the insulating layer 619 by deposition. Layer 916 electrically connects the conductive post 913, which is used as a source contact in FIG. The conductive pillars 913 and the surface metal layer 916 may be the same or different in material. In the example shown in FIG. 14, the surface metal layer 916 is electrically connected to the active region of the component, that is, electrically connected to the source region 906, the substrate region 903, and the contact region 909 through the conductive pillars. The gate spacing (mesas) between adjacent gate trenches is denoted by M, which may be less than 0.8 microns below the sub-micrometer level.

If it is in the gate busbar region, other conductive pillars corresponding to the conductive layer 600 are formed, and the corresponding surface metal layer 916 is electrically connected through the other conductive pillars, and the corresponding surface metal layer 916 is used as a gate. point.

According to the structure shown in FIG. 14, if the bottom surface of the substrate 900 is surface-polished and the back metal layer is formed to form a drain, the fabrication of the MOSFET can be completed. This part is not a feature of the present invention and will not be described again.

Similarly, as shown in FIG. 15, if the bottom surface of the substrate 900 is first surface-polished and P-doped 919, and finally the back metal layer is deposited to form a collector, the fabrication of the IGBT can be completed.

Claims (11)

A trench type power transistor method, a. preparing a substrate to form a reserved layer on a top surface of the substrate; b. forming a hard mask layer on a top surface of the reserved layer; c. The hard mask layer defines and forms a plurality of first openings, the hard mask layer being divided into the plurality of mask blocks by the first openings; d. etching to remove the reserved layer not covered by the plurality of mask blocks; e. forming a partition wall on each side of the mask block, the partition walls having the same width and a spacing between adjacent partition walls; f. forming a gate at each of the intervals a trench, each of the gate trenches extending downward from a top surface of the substrate, and a spacing between adjacent two gate trenches is less than 1 micrometer; g. filling the interior of the gate trench and each of the first openings Entering a conductive layer; h. defining a gate busbar region and a source implant region in the conductive layer, and removing part of the conductive layer to form a plurality of gate row openings and a planting region opening, wherein the cloth The width of the opening of the planting area is greater than the width of the opening of the gate row; i. forming a plurality of source regions inside the substrate exposed to the opening of the cloth value region; j. comprehensively covering an insulating layer, and etching and removing part of the insulating layer to form a plurality of conductive pillar upper trenches, wherein a center position of the upper trench of each conductive pillar is aligned with a center position of the reserved layer; k. The reserved layer and the substrate underneath thereof form a plurality of lower pillars of the conductive pillars, and the lower trenches of the conductive pillars communicate with the upper trenches of the corresponding conductive pillars to form conductive pillar trenches; l. A conductive material is filled inside the trench to form a plurality of conductive pillars, and each conductive pillar is coplanar with the insulating layer. The method for manufacturing a trench power transistor according to claim 1, wherein in the step b, the method comprises: forming a first insulating layer, a second insulating layer and a second surface from the bottom to the top of the reserved layer. a third insulating layer, wherein the hard mask layer comprises the first insulating layer, the second insulating layer, and the third insulating layer. The trench power transistor manufacturing method of claim 2, wherein in the step e, the method includes: forming a first spacer on the sidewalls of the reserved layer, the first insulating layer and the second insulating layer , The first spacer and the second spacer are the same material ; and a second spacer is formed on each of the third insulating layer and the side of the first spacer, so that the first spacer and the second spacer The partition wall is formed, and the partition wall has a width that is a total width of the first partition wall and the second partition wall. The trench power transistor manufacturing method according to claim 3, in the step f, further comprising: after forming the gate trench, performing a wet etching to expose a corner of the upper edge of the gate trench Removing the second spacer and the third insulating layer; forming a gate oxide layer on the inner surface of the gate trench. In the trench power transistor manufacturing method of claim 4, in step g, the conductive layer is coplanar with the second insulating layer. The trench power transistor manufacturing method according to claim 5, in the step i, comprising: removing the first spacer; performing substrate implantation and thermal annealing on the substrate to form a base region; The substrate of the open area is subjected to oblique ion implantation to form the plurality of source regions. The trench power transistor manufacturing method according to claim 5, in the step i, comprising: removing the first spacer; performing substrate implantation and thermal annealing on the substrate to form a base region; depositing an oxide layer Opening each of the gate opening and the implanting region; performing an isotropic etching on the oxide layer to remove the oxide layer in the opening of the implanting region; and vertically implanting the substrate in the opening of the implanted region To form the plurality of source regions. The trench power transistor manufacturing method according to claim 6 or 7, wherein in step j, the width of the upper trench of each of the conductive pillars is greater than the width of the reserved layer. The trench power transistor manufacturing method of claim 8, wherein in step k, the width of the lower trench of each conductive pillar is equal to the width of the reserved layer; and the inside of the substrate below the lower trench of the conductive pillar A contact zone is formed. The trench power transistor manufacturing method according to claim 9, wherein in the step 1, the method comprises: forming a front metal layer on the surface of the conductive pillar and the insulating layer. The trench power transistor method of claim 10, wherein after step 1, further comprising: forming a doped surface on a bottom surface of the substrate.