KR101025739B1 - Method of manufacturing semiconductor device with neck free vertical gate - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device capable of cleanly removing the liner layer and the gate conductive layer of the upper side wall of the active pillar during the neck-free vertical gate process, the present invention comprises the steps of forming a linear active pillar on the substrate; Forming a buried bitline in the substrate between the active pillars; Forming a preliminary gate conductive film surrounding a sidewall of the active pillar; Forming a liner film on the entire surface of the substrate; Forming a recessed sacrificial layer on the liner layer to expose the upper side wall of the active pillar while gap filling between the active pillars; Etching a portion of the liner layer and the preliminary gate conductive layer exposed by the sacrificial layer to form vertical gates surrounding sidewalls of the active pillars; Etching a substrate between the active pillars to form a trench separating the buried bit lines; And forming an interlayer insulating film gap-filling the trench, wherein the present invention described above forms a vertical vertical gate that surrounds the active pillar of the neck-free structure before the trench and the interlayer insulating film process to separate the buried bit line, and spins. After the on insulation layer is formed, the preliminary gate conductive layer and the liner layer are etched to cleanly etch the preliminary gate conductive layer and the liner layer while exposing the upper side wall of the active pillar.

Vertical gate, neck free, buried bit line, liner film, etch back

Description

Method of manufacturing semiconductor device with neck-free vertical gate {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH NECK FREE VERTICAL GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device manufacturing method having a neck-free vertical gate.

As the design rules of semiconductor devices become smaller and smaller, there are many difficulties in manufacturing semiconductor devices of 40 nm or less. In order to overcome this problem, researches on the formation of vertical gates rather than horizontal gates have been conducted.

In a semiconductor device having a vertical gate, a substrate is processed to form an active pillar including a neck pillar and a top pillar, and then a gate insulating layer is grown to form a gate electrode. Since the gate electrode has a structure surrounding the neck wall of the active pillar, a vertical channel is formed between the upper end and the lower end of the active pillar.

When the active pillars are divided into the neck pillars and the top pillars as described above, there is a limit to the high integration due to the interval between the top pillars, and in particular, the neck pillars have a weak bearing force, causing the active pillars to collapse.

Therefore, a neck free vertical gate has been proposed that can secure the gap between the active pillars and prevent the pattern from collapsing. The neckfree vertical gate refers to a gate structure that surrounds a linear active pillar without neck pillars.

1A and 1B illustrate a method of manufacturing a semiconductor device having a neck-free vertical gate according to the related art.

As shown in FIG. 1A, the substrate 11 is etched using the hard mask layer 13 as an etch barrier to form a linear active pillar 12. Subsequently, ion implantation is performed in the substrate 11 between the active pillars 12 to form a buried bitline 14.

Subsequently, after the gate insulating film 15 is formed on the surfaces of the active pillar 12 and the substrate 11, the preliminary gate conductive layer 16 surrounding the sidewalls of the active pillar 12 is formed on the gate insulating layer 15. .

Subsequently, a liner layer 17 is formed on the entire surface including the preliminary gate conductive layer 16.

Subsequently, after forming the trenches 18 that separate the buried bit lines 14, the interlayer insulating film 19 is deposited. Subsequently, the interlayer insulating film 19 is etched back to a predetermined height of the active pillar 12 to fill the trench 18. Since the interlayer insulating film 19 is an interlayer insulating film that insulates between buried bit lines, it is referred to as 'BBL IB (Buried BitLine Inter Layer Dielectric)'.

As shown in FIG. 1B, the liner layer 17 and the preliminary gate conductive layer 16 of the upper sidewall of the active pillar exposed by the etch back of the interlayer insulating layer 19 are removed. The remaining preliminary gate conductive film becomes a round vertical gate 16A surrounding the lower sidewall of the active pillar.

However, the related art has a problem in that loss of the interlayer insulating film 19 (see reference numeral 20A) occurs when the liner film 17 is removed during the process of forming the vertical gate 16A of FIG. 1B. In addition, when the liner layer 17 is not completely removed, it is difficult to uniformly remove the gate conductive layer on the upper side wall of the active pillar 12 (see reference numeral 20B). If the gate conductive layer is not uniformly removed, the uniformity of the vertical gate may be degraded, resulting in a non-uniform channel length.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent the collapse of the active pillar while sufficiently securing the gap between the active pillars of the neck-free structure.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device capable of cleanly removing the liner film and the gate conductive film of the upper side wall of the active pillar during the vertical gate process.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a linear active pillar on the substrate; Forming a buried bitline in the substrate between the active pillars; Forming a preliminary gate conductive film surrounding a sidewall of the active pillar; Forming a liner film on the entire surface of the substrate; Forming a recessed sacrificial layer on the liner layer to expose the upper side wall of the active pillar while gap filling between the active pillars; Etching a portion of the liner layer and the preliminary gate conductive layer exposed by the sacrificial layer to form vertical gates surrounding sidewalls of the active pillars; Etching a substrate between the active pillars to form a trench separating the buried bit lines; And forming an interlayer insulating layer gap gap filling the trench, wherein forming the recessed sacrificial layer comprises: forming a spin-on insulating layer gap gap filling the active pillars on the liner layer; Planarizing the spin-on insulating film; And recessing the spin-on insulating layer through an etch back. In the forming of the vertical gate, the liner layer may be etched by wet etching, and the preliminary gate conductive layer may be etched by dry etching.

The present invention described above has the effect of forming a uniform vertical gate by forming a straight vertical gate surrounding the active pillar of the neck-free structure before the trench and the interlayer insulating film process for separating the buried bit line.

In addition, the present invention has the effect of etching the preliminary gate conductive film and the liner film after the spin-on insulating film is formed, and the preliminary gate conductive film and the liner film can be etched cleanly while exposing the upper side wall of the active pillar.

As a result, the present invention can ensure a constant channel length by forming a uniform vertical gate, thereby stably realizing a semiconductor device having a neck-free vertical gate.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

In the present invention, the vertical gate is formed before the buried bit line interlayer dielectric (BBL ILD) process in forming a straight neck free vertical gate having no distinction between the top pillar and the neck pillar. As a result, it is possible to prevent the liner film and the vertical gate from remaining unevenly in the upper side wall of the active pillar.

2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device having a neck-free vertical gate according to an exemplary embodiment of the present invention.

As shown in Fig. 2A, a hard mask film 22 is formed on a substrate 21 such as a silicon substrate. The hard mask film 22 may be formed by stacking a first hard mask film and a second hard mask film. The first hard mask film includes a nitride film, and the second hard mask film includes an oxide film. The hard mask layer 22 is a layer for use as an etching barrier in a subsequent pillar etching process. The hard mask layer 22 may be patterned in a form corresponding to the linear active pillar, which may be formed by an etching process using a photoresist pattern (not shown).

The substrate 21 is etched to a predetermined depth using the hard mask layer 22 as an etch barrier. This is abbreviated as 'pillar etching', and a plurality of active pillars 23 serving as active regions are formed by the pillar etching. In plan view, the active pillars may be arranged in a matrix form.

Pillar etching uses anisotropic etching. When the substrate 21 is a silicon substrate, anisotropic etching may be performed by using plasma dry etch using Cl ₂ or HBr gas alone, or using a mixture of these gases.

After the pillar etching, a plurality of active pillars 23 are formed on the substrate 21, and a hard mask layer 22 remains on the active pillars 23.

The present invention forms the active pillar 23 in a straight form. In other words, it is not divided into a neck pillar and a top pillar to form a straight shape does not cause collapse. As described above, the active pillar having a linear structure without neck pillar is defined as 'Neck free active pillar'.

As a result, the active pillar 23 has a straight structure on the substrate 21 and becomes a raised pillar structure. The active pillar 23 has a height of about 3000 mm 3. Since the active pillars 23 have a straight structure, they do not collapse even if the line width of the active pillars 23 becomes small. In the conventional structure consisting of the neck pillar and the top pillar, the support force of the neck pillar is weak, but a problem occurs. However, in the present invention, the active pillar 23 is not collapsed in the subsequent process because the neck pillar is a straight structure.

Next, the buried bit line 24 is formed through ion implantation of impurities in the substrate 21 between the active pillars 23.

As shown in FIG. 2B, a gate insulating film 25 covering the surfaces of the active pillars 23 and the substrate 21 is formed. The gate insulating film 25 may include a silicon oxide film.

Subsequently, a gate conductive layer is deposited on the entire surface of the substrate 21 on which the gate insulating layer 25 is formed, and then etched back to form a preliminary gate conductive layer 26 surrounding the sidewall of the active pillar 23. The preliminary gate conductive layer 26 may be a polysilicon layer doped with N-type impurities or a polysilicon layer doped with P-type impurities. In addition, a polysilicon film doped with an impurity and a metal film may be stacked. The preliminary gate conductive layer 26 is a material that becomes a vertical gate.

As shown in FIG. 2C, a thin liner layer 27 is formed on the entire surface. Here, the liner film 27 includes a nitride film. The liner film 27 is for protecting the preliminary gate conductive film 26 from subsequent etching and the like, and is formed to a thickness of 70 to 85 kPa.

Subsequently, a sacrificial film 28 is formed on the liner film 27. In this case, the sacrificial layer 28 is formed of a material capable of gapfilling the adjacent active pillars 23 without voids. Preferably, the sacrificial layer 28 uses a spin on dielectric (SOD). Depending on the height of the active pillar 23, the thickness of the spin-on insulating film is 4500 to 5000 kPa. After coating the spin-on insulating film, wet curing may be performed at a low temperature of 300 to 400 ° C.

By such wet curing, the spin-on insulating film is replaced with a silicon oxide film. For example, polysilazane (PSZ) is used as a source material when the spin-on insulating film is applied, and the polysilazane is replaced with a silicon oxide film by wet curing. Thus, the sacrificial layer 28 may be a silicon oxide layer. Meanwhile, before applying the spin-on insulating film, an oxide liner film may be further formed. If wet cure is performed at a low temperature, uniform characteristics can be obtained during the etch back process of the subsequent liner film and avigate conductive film.

Subsequently, a chemical mechanical polishing (CMP) process is used to planarize the step. Here, the step means the step between the cell area and the peripheral circuit area. Although the cell region and the peripheral circuit region are not illustrated separately, since the active pillar is formed only in the cell region, a step may be generated between the cell region and the peripheral circuit region by the height of the active pillar. Therefore, the step can be eliminated by performing a planarization process such as chemical mechanical polishing.

The reason for the planarization process as described above is to uniformly retain the preliminary gate conductive layer 26 in a subsequent process. In other words, it is necessary to uniformly etch back the sacrificial film 28.

As shown in FIG. 2D, the sacrificial layer 28 is etched back. At this time, the etch back proceeds until the upper sidewall of the active pillar 23 is opened. The etch back process of the sacrificial film 28 may use a wet etch bag or a dry etch bag, but a wet etch bag is more advantageous to cleanly remove the sacrificial film 28 from the upper sidewall of the active pillar 23. Wet etch bags may use 100: 1 HF solution.

The sacrificial film 28A remaining by the etch back process as described above opens the upper side wall of the active pillar 23.

As shown in FIG. 2E, the liner layer 27 and the preliminary gate conductive layer 26 exposed by the etch back of the sacrificial layer 28A are etched back. At this time, the liner layer 27 and the preliminary gate conductive layer 26 are etched back only to the height of the remaining sacrificial layer 28A. Therefore, the preliminary gate conductive layer 26A and the liner layer 27A remain in a form surrounding the lower sidewall of the active pillar 23. Here, the remaining preliminary gate conductive film becomes 'vertical gate 26A'.

The lower side wall of the active pillar 23 and the upper side wall of the active pillar 23 are divided for convenience of description. The portion surrounded by the vertical gate 26A is called the lower side wall, and the portion not surrounded by the vertical gate 26A is referred to as the lower side wall. Assume the upper side wall. The lower side wall may be higher than the upper side wall. On the other hand, the vertical gate 26A may be formed to surround all side walls of the active pillar 23, without being limited to the lower side wall and the upper side wall.

As described above, when the liner layer 27 and the preliminary gate conductive layer 26 are etched back after the etch back of the sacrificial layer 28A, the upper side walls of the active pillars 23 may be uniformly exposed. Vertical gates can be formed by height. As a result, the channel length formed by the vertical gate can be kept constant. The etch back of the liner layer 27 and the preliminary gate conductive layer 26 uses a selectivity ratio between the sacrificial layer 28A, and thus can be etched back without residue.

Since the liner film 27 is a nitride film, the etch back of the liner film 27 proceeds to a wet etch bag using a phosphoric acid solution.

The etch back of the preliminary gate conductive film 26 uses a dry etch back.

As shown in FIG. 2F, the sacrificial film 28A filled between the active pillars 23 is dip out. Since the sacrificial film 28A is a spin-on insulating film made of an oxide film, the dipout process is performed using a 100: 1 hydrofluoric acid (HF) solution.

As shown in FIG. 2G, a first interlayer insulating layer 30 is formed to gap gap between the active pillars 23. Here, the first interlayer insulating film 30 may use a BPSG film, and the liner film 29 may be further formed before the first interlayer insulating film 30 is formed. The liner layer 29 may include a nitride layer, and may sequentially form an oxide layer and a nitride layer. The liner film 29 is used to protect the vertical gates 26A from subsequent etching and the like, and is formed to a thickness of 70 to 85 kPa.

As shown in FIG. 2H, an etching process for separating the buried bit line 24 (hereinafter, referred to as a 'BBL etching process') is performed. The substrate 21 is etched by the etching process to form the trench 31, and the buried bit lines 24A and 24B are separated from each other by the trench 31.

When the first interlayer insulating layer 30 is etched, the liner layer 29 may be self-aligned. If the liner layer 29 is not present, the liner layer 29 may be self-aligned.

The first interlayer insulating layer 30 is etched to form the trench 31, and the liner layers and the gate insulating layer 25 on the substrate 21 are etched between the vertical gates 26A. Subsequently, the trench 21 is formed by etching the substrate 21 to a depth at which the buried bit line 24 is separated.

As shown in FIG. 2I, a second interlayer insulating film 32 is deposited on the entire surface to gap fill the trench 31. Here, the second interlayer insulating film 32 may be a BPSG film having excellent gap fill characteristics, and the second interlayer insulating film 32 may serve as an interlayer insulating film between adjacent buried bit lines 24A and 24B. Therefore, the second interlayer insulating film 32 becomes a buried bit line interlayer insulating film BBL ILD.

As described above, the present invention forms a buried bit line interlayer smoke film after forming the vertical gate 26A.

Although not shown, the damascene word line process is subsequently performed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B illustrate a method of manufacturing a semiconductor device having a neck-free vertical gate according to the prior art.

2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device having a neck-free vertical gate according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 hard mask film

23: active pillar 24: buried bit line

25 gate insulating film 26A vertical gate

27A: liner film 28A: sacrificial film

30: first interlayer insulating film 31: trench

32: second interlayer insulating film

Claims (15)

Forming a straight active pillar on the substrate; Forming a buried bitline in the substrate between the active pillars; Forming a preliminary gate conductive film surrounding a sidewall of the active pillar; Forming a liner film on the entire surface of the substrate; Forming a recessed sacrificial layer on the liner layer to expose the upper side wall of the active pillar while gap filling between the active pillars; Etching a portion of the liner layer and the preliminary gate conductive layer exposed by the sacrificial layer to form vertical gates surrounding sidewalls of the active pillars; Etching a substrate between the active pillars to form a trench separating the buried bit lines; And Forming an interlayer insulating film gap-filling the trench A semiconductor device manufacturing method comprising a. The method of claim 1, And removing the sacrificial layer through a deep out before forming the trench. The method of claim 1, Forming the recessed sacrificial layer, Forming a spin-on insulating layer on the liner layer to gap-fill the active pillars; Planarizing the spin-on insulating film; And Recessing the spin-on insulating layer through an etch back A semiconductor device manufacturing method comprising a. The method of claim 3, Forming the spin-on insulating film, Applying a spin-on insulating film (SOD); And Curing the spin-on insulating film A semiconductor device manufacturing method comprising a. The method of claim 4, wherein The curing method is a semiconductor device manufacturing method that proceeds to wet curing. The method of claim 5, The wet cure is a semiconductor device manufacturing method that proceeds at 300 ~ 400 ℃. The method of claim 3, The etch back may be a wet etch back or a dry etch back. The method of claim 7, wherein The wet etch bag is a semiconductor device manufacturing method using a hydrofluoric acid solution. The method according to any one of claims 1 to 8, In the forming of the vertical gate, And the preliminary gate conductive layer is etched by wet etching, and the preliminary gate conductive layer is etched by dry etching. 10. The method of claim 9, The preliminary gate conductive film is formed by forming a polysilicon film alone or by stacking a polysilicon film and a metal film. 10. The method of claim 9, And the liner film comprises a nitride film. The method of claim 2, And removing the sacrificial layer through a dip out using a hydrofluoric acid solution. The method of claim 1, And further forming a liner film before forming the interlayer insulating film. The method of claim 13, And the liner film is formed by forming a nitride film alone or by stacking an oxide film and a nitride film. The method of claim 1, The interlayer insulating film includes a BPSG (Boro Phosphorous Silicate Glass) film.

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