DE19507146A1 - Semiconductor device used as FET - Google Patents

Abstract

A semiconductor device (I) comprises: (a) a semiconductor substrate (1); (b) a trench (31) in the substrate (1); (c) a gate insulating layer (32) covering the inner wall of the trench (31); (d) a gate electrode (34) which fills the trench (31) and projects above the surface of the substrate (1), where the width of the section of gate electrode (34) is the same or less than the width of the projecting gate electrode filling the trench (31); and (e) an insulating layer (32) formed in such a way that it covers only the projecting section of the gate electrode (34). Prodn. of the semiconductor device is also claimed.

Description

The present invention relates to a semiconductor direction and a process for their manufacture. More precisely be she draws on an improvement in a performance field fect transistor that can conduct a large current. The present The present invention also relates to a method of manufacturing position of such a semiconductor device.

Fig. 60 is a sectional view of a first Feldeffekttransi stors the vertical type with a grave structure (hereinafter referred to as "trench MOS" hereinafter), which is disclosed in US 4,767,722.

As shown in FIG. 60, a semiconductor device has an n⁺-type single crystal silicon substrate 110 . An n⁻-type single-crystal silicon epitaxial layer 111 is formed on the n⁺-type single-crystal silicon substrate 110 . A trench 131 is formed in the n⁻-type single crystal silicon epitaxial layer 111 . A silicon oxide layer 132 , which is a gate insulating layer, covers the inner wall of the trench 131 . The trench 131 is filled with polycrystalline silicon 134 , which has an n-type dopant, which becomes the gate electrode. p-type base diffusion layers 120 a and 120 b are provided on both sides of the trench 131 on the n⁻-type single crystal silicon epitaxial layer 111 . An n-type source diffusion layer 121 a is provided in the p-type base diffusion layer 120 a. An n-type source diffusion layer 121 b is provided in the p-type base diffusion layer 120 b. A gate electrode 134 is covered with an insulating layer 135 . A source electrode 118 is connected to the n-type source diffusion layer 121 a. A source electrode 119 is connected to the n-type source diffusion layer 121 b. A drain electrode 117 is connected to the bottom surface of the n⁺-type single crystal silicon substrate 110 .

The operation of the semiconductor device will be described below. By applying a positive potential to the gate electrode 134 , channels are formed on the sides of the trench 131 . The arrows 122 C1 and 122 C2 show the way. Electrons migrate and cause a current to flow between the source electrodes 118 and 119 and the drain electrode 117 .

The trench MOS described above is a so-called power MOS. It can conduct a large current and is used e.g. B. to the scarf motor.

A method of manufacturing the trench MOS described above is described below.

As shown in FIG. 61, an n⁻-type single crystal silicon epitaxial layer 111 is formed everywhere but a main surface of the n⁺-type single crystal silicon substrate 110 by epitaxial growth. Then, photolithography, ion implantation, and dopant diffusion steps are repeated to form the p-type base diffusion layer 120 and the n-type source diffusion layer 121 , respectively. This structure is referred to in the following as silicon substrate 100 . A silicon oxide layer 130 is formed on the surface of the silicon substrate 100 .

As shown in FIG. 62, the silicon oxide layer 130 is patterned into a predetermined configuration so that it can serve as a mask for subsequently forming a trench. Using the silicon oxide layer 130 as a mask, the silicon is etched to form a trench 131 in the silicon substrate 100 through the n-type source diffusion layer 121 and the p-type base diffusion layer 120 into the n⁻-type single crystal silicon epitaxial layer 111 .

As shown in FIGS. 62 and 63, a silicon oxide layer 132 , which becomes a gate oxide layer, is formed on the inner wall of the trench 131 .

As shown in Fig. 64, a polycrystalline silicon layer 133 containing n-type dopant is formed on the silicon substrate 100 by CVD so that the trench 131 is filled. As shown in FIGS. 64 and 65, the n-type poly crystalline silicon layer 133 is etched back until the upper surface thereof is arranged between the surface of the silicon substrate 100 and the bottom surface of the n-type source diffusion layers 121 a and 121 b. The upper surface 134 a of the n-type polycrystalline silicon is arranged 0.25-0.5 μm below the surface of the silicon substrate 100 . A polycrystalline line n-type gate silicon layer 134 is formed in this way.

As shown in Fig. 66, the surface is the polykristal linen n-type silicon layer 134 is oxidized to form a silicon oxide layer 135 on the polycrystalline n-type silicon layer 134. The silicon oxide layer 135 is formed thicker than the oxide layer 130 that is provided on the surface of the silicon substrate 100 . The oxide layer 130 , which is formed on the surface of the silicon oxide layer 135 and the silicon substrate 100 , is substantially flat. It is necessary that the upper surface 134 a of the gate electrode 134 is arranged below the surface of the silicon substrate 100 and above the bottom surface of the n-type source diffusion layers 121 a and 122 b.

As shown in FIGS. 66 and 67, is attached to the Oberflä of the silicon substrate surface 100 formed silicon oxide layer 130 by etching to form source electrodes 118 and 119 on the silicon substrate, the diffusion regions so in contact with the p-type base 120 a and 120 b and the n-type source diffusion layers 121 a and 121 b come away. The drain electrode 117 is formed on the bottom surface of the n⁺-type single crystal silicon substrate 110 .

Fig. 68 is a sectional view of a second trench MOS, which is disclosed in US 4,767,722. Elements in FIG. 68 corresponding to those of the semiconductor device of FIG. 67 are given the same reference numerals and their description is not repeated.

As shown in FIG. 68, a trench 123 , a silicon oxide layer 124 , which becomes a gate insulating layer, and polycrystalline n-type silicon 125 of a gate electrode are provided. The semiconductor device from FIG. 68 differs from the semiconductor device from FIG. 67 in that the cut of the polycrystalline n-type gate silicon 125 has a U-shape, the trench 123 is not completely filled, and in that the polycrystalline n-type silicon layer 125 upwards over the surface of the silicon substrate 100 and also protrudes sideways away from the trench opening.

Fig. 68 is a sectional view of a third trench MOS described in IEDM86, pages 638-641. The elements of the semiconductor device shown in FIG. 69, which are identical to those of the semiconductor device shown in FIG. 67, are denoted by the same reference numerals, and the description thereof is not repeated. As shown in FIG. 69, an interlayer insulating layer 136 is provided for electrically isolating the gate electrode 134 from the source electrode 118 . The semiconductor device of FIG. 69 differs from the semiconductor device of FIG. 60 in that the polycrystalline line n-type gate silicon 134 protrudes upward from the surface of the silicon substrate 100 and also laterally from the trench opening.

A method of manufacturing the trench MOS shown in Figs. 68 and 69 will be described below.

First, process sequences comparable to those from FIGS. 61 to 64 for forming a trench, a gate oxide layer and a polycrystalline n-type silicon layer are carried out. Then, the polycrystalline n-type silicon layer is patterned by photolithography to form a U-shaped or a T-shaped gate electrode that protrudes horizontally above the trench opening. Then, the interlayer insulating layer 136 is formed, followed by lithography to pattern the interlayer insulating layer 136 , which results in the formation of a contact area. Ultimately, a source electrode and a drain electrode are formed. The trench MOS is thus completed.

Fig. 70 is a sectional view of a semiconductor device disclosed in Japanese Patent Laid-Open No. 4-17371. A p-type diffusion region 2 a, which becomes a drain, is formed in an n-type silicon substrate 1 a. An n-type diffusion region 3 a of high concentration, which becomes a source, is formed in the p-type diffusion region 2 a. A trench 4 a is formed such that it penetrates the n-type diffusion region 3 a and the p-type diffusion region 2 a. A gate oxide layer 5 a is formed on the side wall of the trench 4 a. A gate electrode 6 is buried in the trench 4 a with the gate oxide layer 5 a in between. An interlayer insulating layer 7 is provided on the silicon substrate 1 a so that it covers the upper surface of the gate electrode 6 . A source electrode 8 a is provided on the silicon substrate 1 a so that it is in contact with the p-type diffusion region 2 a and the n-type diffusion region 3 a of high concentration. A Drainelek electrode 9 a is seen on the bottom side of the silicon substrate 1 a.

A trench MOS with the one described above or with one of the The structures described above have the following problems.  

First, there is the problem of making the trench shown in Fig. 60. More specifically, it is necessary, a po lykristallinen n-type silicon layer 134 to perform a precise control of the positioning of the upper surface 134, as shown in Fig. 65. This critical control requires expensive, high level manufacturing devices and techniques.

Since the polycrystalline n-type silicon layer 134 for forming the silicon oxide layer 135, as shown in Fig. 66, are coded oxi, there is the second problem that layer, the position of the upper surface 134 a of the polycrystalline n-type gate silicon 134 exactly and must be determined with a margin, taking into account the amount of polycrystalline silicon consumed or converted by the oxidation, taking into account the layer thickness and the formation conditions for the silicon oxide layer 135 .

Since the position of the upper surface 134 a of the polycrystalline n-type gate silicon layer 134, a gate electrode and is, above the bottom surface of the n-type source diffusion layers 121 a and 121 b must be such that the device as a MOS works must Depths of the n-type source diffusion layers 121 a and 121 b can be determined accordingly. Therefore, there is the third problem that reduction (sizes) in the vertical direction (flattening the semiconductor device) becomes difficult. Since the p-type base diffusion layer and also the depth of the trench cannot be made shallower, the static capacitance between the gate electrode and the silicon substrate cannot be reduced.

There is also the fourth problem that the resistance of the gate electrode in the trench MOS of Fig. 68 is increased. The first through third problems described above do not occur with the trench MOS of FIG. 68.

There is also the fifth problem that reducing (the size) of a chip becomes difficult since the n-type polycrystalline silicon layer 125 protrudes beyond the trench opening. More specifically, the corresponding formation of the trench, the gate electrode and the contact area is carried out by photolithography using individual masks in the manufacturing process. Therefore, it is necessary to provide a margin for the alignment of the mask and a margin for the manufacturing process (a margin for the etching or the like) between the trench and the gate electrode and between the gate electrode and the contact area. This becomes a "bottleneck" in reducing the size of the chip.

The fifth problem described above occurs in the trench MOS of Fig. 69. The first through fourth problems do not occur with the trench MOS of Fig. 69.

In the trench MOS of Fig. 70, there is the problem that the formation of an edge or from the edge portion of the interlayer insulating film 7 a projecting laterally or spreads, prevents an increase in the integration density.

It is an object of the present invention to provide an improved half Conductor device without expensive manufacturing device high level technologies and techniques, and specify a process for their manufacture.

This object is achieved by a semiconductor device according to Claim 1 or 8 and a method according to Claim 13 or 14 or 15.

Developments of the invention are in the dependent claims ben.

The invention enables a trench MOS, which is the reduction the dimensions in the vertical direction, she facilitated possible further a trench MOS, which is so improved that the The resistance of the gate electrode is not increased, it enables also a trench MOS, which is a reduction in size  of the chip, and it also enables a process to manufacture such trench MOS.

A semiconductor device according to an embodiment of the invention has a semiconductor substrate with a top surface and a floor surface. A ditch is on provided the surface of the semiconductor substrate. A gate insulating layer covers the inner wall (i.e. the side walls and the bottom) of the trench. A gate electrode is in the trench dig. The gate electrode is above the surface of the semi-lead substrates. The width of the protruding section of the Gate electrode is less than or equal to the width of the one in the gra ben buried gate electrode section. The semiconductor device tion further has an insulating layer which is formed in this way det is that they only the protruding portion of the gate elek tode covered. The semiconductor device works with the screen or the part of the semiconductor substrate that is the is adjacent to the trench as a channel.

A semiconductor device according to another embodiment Form of the present invention has a semiconductor sub strat with a top surface and a bottom surface. A trench is in the top surface of the semiconductor substrate intended. A gate insulation layer covers the inner wall of the Trench. A gate electrode is buried in the trench. The Ga Teelectrode jumps towards the surface of the semiconductor sub strates before. The projecting section of the Gate electrode is re in its width in the upward direction induced. The semiconductor device further has an insulation layer that covers the surface area of the semiconductor substrate not, but only the protruding section of the gate elek tode covered. The semiconductor device operates the side of the Digging as a channel.

In a method of manufacturing a semiconductor device according to another embodiment of the present invention is first a semiconductor substrate such. B. a silicon sub prepared. A silicon oxide layer, a silicon ni  tride layer, and then a silicon oxide layer are successively which is formed on the surface of the silicon substrate where by a three-layer structure, which is referred to below as three layered film is called, is produced. This three layered film is patterned. Using the patterned three-layer film as a mask will dig a trench in the top Surface of the silicon substrate is formed. A silicon oxide layer, which will later become a gate oxide layer, in the Trench formed while the three-layer film is still remains on the substrate. Then polycrystalline silicon in the trench and on the surface of the silicon substrate or deposited on the surface of the three-layer film. The polycrystalline silicon is etched back until the upper one Surface of the polycrystalline silicon (in the opening of the three layer film) over the top surface of the Silicon substrate and deeper than the surface of the top Silicon oxide layer of the three-layer film is located. The top silicon oxide layer of the three-layer film is returned etches so that the top portion of the polycrystalline silicon protrudes from the surface of the silicon substrate. The protruding polycrystalline silicon is used to form a Silicon oxide layer that is thicker than the lower silicon oxide layer of the three-layer film is oxidized so that it encloses the upper portion of the polycrystalline silicon. The silicon nitride layer is made by etching without using a Mask removed. All layers of silicon oxide on the surface of the Silicon substrates are removed so that the silicon oxide layer covering the upper section of the protruding polykri stallinen silicon layer covered, what remains in the training of a contact area results. Then a ge desired electrode.

In a method of forming a semiconductor device according to yet another embodiment of the present Invention is first prepared a silicon substrate. On the Silicon substrate become a silicon oxide layer, a silicon nitride layer and then a silicon oxide layer in succession trained, which creates a three-layer film. Of the  three-layer film is patterned so that it follows in a Forming a trench can serve as a mask, wherein an opening with a predetermined configuration in the three layered film is formed. Using the gemu The three-layer film as a mask becomes a trench in the Semiconductor substrate formed. The side wall of the opening of the top silicon oxide layer of the three-layer film is ge etches so that the width of the opening is larger than the width of the Opening of the trench will. A silicon oxide layer that later a gate oxide layer is formed in the trench, wherein the three-layer film remains. Then it becomes polycrystalline Silicon in the trench and over the surface of the silicon sub strates deposited. The polycrystalline silicon is returned etches until its top surface is above the surface of the Silicon substrate is and deeper than the surface of the top Silicon oxide layer of the three-layer film is arranged. The top silicon oxide layer of the three-layer film becomes Exposing the top portion of the polycrystalline silicon etched away so that the top portion of the polycrystalline Silicon opposite the surface of the silicon substrate and also laterally opposite the opening of the trench (i.e. from the edge of the opening of the trench). The upper ab cut the polycrystalline silicon, the side opposite protruding the opening of the trench is oxidized, whereby the upper section of the polycrystalline silicon no longer Lich opposite the opening of the trench and then only after protrudes above the surface of the silicon substrate. A silicon oxide layer thicker than the bottom silicon oxide layer of the three-layer film is for connection the upper portion of the polycrystalline silicon det. The silicon nitride layer is made by etching without using a mask removed. The silicon oxide layer on the surface of the silicon substrate is completely removed, the Si silicon oxide layer covering the upper portion of the protruding polycrystalline silicon, still remains, whereby a contact area is formed. A desired one Electrode is formed.  

In a method of manufacturing a semiconductor device according to yet another embodiment of the present Invention is first prepared a silicon substrate. A Si Silicon oxide layer is formed on the silicon substrate. The Silicon oxide layer is patterned so that it can be used as a mask can serve the subsequent formation of a trench, wherein an opening with a predetermined configuration in the sili Ziumoxidschicht is formed. Using the pattern The silicon oxide layer as a mask becomes a trench in the half conductor substrate formed. The side wall of the opening in the Silicon oxide layer is etched so that the width of the opening voltage is greater than the width of the opening in the trench. With the still remaining silicon oxide layer becomes a sili ziumoxidschicht, which becomes a gate oxide layer, in the trench educated. Then polycrystalline silicon is in the trench and deposited over the surface of the silicon substrate. The polycrystalline silicon is etched back in such a way that the upper one Surface of the same over the surface of the silicon substrate and deeper than the surface of the silicon oxide layer that is on the semiconductor substrate is formed, is arranged. The Si Silicon oxide layer on the surface of the silicon substrate etched, causing the top portion of the polycrystalline silicon so that it is exposed in such a way that it is upwards opposite the waiter surface of the silicon substrate and also on the side opposite protrudes from the opening of the trench. The upper section of the poly crystalline silicon, which is laterally opposite the opening of the Trench protrudes, is oxidized, causing the polycrystalline Silicon is formed with a configuration that is not laterally opposite the opening of the trench but only upwards protrudes from the surface of the silicon substrate. Except which will have a silicon oxide layer covering the top portion of the including polycrystalline silicon. A con tact area is trained, followed by training a desired electrode.

According to the semiconductor device according to one embodiment form of the present invention covers the insulating layer, that covers the protruding portion of the gate electrode, only  the protruding portion of the gate electrode and not the Surface area of the semiconductor substrate. Therefore extends the insulating layer is not in the horizontal direction.

According to the semiconductor device after the other embodiment Form of the present invention is the width of the front jumping portion of the gate electrode as a function of Height narrower. That is why the step cover is the first elec trode improved.

According to the method of manufacturing a semiconductor direction according to an embodiment of the present invention the silicon nitride layer is etched without using a Mask removed. Therefore no mask alignment is required, so that the manufacturing step is simplified.

According to the method of manufacturing a semiconductor direction according to a further embodiment of the invention the silicon oxide layer on the surface of the silicon substrate etched without using a mask, creating the top section of the polycrystalline silicon against the surface of the Si protrudes upwards. That is why there is no mask alignment needed, which in a simplification of manufacture procedure results.

According to the method of manufacturing a semiconductor direction according to yet another embodiment of the inven The silicon nitride layer is formed by etching without use a mask removed. Therefore no mask alignment is required Tigt, so that the manufacturing process is simplified.

Further features and advantages of the invention result from the description of exemplary embodiments with reference to the Characters. From the figures show:

Fig. 1 is a sectional view of a MOS transistor with a grave structure according to an embodiment;

Fig. 2 is a perspective view of a trench accordingly embodiments of the present invention;

Fig. 3 is a plan view of a trench formed according to imple mentation forms of the present invention

Fig. 4 is a plan view of a trench accordingly other embodiments of the vorlie invention;

Figure 5 tung to 12 sectional views of a Halbleitervorrich that the first through the eighth step ei nes manufacturing process accordingly show the same embodiment 1; Fig.

FIG. 13 is a sectional view of a MOS transistor having a structure corresponding to from grave guide die 2;

FIG. 14 is a sectional view of a MOS transistor with a grave structure corresponding guide die 3;

Fig. Tung 15 to 23 sectional views of a Halbleitervorrich showing the first to ninth steps of a method of manufacturing the same according to Embodiment 4;

Figure 24 to 34 are sectional views of a tung Halbleitervorrich showing the first to eleventh step ei nes method of manufacturing the same according to Embodiment 5; FIG.

Figure 35 to 41 are sectional views of a tung Halbleitervorrich showing the first to seventh step ei nes method of manufacturing the same according to Embodiment 6; FIG.

Figure 42 is a sectional view of another MOS-Tran sistors vertical type having a trench structure, which is prepared according to the method of Embodiment 6; FIG.

FIG. 43 is a sectional view of a further MOS-Tran sistors vertical type having a trench structure is prepared according to the method of Embodiment 6;

Figure 44 to 47 are sectional views of a tung Halbleitervorrich which accordingly show the first to fourth steps ei nes manufacturing method of the same embodiment. 7;

48 is a sectional view of another MOS-Tran sistors vertical type having a trench structure, which is prepared according to the method of Embodiment 7; FIG.

Figure 49 to 52 are sectional views of another MOS-Transistor stors the vertical type having a trench structure is prepared according to the method of Embodiment 7; FIG.

Figure 53 to 55 are sectional views of a tung Halbleitervorrich that the first to third step ei nes manufacturing process accordingly show the same embodiment. 8;

Figure 56 to 59 are sectional views of a tung Halbleitervorrich the same to the first to fourth step ei nes manufacturing process accordingly show Embodiment 9; Fig.

Fig. Is a sectional view of a first MOS-Transistor stors the vertical type having a trench structure 60;

Fig. 61 to 67 are sectional views of the first Halbleitervor direction in the first to seventh steps in a method of manufacturing the same according to a manufacturing process;

FIG. 68 is a sectional view of a tervorrichtung other semiconducting; and

Fig. 69 and 70 are sectional views of other MOS transistors of the vertical type with a grave structure.

In the following, embodiments of the invention are referenced take described on the figures.

Embodiment 1

Fig. 1 is a sectional view of a trench MOS according to Embodiment 1.

As shown in FIG. 1, an n⁻-type single crystal silicon epitaxial layer 11 is formed on an n⁺-type single crystal silicon substrate 10 . A p-type base diffusion layer 20 is formed on the n⁻-type single crystal silicon epitaxial layer 11 . An n-type source diffusion layer 21 is formed in or on the surface of the p-type base diffusion layer 20 . These layers are referred to below as a silicon substrate 1 . In the silicon substrate 1 , a trench 31 is sufficiently formed through the n-type source diffusion layer 21 and the p-type base diffusion layer 20 into the na-type single-crystal silicon epitaxial layer 11 . A gate insulating layer 32 covers the inner wall of the trench 31 . A gate electrode 34 formed of polycrystalline silicon containing n-type dopant is buried in the trench 31 . The gate electrode 34 protrudes upward over the surface of the silicon substrate 1 . An insulating layer 35 covers only the protruding portion of the gate electrode 34 . The surface area of the silicon substrate 1 is not covered with the insulating layer 35 . A source electrode 41 is formed on the silicon substrate 1 , covering the gate electrode 34 , and in contact with the n-type source diffusion layer 21 and the p-type base diffusion region 20 . A drain electrode 42 is provided on the bottom surface of the silicon substrate 1 .

The operation of the semiconductor device will be described below. By applying a positive potential to the gate electrode 34 , a channel is formed on the sides of the trench 31 . Electrons travel in the path indicated by the arrows. A current flows between the source electrode 41 and the drain electrode 42 .

According to the present embodiment, the insulating layer 35 covers only the protruding portion of the gate electrode 34 and does not cover the surface area of the silicon substrate 1 . Therefore, the insulating layer 35 does not spread in the horizontal direction, so that the occupied area can be reduced. This enables the size of the chip to be reduced.

FIG. 2 is a perspective view showing the trench portion of the trench MOS of FIG. 1. Fig. 4 is a plan view. It can be seen that the trench 31 is formed in a strip shape.

Fig. 3 is a plan view showing another construction of a Gra bens, which can be used in the embodiments of the present invention. As shown in FIG. 4, the trench can be formed in a polygon.

A method of manufacturing a trench MOS according to Aus management form 1 is described below.  

As shown in FIG. 5, the n⁻-type single crystal silicon epitaxial layer 11 is formed on the n⁺-type single crystal silicon substrate 10 . The p-type base diffusion region 20 is formed on the n⁻-type single crystal silicon epitaxial layer 11 . The n-type source diffusion region 21 is formed in the surface of the p-type base diffusion region 20 . In the following, the n⁺-type single crystal silicon substrate 10 , the n⁻-type single crystal silicon epitaxial layer 11 , the p-type base diffusion layer 20 and the n-type source diffusion layer 21 are collectively referred to as silicon substrate 1 . On the surface of the silicon substrate 1 , a silicon oxide layer 37 with a layer thickness of 30 nm (300 Å) z. B. formed by thermal oxidation. A silicon nitride layer 38 with a layer thickness of 100 nm (1000 Å) on the silicon oxide layer 37 z. B. excreted by CVD. Then a silicon oxide layer 30 with a layer thickness of 800 nm (8000 Å) on the silicon nitride layer 38 z. B. deposited by CVD. The silicon oxide layer 30 serves as a mask in a subsequent etching step to form a trench. The layer thickness is selected for the purpose of this etching.

As shown in FIG. 6, the silicon oxide layer 30 , the silicon nitride layer 38 and the silicon oxide layer 37 are patterned into a predetermined shape so that they can serve as a mask for the subsequent trench formation. Using the patterned silicon oxide layer 30 as a mask, a trench 31 is formed in the silicon substrate 1 , which reaches the n⁻-type single crystal silicon epitaxial layer 11 through the n-type source diffusion layer 21 and the p-type base diffusion layer 20 .

As shown in FIG. 7, a silicon oxide layer 32 with a layer thickness of 50 nm (500 Å) that becomes a gate oxide layer covering the inner wall of the trench 31 is formed. Then a polycrystalline silicon layer 33, the n-type doping material is comprises, deposited on the silicon substrate 1, that it fills the trench 31st The layer thickness of the gate oxide layer 32 can be varied in accordance with the required or desired electrical properties.

As shown in FIGS. 7 and 8, the polycrystalline n-type silicon layer 33 is etched back. This etching back step is carried out for a period of time which is longer than that which is required for completely removing the polycrystalline n-type silicon 33 on the silicon oxide layer 30 . By selecting an appropriate etching period, the upper surface 34 a of the polycrystalline n-type silicon 34 is arranged between the upper surface and the bottom surface of the silicon oxide layer 30 . The upper surface 34 a of the polycrystalline n-type silicon 34 is preferably 200 nm (2000 Å) lower than the upper surface of the silicon oxide layer 30 . The amount of etching back of the polycrystalline n-type silicon layer 33 is 200 nm (2000 Å).

As shown in FIGS. 8 and 9, the silicon oxide layer 30 is removed by etching to expose the top portion of the n-type polycrystalline gate silicon layer 34 . The polycrystalline n-type gate silicon 34 protrudes upward by approximately 700 nm (7000 Å) above the upper surface of the silicon substrate 1 .

As shown in FIGS. 9 and 10, a silicon oxide layer 35 having a layer thickness of 100 nm (1000 Å) is formed by thermal oxidation on the surface of the protruding portion of the polycrystalline n-type gate silicon 34 . The upper surface 34 a of the polycrystalline n-type silicon layer 34 is arranged opposite the upper surface of the silicon substrate 1 by approximately 650 nm (6500 Å). The amount of the protrusion t 1 depends on the layer thickness of the silicon oxide layer 30 , the amount of etching of the polycrystalline n-type silicon layer 34 and the thickness of the silicon oxide layer 35 . These conditions are varied so that a desired amount of projecting (projecting amount) t₁ he will keep. However, the layer thickness t₃₂ of the gate oxide layer 32 , the layer thickness t₃₇ of the silicon oxide layer 37 and the layer thickness t₃₅ of the silicon oxide layer 35 must be selected so that they satisfy the following inequality, taking into account the following manufacturing steps.

t₃₂ + t₃₇ <t₃₅.

As shown in FIGS . 10 and 11, the silicon nitride layer 38 and the silicon nitride layer 37 are removed by etching without using a mask. By etching the silicon oxide layer 37 for a corresponding period of time, which is appropriate for the layer thickness t₃₇, the layer thickness of the silicon oxide layer 35 becomes t₃₅ - t₃₇ (t₃₅ - t₃₇ <t₃₂), so that the insulation breakdown voltage between the gate and the source is greater than which is held by the gate oxide layer.

As shown in FIG. 12, a source electrode 41 is formed on the upper surface of the silicon substrate 1 . A drain electrode 42 is provided on the bottom surface of the silicon substrate 1 . The trench MOS is thus completed.

The ditches described in the introduction to the description Problems arising from the trench MOS with the Structure described above solved. The trench MOS of the present The embodiment further has the following advantages.

The first advantage is that the n-type polycrystalline gate silicon can be manufactured at a high level without manufacturing technology and without critical control. The second advantage is that flattening (ie reduction in vertical dimensions) is facilitated because the depth of the n-type source diffusion layer 21 can be determined independently of other factors. Since the trench, the gate electrode and the contact area can be formed in self-alignment, no latitude is required for the alignment of masks and for the manufacturing processes between the trench and the gate electrode and between the gate electrode and the contact area. This makes it easier to reduce the size of the chip. That is the third advantage. There is also the fourth advantage that the resistance of the gate electrode is not increased.

In the above embodiment, it is desirable that the total thickness t₁₀ of the silicon oxide layer 30 , the nitride layer 38 and the silicon oxide layer 37 , the depth d₁₀ of the trench 31 and the width w₁₀ of the trench 31 satisfy the following inequality.

(t₁₀ + d₁₀) / w₁₀ 12.

The above relationship is called the aspect ratio when depositing the polycrystalline n-type silicon layer 33 of FIG. 7. If (t₁₀ + d₁₀) w₁₀ <12, then it is difficult to completely fill the trench to the bottom with polycrystalline n-type silicon 33 . There is a possibility of a cavity in the polycrystalline n-type silicon. The layer thickness t₃₂ of the MOS gate oxide layer 32 satisfies the following inequality:

t₃₂ «d10, t₃₂« w₁₀.

. With reference to Figures 7 and 1, the relationship is d₁ between the grave depth and width w₁ of the grave:

d₁ ≡ d₁₀, w₁ ≡ w₁₀.

Therefore, the relationship between t₁₀, d₁, and w₁ is more preferred wise:

(t₁₀ + d₁₀) / w₁₀ 12.

Since the protrusion amount t₁ of the polycrystalline n-type gate silicon becomes t₁ t₁₀ due to the manufacturing process with reference to Fig. 1, the relationship between the protrusion amount t₁ of the polycrystalline n-type silicon, the trench depth d₁ and the trench width w₁ preferably satisfies the following inequality:

(t₁ + d₁) / w₁ 12.

As shown in Fig. 1, the relationship between the amount of protrusion t 1 of the polycrystalline silicon layer and the trench interval w 3 preferably satisfies the following inequality:

t₁ / w₃ 2.

By satisfying the above relationship, the step coverage of the source electrode 41 becomes very advantageous.

Therefore, there is no disadvantage of disconnection at the step portion or reduction of the source electrode 41 which would cause an increase in resistance.

The present invention is not based on the above embodiment form in which it is applied to a MOS, and the present invention is also applicable to a thyristor a GTO, MCT and BRT applicable.

Embodiment 2

Fig. 13 is a sectional view of a trench MOS according to Embodiment 2. The present invention is not approximately form a MOS vertical type having a structure according to grave 1 exporting limited. The present invention is also applicable to a horizontal type MOS transistor having a trench structure as shown in FIG. 13. More specifically, the present invention is applicable to any semiconductor device having a channel formed on a trench side, in which current flows in the vertical direction of the trench.

As shown in FIG. 13, a trench 31 is formed in the surface of a semiconductor substrate 1 . The semiconductor substrate 1 has a p-type diffusion layer 20 . A gate insulating layer 32 covers the inner wall of the trench 31 . Polycrystalline silicon 34 , which has an n-type dopant and serves as a gate electrode, fills the interior of the trench 31 . The gate electrode 34 projects from the surface of the semiconductor substrate 1 . The width of the protruding portion of the gate electrode 34 is equal to the width of the gate electrode 34 within the trench 31 . An insulating layer 35 covers only the protruding portion of the gate electrode 34 . The surface area of the semiconductor substrate 1 is not covered with the insulating layer 35 . An n-type source diffusion layer 21 and an n-type drain diffusion layer 22 are formed separately from one another in or on the surface of the semiconductor substrate 1 and on both sides of the trench 31 . A source electrode 41 is connected to the n-type source diffusion region 21 . A drain electrode 42 is connected to the n-type drain diffusion region 22 . The p-type base diffusion region 20 serves as a channel.

By applying a positive voltage to the gate electrode 34 , a channel is formed on both sides of the trench 31 , so that a current flows between the source electrode 41 and the drain electrode 42 .

Embodiment 3

Fig. 14 is a sectional view of a bipolar transistor with insulated gate. From the vertical type with a trench structure (hereinafter referred to as "trench IGBT") according to embodiment 3. The trench IGBT from embodiment 3 has a silicon substrate 1 made of a p⁺-type single crystal silicon substrate 12 , an n⁺ type single crystal silicon epitaxial layer 13 , an n⁻-type single crystal silicon epitaxial layer 11 and a p-type base diffusion layer 20 . An n-type emitter diffusion layer 23 is provided in the surface of the p-type base diffusion layer 20 . In the silicon substrate 1 , a trench 31 is formed through the n-type emitter diffusion layer 23 and the p-type base diffusion layer 20 through the n⁻-type single crystal silicon epitaxy layer 11 . A gate insulating layer 32 covers the inner wall of the trench 31 . The trench 31 is filled with a polycrystalline silicon layer which contains the n-type dopant and serves as a gate electrode 34 . The gate electrode 34 projects from the surface of the semiconductor substrate 1 .

The width of the protruding portion of the gate electrode 34 is equal to the width of the electrode 34 that is buried in the trench 31 . An insulating portion 35 covers only the protruding portion of the gate electrode 34 . The surface of the semiconductor substrate 1 is not covered with the insulating layer 35 . An emitter electrode 43 is provided on the semiconductor substrate 1 so that it covers the protruding portion of the gate electrode 34 and is in contact with the n-type emitter diffusion region 23 and the p-type base diffusion region 20 . A collector electrode 44 is provided on the bottom surface of the semiconductor substrate 1 .

By applying a positive potential to the gate electrode 34 , a channel is formed on the side of the trench 31 , so that current flows between the emitter electrode 43 and the collector electrode 44 .

Embodiment 4

The present embodiment relates to another method of manufacturing the trench MOS of FIG. 1.

As shown in FIG. 15, an n⁻-type single crystal silicon epitaxial layer 11 is formed on the n⁺-type single crystal silicon substrate 10 . Then, a p-type base diffusion layer 20 and a plurality of n-type source diffusion layers 21 are formed. The n⁺-type single crystal silicon substrate 10 , the n⁻-type single crystal silicon epitaxial layer 11 , the p-type base diffusion layer 20 and the n-type source diffusion layers 21 are referred to below as silicon substrate 1 .

On the surface of the silicon substrate 1 , a silicon oxide layer 37 with a layer thickness of 30 nm (300 Å) z. B. formed by thermal oxidation. Then a silicon nitride layer 38 with a layer thickness of 100 nm (1000 Å) on the silicon oxide layer 37 z. B. excreted by CVD. On the silicon nitride layer 38 , a silicon oxide layer 30 with a layer thickness of 800 nm (8000 Å) z. B. deposited by CVD. The silicon oxide layer 30 serves as a mask for etching when a trench is formed. The thickness thereof is selected for the purpose of an etching process or for this purpose accordingly.

As shown in FIG. 16, the three-layer film of the silicon oxide layer 30 , the silicon nitride layer 38 and the silicon oxide layer 37 is patterned into a predetermined configuration so that it can serve as a mask in the subsequent trench formation. Using the patterned silicon oxide layer 30 as a mask, the trench 31 is formed in the silicon substrate 1 through the n-type source diffusion layer 21 and the p-type base diffusion layer 20 through the n⁻-type single crystal silicon epitaxial layer 11 .

In order to eliminate an etching damage in the trench 31, the inner wall of the trench 31 is to form a silicon oxide layer (not shown and hereinafter referred to as sacrificial oxide layer be distinguished) with a layer thickness of 100 nm (1000 Å) on the In nenwand of the trench 31 thermally oxidized.

As shown in FIG. 17, the silicon oxide layer 30 is etched away at the same time that the sacrificial oxide layer is removed. The surface of the silicon oxide layer 30 is reduced from a position 30 a to a position 30 b. If the etching is carried out by a wet method with hydrogen fluoride solution, the silicon oxide layer 30 is etched away by an amount that is identical in both the vertical and the lateral direction. The etching amount is controlled by the etching period. If e.g. B. 200 nm (2000 Å), the layer thickness of the silicon oxide layer 30 becomes 60 nm (600 Å), and the side wall 30 e of the opening of the silicon oxide layer 30 becomes 200 nm (2000 Å) from the side wall of the opening of the trench 31 seen here reduced.

As shown in FIG. 18, a silicon oxide layer 32 with a layer thickness of 50 nm (500 Å), which becomes a gate oxide layer, is formed covering the inner wall of the trench 31 . Then, polycrystalline silicon, which has an n-type dopant, is deposited on the silicon substrate 1 in such a way that it fills the trench 31 .

As shown in FIGS. 18 and 19, the polycrystalline n-type silicon layer 33 is etched back. The etching step is carried out for a period of time that is longer than the period in which the polycrystalline n-type silicon layer 33 on the silicon oxide layer 30 is completely removed. More specifically, the polycrystalline silicon layer 33 is etched back until the top surface thereof is sandwiched between the top surface and the bottom surface of the silicon oxide layer 30 . The position of the upper surface 34 a of the polycrystalline n-type silicon 34 is preferably 200 nm (2000 Å) below or below the surface of the silicon oxide layer 30 .

As shown in FIGS. 19 and 20, the silicon oxide layer 30 is removed by etching. As a result, the n-type polycrystalline gate silicon layer 34 protrudes laterally about 400 nm (4000 Å) over the surface of the silicon nitride layer 38 and also about 200 nm (2000 Å) over the opening of the trench 31 . In this way, a gate structure with a T-shaped cross section is obtained.

As shown in FIGS. 20 and 21, the projecting portion of the polycrystalline n-type gate silicon layer 34 is thermally oxidized, thereby forming a silicon oxide film 35 is is. The layer thickness of the silicon oxide layer 35 is selected such that the laterally projecting section of the poly-crystalline n-type silicon layer 34 is completely oxidized. If e.g. For example, if the amount of lateral protrusion is 200 nm (2000 Å), the laterally protruding portion can be completely oxidized by adjusting the layer thickness of silicon oxide layer 35 to approximately 400 nm (4000 Å). As a result, the width of the n-type polycrystalline gate silicon 34 can be set equal to or less than the width of the opening portion of the trench 31 . Such thermal oxidation makes the T-shaped cross section of the gate an I-shaped cross section of the gate. The silicon oxide layer 35 is preferably thick before being used as an interlayer insulating layer between the source electrode and the gate electrode. However, a side effect is poor step coverage of the emitter electrode. For this reason, the layer thickness must be selected from an integral point of view, ie from a point of view that keeps an eye on the entire situation. The layer thickness of the silicon oxide layer 35 depends on the amount of lateral protrusion of the polycrystalline n-type gate silicon layer 34 . An arbitrary or freely selectable layer thickness of the silicon oxide layer 35 can be varied by varying the conditions of the layer thickness of the silicon oxide layer 30 deposited in this way, the etching amount of the silicon oxide layer 30 , and the etching amount (up to 34 a) of the polycrystalline n-type silicon layer 34 , taking into account the protrusion amount t 1 to be chosen.

It is also possible, the thickness of the silicon oxide layer 35 by a widely held end of etching (over-all-Ät zen) after forming the silicon oxide layer 35 to reduzie ren. However, the relationship between the layer thickness must t₃₂ the gate oxide layer 32, the layer thickness t₃₇, the lower silicon oxide layer 37 and the layer thickness t₃₅ of the silicon oxide layer 35 are chosen so that the following inequality is met:

t₃₂ + t₃₇ <t₃₅.

As shown in FIGS . 21 and 22, the silicon nitride layer 38 and the silicon oxide layer 37 are etched without using a mask. By etching the silicon oxide layer 37 for a period which matches the layer thickness t₃₇, the layer thickness of the silicon oxide layer 35 becomes t₃₅ - t₃₇ (t₃₅ - t₃₇ <t₃₂), so that the insulation breakdown voltage between the gate and the source is higher than that of the gate oxide layer is held. Therefore, there is no problem in the properties of the semiconductor device.

As shown in FIG. 23, the source electrode 41 is formed on the surface of the silicon substrate 1 and the drain electrode 42 is formed on the bottom surface of the silicon substrate 1 . A trench MOS has been completed in this way.

According to the present embodiment, there is one additional step of victim oxidation (i.e. an additional Oxidation) to remove damage or contaminants conditions that occurred at the time of the etching when the gra have been generated. Therefore the fifth advantage, näm improving the electrical properties of a trench MOS, and the first to fourth advantages in embodiment 1 have been achieved.

The present invention is not limited to that described above Embodiment in which a MOS trench structure from the vertical Type used is limited. The present invention is also applicable to any semiconductor device that one channel formed on the trench side with the power line in the vertical direction of the trench, such as. B. one Horizontal type MOS with a trench structure and an IGBT of the vertical type with a trench structure.

It is preferable that the present embodiment except which, as in embodiment 1, satisfies the following inequality:

(t₁ + d₁) / w₁ 12, t₁ / w₃ 2.

Embodiment 5

The present embodiment relates to another Process for producing the trench MOS.

As shown in FIG. 24, an n⁻-type single crystal silicon epitaxial layer 11 is formed on an n⁺-type single crystal silicon substrate 10 . Then, a p-type base diffusion layer 20 and a plurality of n-type source diffusion layers 21 are formed. These are referred to in the following as a silicon substrate 1 .

On the surface of the silicon substrate 1 , a silicon oxide layer 30 with a thickness of 800 nm (8000 Å) z. B. formed by CVD. The silicon oxide layer 30 serves as a mask in an etching process to form a trench. The layer thickness is selected so that it can be used in the etching process.

As shown in Fig. 25, the silicon oxide layer 30 is patterned into a predetermined configuration so that it can serve as a mask in the formation of a trench. Using the patterned silicon oxide layer 30 as a mask, a trench 31 is formed in the silicon substrate 1 through the n-type source diffusion layer 21 and the p-type base diffusion layer 20, the n⁻-type single crystal silicon epitaxial layer 11 being formed.

As shown in FIG. 26, a sacrificial oxide layer with a layer thickness of 100 nm (1000 Å) (not shown) is formed in the trench 31 by thermal oxidation for the purpose of eliminating etching damage in the trench 31 . Then, when the sacrificial oxide layer is removed, the silicon oxide layer 30 is also etched. The surface is reduced from a position 30 a to a position 30 b. By performing this wet etching method using a hydrogen fluoride solution, the silicon oxide layer 30 is etched away by an identical amount in both the thickness and side directions. This amount of etching can be controlled by the etching period. If the silicon oxide film 30 about 200 nm (2000 Å) is etched away, the film thickness of silicon oxide film 30 is 600 nm (6000 Å), and the side wall 30 e of the silicon oxide film 30 at the opening of the silicon oxide layer 30 is opposite to the Be tenwand of the trench 31 ( ie away from this side wall) by 200 nm (2000 Å).

As shown in FIG. 27, a silicon oxide layer 32 with a layer thickness of 50 nm (500 Å), which becomes a gate oxide layer, is formed on the inner wall of the trench 31 . Then, a polycrystalline silicon layer 33 having an n-type dopant is deposited on the silicon substrate 1 so as to fill the trench 31 . The layer thickness of the gate oxide layer 32 is varied in accordance with the required or desired properties.

As shown in FIGS. 27 and 28, the polycrystalline n-type silicon layer 33 is etched back. This etching step is carried out for a period of time that is longer than the time required to completely etch away the polycrystalline n-type silicon layer 33 on the silicon oxide layer 30 . Ge said more precisely is carried out the etching so that the upper top surface 34 at 30 is a polycrystalline n-type silicon layer 34 200 nm (2000 Å) deeper than the surface of the silicon oxide layer in order.

As shown in FIGS . 28 and 29, when the silicon oxide layer 30 is removed by etching, the polycrystalline n-type gate silicon layer 34 is approximately 400 nm (4000 Å) from the surface of the silicon substrate 1 and laterally around 200 nm (2000 Å) away from the opening of the trench 31 . In this way, a gate structure with a T-shaped cross section is obtained.

As shown in Fig. 30, the surface of the projecting portion is the n-type polycrystalline silicon layer 34 is thermally oxidized, which advantage resul in a silicon oxide film 35th The layer thickness of the silicon oxide layer 35 is selected so that the laterally projecting section of the polycrystalline n-type silicon layer 34 is completely oxidized. If e.g. B. the amount of lateral protrusion is 200 nm (2000 Å), the laterally protruding portion can be completely oxidized by adjusting the layer thickness of the silicon oxide layer 35 to about 400 nm (4000 Å). As a result, the width of the n-type polycrystalline gate silicon layer is equal to or less than the width of the opening of the trench 31 . Furthermore, a silicon oxide layer 35 with the same layer thickness is formed on the polycrystalline n-type gate silicon layer 34 . The silicon oxide layer 35 can be left as it is, or its layer thickness can be reduced by etching carried out everywhere. Alternatively, it can be removed completely.

Although the layer thickness of the silicon oxide layer 35 is determined depending on the amount of lateral protrusion of the polycrystalline n-type gate silicon layer 30 , an arbitrary (ie freely selectable) layer thickness can be varied by varying the conditions of the layer thickness of the silicon oxide layer 30 as it is deposited, the etching amount of the silicon oxide layer 30 and the etching amount (up to 34 a) of the polycrystalline n-type silicon layer 34 , taking into account the protrusion amount of t 1.

As shown in FIG. 31, an intermediate layer with a layer thickness of 800 nm (8000 Å) is deposited on the surface of the silicon substrate 1 by CVD.

As shown in FIG. 32, the intermediate layer 36 is patterned by photolithography, resulting in a contact area on the surface of the silicon substrate 1 .

As shown in FIG. 33, a source electrode 41 is formed on the surface of the silicon substrate 1 . A drain electrode 42 is formed on the bottom surface of the silicon substrate 1 . This completes a trench MOS.

By adding the victim oxidation step to the elimination damage and impurities caused by the etching process were created to form the trench, the fifth Advantage of improving the electrical properties of the Gra received ben-MOS.

The present invention is not based on the present embodiment form in which a vertical type MOS with a trench structure is used, limited. The present invention is also applicable to any semiconductor device in which  a channel formed on the trench side and a stream in the vertical direction of the trench is directed such. B. one Horizontal type MOS with the trench structure and an IGBT of the vertical type with a trench structure.

The present embodiment preferably also fulfills the following inequality as in embodiment 1 :

(t₁ + d₁) / w₁ 12, t₁ / w₃ 2.

Embodiment 6

Fig. 34 is a sectional view of a trench MOS according to Embodiment 6.

As shown in FIG. 34, a trench MOS has a silicon substrate 1 . The silicon substrate 1 has an n⁺-type single-crystal silicon substrate 10 , an n⁻-type single-crystal silicon epitaxial layer 11 , a p-type base diffusion layer 20 and an n-type source diffusion layer 21 . In the silicon substrate 1 , a trench 31 is formed through the n-type source diffusion layer 21 and the p-type base diffusion layer 20 through the n⁻-type single-crystal silicon epitaxial layer 11 . A gate insulating layer 32 covers the inner wall of the trench 31 . A gate electrode 34 , which projects upward above the surface of the silicon substrate 1 , is buried in the trench 31 . The jumping portion of the gate electrode 34 is reduced in width as a function of height. An insulating layer 35 covers only the protruding portion of the gate electrode 34 . The upper surface area of the silicon substrate 1 is not covered with the insulating layer 35 . A source electrode 41 is formed on the upper surface of the silicon substrate 1 . A drain electrode 42 is formed on the bottom surface of the silicon substrate 1 .

According to the present embodiment, the width of the protruding portion of the gate electrode 34 becomes smaller as a function of the height. Therefore, there is an advantage that the step coverage of the source electrode 41 is improved.

A method of manufacturing the trench MOS of Fig. 34 will be described below.

First, a process is carried out that is identical to that shown in FIGS. 5 to 8.

As shown in FIG. 35, the silicon oxide layer 30 is etched back by 400 nm (4000 Å) so that the polycrystalline n-type gate silicon layer 34 protrudes upward by approximately 200 nm (2000 Å) from the surface of the silicon oxide layer 30 . In comparison to embodiment 1, in which the silicon oxide layer 30 is completely etched away, the present embodiment is characterized in that the silicon oxide layer 30 remains ver.

As shown in Fig. 36, the surface of the projecting portion of the gate electrode 34 is thermally oxidized to form a silicon oxide layer 35 a with a layer thickness of 100 nm (1000 Å).

As shown in FIGS. 36 and 37, the silicon oxide layer 30 are etched and the silicon oxide layer 35 a. The amount of etching is chosen so that the remaining thickness of the silicon oxide layer 30 is approximately 200 nm (2000 Å). At this time, the surface of the n-type polycrystalline gate silicon layer 34 was consumed by the oxidation (ie, part of the material is converted and then etched), resulting in a stepped portion on the surface thereof.

As shown in FIGS. 37 and 38, the surface of the protruding portion of the gate electrode 34 is further oxidized by thermal oxidation, resulting in a silicon oxide layer 35 b with a layer thickness of 100 nm (1000 Å).

As shown in FIGS. 38 and 39, the silicon oxide layer 30 and silicon oxide film be 35 b completely Ät zen removed.

As shown in FIG. 40, the protrusion of the gate electrode 34 is further oxidized by thermal oxidation to form a silicon oxide layer 35 c with a layer thickness of 100 nm (1000 Å).

As shown in FIGS. 40 and 41, the silicon oxide layer 38 and silicon oxide film are formed by etching 37 without Ver application of a mask removed. Then, a source electrode 41 is formed on the surface of the silicon substrate 1 . A drain electrode 42 is formed on the bottom surface of the silicon substrate 1 . A trench MOS has been completed in this way. According to the present embodiment, by repeating the oxidation step and the etching step as shown in Figs. 36 to 38, the surface of the n-type polycrystalline gate silicon layer 34 becomes a step-like surface. The width of the upper portion of the n-type polycrystalline gate silicon layer 34 becomes smaller than the width of the trench opening. The number of oxidation steps and the etching steps, which are repeated, the layer thickness of the oxide layer and the amount of etching can be chosen arbitrarily or freely on the basis of the projecting section t 1.

According to the method of Embodiment 6, a trench MOS as shown in FIGS. 42 and 43 can be formed.

In these figures, elements corresponding to those of the semiconductor device of FIG. 1 have the same reference numerals and their description is not repeated.

Embodiment 7

The present embodiment relates to another Process for producing a trench MOS, in which the width  of the protruding portion of the gate electrode all radio tion of the height becomes smaller.

The process sequences identical to those shown in FIGS . 5 to 8 are carried out first.

As shown in FIGS. 8 and 44, the silicon oxide layer 30 is etched to leave 200 nm (2000 Å). The polycrystalline n-type gate silicon layer 34 projects upward by approximately 400 nm (4000 Å) from the surface of the silicon oxide layer 30 .

As shown in FIG. 45, using an ion sputter etching process, the corner of the top portion of the n-type polycrystalline gate silicon layer 34 is quickly etched away, resulting in a gate structure 34 with a rounded top portion.

If the polycrystalline n-type gate silicon layer is etched isotropically 34, the upper surface and the Seitenoberflä surface of the projection of the polycrystalline n-type gate silicon layer etched 34 simultaneously, resulting in the in Fig. Gate structure 34 shown 48 with an inclination. By continuing this etching step, a gate structure can be obtained that has a slope and a rounded corner and / or edge. The etching step of the n-type polycrystalline gate silicon layer 34 is not limited to the method described above, but any method may be used as long as the width of the upper portion of the n-type polycrystalline gate silicon layer 34 after the etching process is smaller than the trench opening.

As, after the Silizi umoxidschicht 30 is completely removed by etching in Figs. 45 is shown and 46, the upper surface of the protrusion of the gate electrode 34 oxidizes dation by thermal Oxi what nm in a silicon oxide film 35 having a film thickness of 100 ( 1000 Å) results.

Then the silicon nitride layer 38 and the silicon oxide layer 37 are removed by etching.

As shown in FIG. 47, a source electrode 41 is formed on the upper surface of the silicon substrate 1 . The drain electrode 42 is formed on the bottom surface of the silicon substrate 1 . A trench MOS has been completed in this way.

As shown in Fig. 45 with respect to the present embodiment, the etching amount of the polycrystalline n-type gate silicon layer 34 can be arbitrarily selected by varying the etching amount of the silicon oxide layer 30 and the layer thickness of the silicon oxide layer 35 with respect to the protrusion amount t 1. The etching of the polycrystalline n-type gate silicon layer 34 can be carried out with a remaining silicon oxide layer 30 . In addition, the etching can be performed with a removed silicon nitride layer 38 and an exposed silicon oxide layer 37 .

According to the method of Embodiment 7, a trench MOS as shown in Figs. 49, 50, 51 and 52 can be made. In these figures, elements corresponding to those of the trench MOS of FIG. 1 are given the same reference numerals and their description is not repeated.

Embodiment 8

The present embodiment relates to the case in FIG that described above with reference to Embodiment 4 Manufacturing process on a conventional manufacturing process is applied to a trench MOS.

First, a trench 31 is formed according to the method shown in FIGS. 15 and 16.

Then, a silicon oxide film (not shown, sacrificial oxide film) with a film thickness of 200 nm (2000 Å) is formed in the trench 31 by thermal oxidation. Then, when removing the sacrificial oxide layer, the silicon oxide layer 30 , which serves as a mask for trench formation, is simultaneously etched. By performing this etching e.g. B. by a wet method using a hydrogen fluoride solution, the silicon oxide layer 30 is etched away in both the vertical direction and the horizontal direction by an identical amount. This etching amount is controlled by the etching period. If e.g. For example, the silicon oxide film is etched by 300 nm (3000 Å) 30, the thickness of the silicon oxide film 30 is 500 nm (5000 Å), so that the side wall nm 30 e of the opening of the trench 31 away to 300 (3000 Å) is reduced .

As shown in FIG. 18, a silicon oxide layer 32 with a layer thickness of 50 nm (500 Å), which becomes a gate oxide layer, is formed in the trench 31 . Then, a polycrystalline silicon layer 33 containing n-type dopant is deposited on the surface of the silicon substrate 1 so as to fill the trench 31 .

As shown in FIGS. 18 and 19, the polycrystalline n-type silicon layer 33 is etched back. This etching step is carried out for a period of time which is longer than the period of time which is required for completely etching away the polycrystalline n-type silicon layer 33 on the silicon oxide layer 30 . The etch-back is more specifically performed such that the upper surface 34 is located a polycrystalline n-type silicon layer 34 200 nm (2000 Å) xidschicht lower than the upper surface of the Siliziumo 30th

As shown in FIGS . 19 and 20, after the silicon oxide layer 30 is removed by etching, the polycrystalline n-type gate silicon layer 34 jumps up about 300 nm (3000 Å) from the surface of the silicon nitride layer 38 and laterally approximately 300 nm (3000 Å) from the opening of the trench 31 . A gate 34 with a T-shaped cross section is thus obtained.

As shown in Fig. 53, the upper portion of the gate electrode 34 is thermally oxidized to form a silicon oxide layer 35 with a layer thickness of 100 nm (1000 Å). By this thermal oxidation, the surface of the polycrystalline n-type silicon layer 34 is consumed, that is, converted, so that the amount of protrusion upward and in the lateral direction becomes 250 nm (2500 Å), respectively. The amount of protrusion t 1 upwards and the amount of protrusion in the lateral direction depends on the layer thickness of the silicon oxide layer 30 , the etching amount of the silicon oxide layer, the etching amount of the polycrystalline n-type silicon layer 34 and the thickness of the silicon layer 35 formed by this step. The corresponding conditions can be varied accordingly so that a desired amount before standing t₁ and a desired amount of lateral projection he will keep.

It should be noted that the relationship between the layer thickness t₃₂ of the gate oxide layer 32 , the layer thickness t₃₇ of the lower Si silicon oxide layer 37 and the layer thickness t₃₅ of the silicon oxide layer 35 formed by this step must be selected so that the following inequality taking into account the following manufacturing steps:

t₃₂ + t₃₇ <t₃₅.

As shown in FIGS. 53 and 54, which are Siliziumni tridschicht 38 and 37 etched the silicon oxide film without using a mask. By performing a suitable etching for the layer thickness t₃₇ of the silicon oxide layer 37 , the layer thickness of the silicon oxide layer 35 becomes t₃₅-t₃₇ ((t₃₅-t₃₇) <t₃₂), so that the insulation breakdown voltage between the gate electrode and the source is kept larger than that of the gate oxide layer . Therefore, there is no problem with the properties of the semiconductor device.

As shown in FIG. 55, a source electrode 41 is formed on the surface of the silicon substrate 1 . A drain electrode 42 is formed on the bottom surface of the silicon substrate 1 . In this way, a trench MOS is completed.

Although a vertical-type MOS manufactured as described above Type with a trench structure that the embodiment 4 ver provides similar advantages, the advantage of the sample reduction adornment reduced because of the polycrystalline n-type gate silicon protrudes laterally. However, the amount of the lateral Chen protrusion of the gate electrode in comparison with that in the Introduction to the described technique by varying the etching amount of the silicon oxide layer can be easily controlled.

The present method is on any semiconductor device tion applicable, which form a on the trench side surface th channel and the current in the vertical direction of the Like a horizontal type MOS with a Trench structure and a trench IGBT. It is also before that the present embodiment does the following satisfied:

(t₁ + d₁) / w₁ 12.

If the interval or the distance between the polycrystalline n-type silicon layers 34 is equal to w₅, the following inequality is desirably satisfied, taking into account the step coverage of the source electrode 41 :

t₁ / w₅ 2

Embodiment 9

The present embodiment relates to a method to form a conventional trench MOS according to the Manufacturing method shown in embodiment 5.

First, process flows identical to those shown in Figs. 24 to 29 are carried out.

As shown in FIGS . 24 and 25, a trench 31 is formed out. As shown in Fig. 26, a silicon oxide film (not shown and referred to as a sacrificial oxide film) with a film thickness of 200 nm (2000 Å) is formed in the trench by thermal oxidation 31 08547 00070 552 001000280000000200012000285910843600040 0002019507146 00004 08428. When removing this sacrificial oxide layer, the silicon oxide layer 35 is etched away at the same time. By performing this etching by a wet method using a hydrogen fluoride solution, the silicon oxide layer 30 is etched in both the thickness direction and the horizontal direction by an identical amount. This amount of etching can be controlled by the etching period. If the silicon oxide layer 35 z. As to 300 nm (3000 Å) is etched away, the film thickness of silicon oxide film 30 (A 5000), so that the side wall 30 is reduced to 500 nm 30 e of the silicon oxide layer from the opening of the trench 31 forth nm to 300 (3000 Å) becomes.

As shown in FIG. 27, a silicon oxide layer 32 with a layer thickness of 50 nm (500 Å), which becomes a gate oxide layer, is formed in the trench 31 . Then, a polycrystalline silicon layer 33 containing n-type dopant is formed on the surface of the silicon substrate 1 so as to fill the trench 31 .

As shown in FIG. 28, the n-type polycrystalline silicon layer 33 on the silicon oxide layer 30 is completely removed by etching. Then the polycrystalline n-type silicon layer 34 is etched until the upper surface 34 a 200 nm (2000 Å) below or below the surface of the silicon oxide layer 30 is arranged.

As shown in FIGS. 28 and 29 is shown, jumps, after the Si liziumoxidschicht 30 has been removed by etching, the poly-crystalline n-type gate silicon layer 34 up to 300 nm (3000 Å) from the surface of the silicon substrate 1 and laterally to 300 nm (3000 Å) from the opening of the trench 31 . The art will keep a gate structure with a T-shaped cross-section.

As shown in FIG. 56, a silicon oxide layer 35 with a layer thickness of 100 nm (1000 Å) is formed by thermal oxidation so as to cover the protrusion of the polycrystalline n-type silicon layer 34 . By this oxidation, the surface of the protrusion of the polycrystalline n-type silicon layer 34 is oxidized, and the amount of the protrusion upward and the protrusion in the lateral direction becomes 250 nm (2500 Å), respectively. The protruding t₁ upward and the protruding to the side to be dependent on the layer thickness of the Silizi umoxidschicht 30, the etching amount of silicon layer 30, the etching amount of the polycrystalline n-type silicon layer 34 and the Si liziumoxidschicht 35, which is formed by this manufacturing step of, certainly. The corresponding conditions can be varied accordingly, so as to maintain the desired amount of protrusion t 1 and the desired amount of lateral protrusion. The step of forming the silicon oxide layer 35 may be omitted.

As shown in Fig. 57, an intermediate layer 36 with a layer thickness of 800 nm (8000 Å) is formed on the silicon substrate 1 by CVD.

As shown in FIGS. 57 and 58, the intermediate layer 36 is etched, resulting in a contact area on the surface of the silicon substrate 1 .

As shown in FIG. 59, a source electrode 41 is formed on the surface of the silicon substrate 1 . A Drainelek electrode 42 is formed on the back of the silicon substrate 1 . In this way, a trench MOS is completed.

Although a vertical type MOS with a trench structure, the through the manufacturing step described above is identical advantages for that of embodiment 5 enables, the effect of pattern reduction is lower than in embodiment 5 because the polycrystalline n-type Gatesi protrudes laterally. However, compared to  the technique described in the introduction to the Be wear the lateral protrusion of the gate electrode easily Varying the amount of etching of the silicon oxide layer is controlled by who the.

The present method is applicable to all semiconductor devices applicable, the one trained on the side wall (of a trench) deten channel and current in the vertical direction of the Channel, such as b. a horizontal type MOS with egg trench structure and a trench IGBT.

It is preferable that the following inequality differ from that before lying embodiment is fulfilled:

(t₁ + d₁) / w₁ 12.

When the distance of the polycrystalline n-type silicon 34 is equal to w,, it is preferable that the following relationship is considered considering the step coverage of the source electrode 41 :

t₁ / w₅ 2.

Embodiment 10

The present invention is not limited to the above embodiment, in which the top surface of the polycrystalline n-type gate silicon 34 is planar in the sectional view. If the layer thickness of the n-type polycrystalline silicon layer 33 filling the trench 31 is reduced and sufficient leveling is not performed, the top surface of the n-type polycrystalline gate silicon layer 34 will become concave. Comparable advantages can be obtained even in this state. In this case, advantages can be obtained in that the layer thickness of the polycrystalline n-type silicon 33 is reduced to improve productivity, and the leveling step can be omitted, and the disadvantage of the difficulty in the process with respect to the polycrystalline n-type gate silicon layer 34 is avoided. Therefore, the top surface of the polycrystalline n-type gate silicon 34 can be selected to be flat or concave depending on the viewpoint of both the advantages and the disadvantages.

According to a semiconductor device according to an embodiment form of the present invention only covers the insulating layer the protruding portion of the gate electrode, and covered it the surface area of the semiconductor substrate is not. That's why he the insulating layer does not stretch in the lateral direction tion, whereby the advantage is obtained that a reduction the occupied area is made possible.

According to a semiconductor device after another off leadership form of the present invention is the projecting Ab cut the gate electrode in width as a function of Height reduced. That enables the benefit of improving the Step coverage of a first electrode.

According to a method of manufacturing a semiconductor Device according to a further embodiment of the present Invention can the silicon nitride layer by etching without Ver using a mask. Therefore no mask is made direction needed, which in a simplification of manufacture step results.

According to a method of manufacturing a semiconductor device according to yet another embodiment of the present invention, the silicon oxide layer on the Surface of the silicon substrate without using a mask etched, causing the top portion of the polycrystalline silicon to jump up against the surface of the Silicon substrate is brought. That is why there is no mask alignment tion necessary, which in a simplification of manufacture step results.

According to a method of manufacturing a semiconductor device according to yet another embodiment of the  In the present invention, the silicon nitride layer is etched zen removed without using a mask. A mask alignment is not required, so that the manufacturing step is simplified can be.

Claims (18)

1. semiconductor device with
a semiconductor substrate ( 1 )
a trench ( 31 ) which is provided in the surface of the semiconductor substrate ( 1 ),
a gate insulating layer ( 32 ) covering the inner wall of the trench ( 31 ),
a gate electrode ( 34 ) which fills the trench ( 31 ) and projects upward against the surface of the semiconductor substrate ( 1 ), the width of the projecting section of the gate electrode ( 34 ) being equal to or smaller than the width of the gate electrode section, which fills the trench ( 31 ), is set, and
an insulating layer ( 32 ) formed to cover only the protruding portion of the gate electrode ( 34 ),
one side surface of the trench ( 31 ) being operated as a channel. 2. Semiconductor device according to claim 1, characterized by
a first electrode ( 41 , 43 ) provided on the upper surface of the semiconductor substrate ( 1 ), and
a second electrode ( 42 , 44 ) which is provided on the bottom surface of the semiconductor substrate ( 1 ),
wherein current is conducted between the first and second electrodes ( 41 , 43 , 42 , 44 ) perpendicular to the semiconductor substrate ( 1 ). 3. Semiconductor device according to claim 1 or 2, characterized by
a first and a second electrode ( 41 , 42 ) which are formed separately from one another on the semiconductor substrate ( 1 ),
wherein current is conducted from the first electrode to the second electrode ( 41 , 42 ). 4. Semiconductor device according to one of claims 1 to 3, characterized by
a first conductive layer ( 21 ) of a first conductivity type which is formed in the surface of the semiconductor substrate ( 1 ) on both sides of the gate electrode so that it is in contact with the first electrode ( 41 ),
a third conductive layer ( 11 ) of the first conductivity type which is formed in the bottom surface of the semiconductor substrate ( 1 ) so as to be in contact with the second electrode ( 42 ), and
a second conductive layer ( 20 ) of a second conductivity type, which is formed in the semiconductor substrate ( 1 ) and between the first conductive layer ( 21 ) and the third conductive layer ( 11 ) and is operated as a channel,
wherein the trench ( 31 ) extends from the surface of the semiconductor substrate ( 1 ) into the third conductive layer ( 11 ). 5. Semiconductor device according to one of claims 1 to 4, characterized in that
that the semiconductor substrate ( 1 ) is made of silicon,
that the gate insulating layer ( 32 ) is formed from a silicon oxide layer, and
that the gate electrode ( 34 ) is formed from polycrystalline silicon containing p-type or n-type dopant. 6. A semiconductor device according to claim 4 or 5, characterized in
that the first conductive layer ( 21 ) is a source region, and
that the third conductive layer ( 11 ) is a drain region. 7. Semiconductor device according to one of claims 1 to 6, characterized by
a first conductive layer ( 23 ) of a first conductivity type, which is an emitter region and is formed in the surface of the semiconductor substrate ( 1 ) on both sides of the gate electrode such that it is in contact with the first electrode ( 43 ),
a second conductive layer ( 20 ) of a second conductivity type which is provided in the semiconductor substrate ( 1 ) such that it is in contact with the first conductive layer ( 23 ),
a fourth conductive layer ( 13 ) of the second conductivity type which is a collector region and is provided on the bottom surface of the semiconductor substrate ( 1 ) so as to be in contact with the second electrode ( 44 ), and
a third conductive layer ( 11 ) of the first conductivity type, which is provided in the semiconductor substrate ( 1 ) and between the second and fourth conductive layers ( 20 , 13 ),
wherein the trench ( 31 ) extends from the surface of the semiconductor substrate ( 1 ) into the third conductive layer ( 11 ). 8. semiconductor device with
a semiconductor substrate ( 1 ),
a trench ( 31 ) which is provided on the surface of the semiconductor substrate ( 1 ),
a gate insulating layer ( 32 ) covering the inner wall of the trench ( 31 ),
a gate electrode ( 34 ) that fills the trench ( 31 ) and protrudes upward from the surface of the semiconductor substrate ( 1 ), the protruding portion of the gate electrode ( 34 ) having a reduced width as a function of height, and
an insulating layer ( 35 ) which is provided to cover the projecting portion of the gate electrode ( 34 ),
one side surface of the trench ( 31 ) being operated as a channel. 9. A semiconductor device according to claim 8, characterized by
a first electrode ( 41 ) provided on the upper surface of the semiconductor substrate ( 1 ), and
a second electrode ( 42 ) which is provided on the back of the semiconductor substrate ( 1 ),
wherein a current is conducted perpendicular to the semiconductor substrate between the first and the second electrode. 10. The semiconductor device according to claim 8, characterized by a first and a second electrode ( 41 , 42 ), which are provided separately from one another in the semiconductor substrate ( 1 ), wherein a current from the first electrode ( 41 ) to the second electrode ( 42 ) flows. 11. Semiconductor device according to one of claims 1 to 10, characterized in that
that the following inequality (t 1 + d 1) / w 1 12 is satisfied, the amount of protrusion of the protruding portion of the gate electrode ( 34 ) being t 1, the depth of the trench ( 31 ) being d 1 and the width of the trench ( 31 ) being w 1 is. 12. A semiconductor device according to any one of claims 1 to 11, characterized in that the following inequality t₁ / w₃ 2 is satisfied, the amount of protrusion of the projecting portion of the gate electrode ( 34 ) being equal to t₁ and the distance between the trench ( 31 ) and one this trench ( 31 ) is adjacent trench w₃. 13. A method of manufacturing a semiconductor device comprising the steps of:
Preparing a silicon substrate ( 1 ),
successively forming a silicon oxide layer ( 37 ), a silicon nitride layer ( 38 ) and a silicon oxide layer ( 30 ) on the surface of the silicon substrate ( 1 ) to obtain a three-layer film,
Patterning the three-layer film and then forming a trench ( 31 ) in the surface of the silicon substrate ( 1 ) using the patterned three-layer film as a mask,
Forming a silicon oxide layer which becomes a gate oxide layer ( 32 ) in the trench ( 31 ) with the three-layer film remaining, and then depositing polycrystalline silicon in the trench ( 31 ) and on the surface of the silicon substrate ( 1 ),
Etching back the polycrystalline silicon until the upper surface thereof is arranged higher than the upper surface of the silicon substrate ( 1 ) and lower than the upper surface of the upper silicon oxide layer ( 30 ) of the three-layer film,
Etching the top silicon oxide layer ( 30 ) of the three-layer film to expose the top portion of the polycrystalline silicon so that the top portion protrudes upward from the surface of the silicon substrate ( 1 ),
Oxidizing the above polycrystalline silicon to form a silicon oxide layer thicker than the lower silicon oxide layer ( 37 ) of the three-layer film so as to enclose the upper portion of the above polycrystalline silicon,
Removing the silicon nitride layer ( 38 ) by etching without using a mask,
completely removing the silicon oxide layer ( 37 ) on the surface of the silicon substrate ( 1 ) such that the silicon oxide layer surrounding the upper portion of the above polycrystalline silicon remains, whereby a contact region is formed, and
Form a desired electrode ( 41 ). 14. A method of manufacturing a semiconductor device comprising the steps of:
Preparing a silicon substrate ( 1 ),
successively forming a silicon oxide layer ( 37 ), a silicon nitride layer ( 38 ) and then a silicon oxide layer ( 30 ) on the silicon substrate ( 1 ) to form a three-layer film,
Patterning the three-layer film so that it can serve as a mask in a subsequent trench formation, and forming an opening with a predetermined configuration in the three-layer film,
Forming a trench ( 31 ) in the semiconductor substrate ( 1 ) using the patterned three-layer film,
Etching a side wall of the opening of the upper silicon oxide layer ( 30 ) of the three-layer film such that the width of the opening is greater than the width of the opening of the trench,
Forming a silicon oxide layer which becomes a gate oxide layer ( 32 ) in the trench ( 31 ) with the three-layer film remaining, and then depositing polycrystalline silicon in the trench ( 31 ) and on the surface of the silicon substrate ( 1 ),
Etching back the polycrystalline silicon until the upper surface thereof is higher than the surface of the silicon substrate ( 1 ) and below the upper silicon oxide layer ( 30 ) of the three-layer film,
Etching the top silicon oxide layer of the three-layer film to expose the top portion of the polycrystalline silicon such that the top portion of the polycrystalline silicon faces upward from the surface of the silicon substrate ( 1 ) and laterally from the opening of the trench ( 31 ),
Oxidizing the upper portion of the polycrystalline silicon that protrudes laterally opposite the opening of the trench ( 31 ) such that the upper portion of the polycrystalline silicon does not protrude laterally of the opening of the trench ( 31 ) and has a structure that is upwardly opposite that Protruding surface of the silicon substrate and forming a silicon oxide layer which is thicker than the lower silicon oxide layer ( 37 ) of the three-layer film such that the upper portion of the polycrystalline silicon layer is included,
Removing the silicon nitride layer ( 38 ) by etching without using a mask,
completely removing the silicon oxide layer ( 37 ) on the surface of the silicon substrate ( 1 ) while the silicon oxide layer surrounding the upper portion of the protruding polycrystalline silicon remains, thereby forming a contact region, and
Form a desired electrode ( 41 ). 15. A method of manufacturing a semiconductor device comprising the steps of:
Preparing a silicon substrate ( 1 ),
Forming a silicon oxide layer ( 30 ) on the surface of the silicon substrate ( 1 ),
Patterning the silicon oxide layer ( 30 ) such that it can act as a mask in a subsequent formation of a trench ( 31 ), an opening having a predetermined configuration being formed in the silicon oxide layer ( 30 ),
Forming a trench ( 31 ) in the semiconductor substrate ( 1 ) using the patterned silicon oxide layer ( 30 ) as a mask, etching a side wall of the opening of the silicon oxide layer ( 30 ), the width of the opening being greater than the width of the opening of the trench ( 31 ) becomes,
Forming a silicon oxide layer which becomes a gate insulating layer ( 32 ) in the trench ( 31 ), with the silicon oxide layer ( 30 ) remaining, and then depositing polycrystalline silicon in the trench ( 31 ) and on the surface of the silicon substrate ( 1 ) ,
Etching back the polycrystalline silicon until the upper surface thereof is arranged higher than the surface of the silicon substrate ( 1 ) and lower than the surface of the silicon oxide layer ( 30 ) which is formed on the semiconductor substrate ( 1 ),
Etching the silicon oxide layer ( 30 ) on the surface of the semiconductor substrate ( 1 ) to expose the upper portion of the semiconductor substrate ( 1 ) such that the upper portion of the polysilicon silicon upwards over the surface of the silicon substrate ( 1 ) and also laterally opposite protrudes from the opening of the trench ( 31 ),
Oxidizing the upper portion of the polycrystalline silicon, which protrudes laterally with respect to the opening of the trench (31) for forming the side opposite the opening of the trench (31) is not above polycrystalline silicon and off of the Siliziumsub formation of up to the surface strates ( 1 ) protruding polycrystalline silicon,
Forming a silicon oxide layer ( 35 ) which encloses the upper portion of the polycrystalline silicon, and
Forming a contact area and then forming a desired electrode ( 41 ). 16. A method for producing a semiconductor device according to claim 14 or 15, characterized by the steps:
Exposing the upper portion of the polycrystalline silicon such that the upper portion of the polycrystalline silicon projects upward from the surface of the silicon substrate ( 1 ) and laterally from the opening of the trench ( 31 ), and
Forming a silicon oxide layer such that the polycrystalline silicon is enclosed,
wherein the upper portion of the polycrystalline silicon has a structure projecting laterally from the opening of the trench ( 31 ) and projecting upwards from the surface of the silicon substrate ( 1 ). 17. A method of manufacturing a semiconductor device according to any one of claims 13 to 16, characterized in that the step of oxidizing the polycrystalline silicon of the upper portion of the polycrystalline silicon projecting upward above the surface of the silicon substrate ( 1 ) and etching the obtained oxide layer in such a manner it is repeated that the diameter of the upper portion of the polycrystalline silicon projecting upward from the surface of the silicon substrate ( 1 ) becomes smaller than the diameter of the polycrystalline silicon filled in the trench ( 31 ). 18. A method for producing a semiconductor device according to one of claims 13 to 17, characterized in that an etching step which results from the following etching steps
(a) and (b) existing group is selected,
(a) isotropic etching of the polycrystalline silicon,
(b) performing etching to round the corner of the top surface of the polycrystalline silicon,
on the upper portion of the polycrystalline silicon, which protrudes upward from the surface of the silicon substrate ( 1 ), is carried out such that the diameter of the upper portion of the polycrystalline silicon, which protrudes from the surface of the silicon substrate ( 1 ), is smaller than the diameter of the trench ( 31 ) filling polycrystalline silicon.