CN106024636A - Grooved gate power device and manufacturing method - Google Patents
Grooved gate power device and manufacturing method Download PDFInfo
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- CN106024636A CN106024636A CN201610551898.0A CN201610551898A CN106024636A CN 106024636 A CN106024636 A CN 106024636A CN 201610551898 A CN201610551898 A CN 201610551898A CN 106024636 A CN106024636 A CN 106024636A
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- 238000005516 engineering process Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a grooved gate power device and a manufacturing method thereof. Through oxidizing one part, higher than a second block layer, of a gate material layer in a groove to form a second oxidization layer, the second oxidization layer covers part of the second block layer, and thus, the whole grooved gate structure is protected, the grooved gate is not influenced by a contact hole instability process during the processing process in the existing lithography equipment condition, production of products with a smaller line width and a larger overlay margin is realized, and the parameters and the reliability of the products meet requirements.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of grooved gate power device and manufacture method.
Background technology
Power device can be divided into Power IC (integrated circuit) device and power discrete device two class, power discrete
Device includes again power MOSFET (Metal-Oxide Semiconductor field-effect transistor), high power transistor
With devices such as IGBT (insulated gate bipolar transistor).Power device is all based on planar technology production in early days,
But along with the development of semiconductor technology, small size, high-power, high-performance become main development trend.
As a example by planar technology MOSFET element, owing to itself internal JFET (junction field effect transistor) posts
The restriction of raw resistance, the area of single primitive unit cell reduces limited, thus makes increase primitive unit cell density become highly difficult,
The conducting resistance (RDSON) being difficult to make planar technology MOSFET reduces further.Trench process is owing to inciting somebody to action
Raceway groove becomes vertical from level, eliminates the impact of planar structure parasitism JFET resistance, makes cellular size significantly
Reduce, primitive unit cell density can be increased on this basis, the overall width of raceway groove in raising unit are chip, so that it may
So that device channel width-over-length ratio on unit silicon chip increases so that electric current increases, conducting resistance decline with
And relevant parameter is optimized, it is achieved that smaller size of tube core has greater power and high performance target,
Therefore trench process is more and more applies in New Type Power Devices.
Along with the development of semiconductor technology, persistently diminish to realize lower cost advantage and minimum feature,
In existing typical groove power device, the live width of groove and contact hole diminishes, and Pitch (pitch) width is simultaneously
Compression so that the spacing between contact hole and gate trench narrows, if now the live width of contact hole does not accomplishes foot
Enough the least, inclined precision cannot be met surplus requirement, and then occur the technological problems such as partially, it will directly lead
Cause device structure be difficult to, and then cause Vth (threshold voltage), BVds (drain-source breakdown voltage),
The abnormal parameters such as Rdson even GS short circuit (short circuit of grid source), form security risk.
Fig. 1 show in prior art MOSFET in groove power device to be held under lithographic equipment limit capacity
Easily produced problem schematic diagram.Wherein, what a-quadrant represented is the normal pattern of contact hole 4, now contacts
The live width that hole 4 is formed on Semiconductor substrate 1 surface is d1, the spacing of the groove 5 that contact hole 4 is adjacent
It is respectively a1 and a2.When the width of d1 is in the limit of power of lithographic equipment, its contact hole 4 will not go out
The topography issues that the most under-exposed, resolution is the best etc. causes.When equipment alignment ability preferably in the case of,
A1 and a2 all can meet product design to inclined margin range, a1-a2 is the smaller the better, as a1-a2=0,
Illustrating that alignment precision is optimal, alignment ability is optimal.
B Regional Representative's is when the lithographic line width of contact hole 4 by the design of equipment limit capacity but still is unsatisfactory for
Predetermined live width design requirement, finally makes contact hole 4 will contact with the grid oxygen 3 in groove 5, polysilicon 2
Abnormal pattern when having contacted.The live width that now contact hole 4 is formed on Semiconductor substrate 1 surface
For d2, the spacing of the groove 5 that contact hole 4 is adjacent is respectively b1 and b2.When b1 and b2 is respectively less than
During the pitch requirements that product allows, it may appear that the abnormal parameters such as Vth, BVds, Rdson, there is reliability wind
Danger.When b1 and b2 the most infinitely small even negative time, contact hole 4 with the grid oxygen 3 in groove 5,
Polysilicon 2 contacts, it may appear that the abnormal parameters such as GS short circuit.This is that typical live width is bigger than normal, capacity of equipment not
The failure conditions of product smaller szie processing can be met.
C Regional Representative's is to meet little linewidth requirements when the lithographic line width of contact hole 4, but lithographic equipment alignment energy
Power can not meet product structure requirement, finally makes contact hole 4 not cause parameter different in the centre of left and right groove 5
Normal structure and morphology.The live width that now contact hole 4 is formed on Semiconductor substrate 1 surface is d3, contact hole 4
The spacing of the groove 5 being adjacent is respectively c1 and c2, wherein, c1 much larger than product design to inclined surplus
Scope, c2 again less than product design to the grid in inclined margin range even contact hole 4 infinite approach groove 5
, the most easily there are the abnormal parameters such as Vth, BVds, Rdson even GS short circuit in oxygen 3, polysilicon 2.This
It is that normally but alignment precision can not meet product smaller size of inefficacy feelings to typical lithographic equipment live width ability
Condition.If in C region, c1 and c2 all then can avoid various inefficacy in product design in the range of partially.
Therefore, how under the conditions of existing lithographic equipment, less live width is realized, it is ensured that contact hole is to slot grid structure
Spacing so that contact hole and groove set are carved with enough surpluses, thus realize the device junction of less live width
The production of structure, makes the parameter of product and reliability meet requirement simultaneously, is that those skilled in the art to study
Content.
Summary of the invention
It is an object of the invention to provide a kind of grooved gate power device and manufacture method, protect slot grid structure,
Make slot grid structure not by the shadow of contact hole instability technique under the conditions of existing lithographic equipment in processing technique
Ring, it is achieved less live width and the production of bigger alignment surplus product, make the parameter of product and reliability meet
Requirement.
For solving above-mentioned technical problem, the present invention provides the manufacture method of a kind of grooved gate power device, including:
Semiconductor substrate is provided；
Sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Etch the quasiconductor lining of described 3rd trapping layer, the second trapping layer, the first trapping layer and segment thickness
The end, is to form the first groove and the second groove；
Grid dielectric is grown on first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate
Layer；
In described first groove and the second groove, form gate material layers, remove the 3rd trapping layer, described grid
Pole material layer has the part higher than described second trapping layer；
Oxidation gate material layers so that described gate material layers is higher than the part generation of described second trapping layer
Second oxide layer, and described second oxide layer covering part the second trapping layer；
Remove the part not covered by the second oxide layer in described second trapping layer；
In described Semiconductor substrate, the first groove and the second groove both sides form p-well；
N-type region is formed in p-well described in first groove and the second groove both sides in described Semiconductor substrate；
Form blanket dielectric layer on the semiconductor substrate；
Etching in described blanket dielectric layer extremely described Semiconductor substrate, form contact hole, described contact hole is positioned at
In first groove both sides and the second groove；And
P type island region is formed bottom described contact hole.
Optionally, for the manufacture method of described grooved gate power device, described first trapping layer, the second resistance
Only the material of layer and the 3rd trapping layer is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or group
Close.
Optionally, for the manufacture method of described grooved gate power device, the thickness of described first trapping layer isThe thickness of described second trapping layer isThe thickness of described 3rd trapping layer is
Optionally, for the manufacture method of described grooved gate power device, the width of described first groove is
0.05 μm-1 μm, the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is
0.1μm-50μm。
Optionally, for the manufacture method of described grooved gate power device, the first groove and the second ditch are being formed
After groove, before growth gate dielectric layer, also include:
Described in described Semiconductor substrate, the first groove and the sidewall of the second groove and diapire form the first oxidation
Layer；
Remove described first oxide layer.
Optionally, for the manufacture method of described grooved gate power device, at described first groove and the second ditch
After groove forms gate material layers, before removing the 3rd trapping layer, also include:
Produce the gate material layers on described 3rd trapping layer surface when removing deposit, make described grid material
The upper surface of layer and the upper surface flush of described 3rd trapping layer.
Optionally, for the manufacture method of described grooved gate power device, wet process oxidation technology is used to form institute
State the second oxide layer.
Optionally, for the manufacture method of described grooved gate power device, described second oxidated layer thickness is
Optionally, for the manufacture method of described grooved gate power device, described blanket dielectric layer includes covering
The first medium layer of described Semiconductor substrate.
Optionally, for the manufacture method of described grooved gate power device, described blanket dielectric layer also includes covering
Cover the second dielectric layer of described first medium layer.
Optionally, for the manufacture method of described grooved gate power device, the material of described first medium layer is
Plain silicon dioxide, silicon nitride, one or more combinations of silicon oxynitride；Described second dielectric layer
Material is boron-phosphorosilicate glass.
Optionally, for the manufacture method of described grooved gate power device, described first medium layer and second is situated between
Matter layer is all formed by chemical vapor deposition method.
Optionally, for the manufacture method of described grooved gate power device, the anti-of described second dielectric layer is formed
The source gas bag of answering includes SiH4、B2H6And/or PH3；In described second dielectric layer, the mass percent of boron is 1～5%,
The mass percent of phosphorus is 2～6%.
Optionally, for the manufacture method of described grooved gate power device, the thickness of described first medium layer isThe thickness of described second dielectric layer is
Optionally, for the manufacture method of described grooved gate power device, the sidewall of described contact hole and diapire
Extended line be 80 ° of-89 ° of angles, the degree of depth of described contact hole be less than or equal to 1 μm.
Optionally, for the manufacture method of described grooved gate power device, bottom described contact hole, form P
After type district, also include:
Forming metal level in described blanket dielectric layer, described metal level fills described contact hole；And
Described metal level is formed passivation layer.
The present invention also provides for a kind of grooved gate power device, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove extending in described Semiconductor substrate
With the second groove；
It is positioned at described first groove and the sidewall of the second groove and the gate dielectric layer of diapire；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides and runs through described blanket dielectric layer, the first resistance
Only layer extending in described Semiconductor substrate, and be positioned in described second groove and run through described overwrite media
Layer, the second oxide layer also extend in described gate material layers.
Optionally, for described grooved gate power device, described first trapping layer and the material of the second trapping layer
For silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
Optionally, for described grooved gate power device, the thickness of described first trapping layer is
The thickness of described second trapping layer is
Optionally, for described grooved gate power device, the width of described first groove is 0.05 μm-1 μm,
The degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
Optionally, for described grooved gate power device, the thickness of described second oxide layer is
Optionally, for described grooved gate power device, described blanket dielectric layer includes covering described quasiconductor
The first medium layer of substrate.
Optionally, for described grooved gate power device, described blanket dielectric layer also includes covering described first
The second dielectric layer of dielectric layer.
Optionally, for described grooved gate power device, the material of described first medium layer is plain two
Silicon oxide, silicon nitride, one or more combinations of silicon oxynitride；The material of described second dielectric layer is boron phosphorus
Silica glass.
Optionally, for described grooved gate power device, in described second dielectric layer, the mass percent of boron is
1～5%, the mass percent of phosphorus is 2～6%.
Optionally, for described grooved gate power device, the thickness of described first medium layer is
The thickness of described second dielectric layer is
Optionally, for described grooved gate power device, the sidewall of described contact hole and the extended line of diapire in
80 ° of-89 ° of angles, the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than or equal to 1 μm.
Optionally, for described grooved gate power device, also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
Compared with prior art, a kind of grooved gate power device of present invention offer and manufacture method, by by ditch
Described gate material layers in groove has higher than a part for the second trapping layer and this partial oxidation is formed the
Dioxide layer, and described second oxide layer covering part the second trapping layer, so that whole slot grid structure is protected
Protect, make slot grid structure not by contact hole instability work under the conditions of existing lithographic equipment in processing technique
The impact of skill, it is achieved less live width and the production of bigger alignment surplus product, makes the parameter of product with reliable
Sexual satisfaction requirement.
Accompanying drawing explanation
Fig. 1 is that in prior art, in groove power device, MOSFET easily goes out under lithographic equipment limit capacity
Existing problem schematic diagram；
Fig. 2 is the flow chart of the grooved gate power device manufacture method in one embodiment of the invention；
Fig. 3-11 is the structural representation in the manufacturing process of the grooved gate power device in one embodiment of the invention.
Detailed description of the invention
Below in conjunction with schematic diagram, grooved gate power device and the manufacture method of the present invention are retouched in more detail
State, which show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can revise at this
The present invention described, and still realize the advantageous effects of the present invention.Therefore, description below is appreciated that
Widely known for those skilled in the art, and it is not intended as limitation of the present invention.
Referring to the drawings the present invention the most more particularly described below in the following passage.According to following explanation and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the simplest
The form changed and all use non-ratio accurately, only in order to convenient, aid in illustrating the embodiment of the present invention lucidly
Purpose.
The present invention provides a kind of grooved gate power device and manufacture method, the manufacture method of described grooved gate power device
Including:
Step S11, offer Semiconductor substrate；
Step S12, sequentially form the first trapping layer, the second trapping layer and the 3rd resistance on the semiconductor substrate
Only layer；
Step S13, etch described 3rd trapping layer, the second trapping layer, the first trapping layer and segment thickness
Semiconductor substrate is to form the first groove and the second groove；
Step S14, raw on the first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate
Long gate dielectric layer；
Step S15, the gate material layers that formed in described first groove and the second groove, removal the 3rd trapping layer,
Described gate material layers has the part higher than described second trapping layer；
Step S16, oxidation gate material layers so that described gate material layers is higher than the one of described second trapping layer
Part produces the second oxide layer, and described second oxide layer covering part the second trapping layer；
Step S17, remove in described second trapping layer the part not covered by the second oxide layer；
Step S18, in described Semiconductor substrate, the first groove and the second groove both sides form p-well；
Step S19, in described Semiconductor substrate, in p-well described in the first groove and the second groove both sides, form N
Type district；
Step S20, form blanket dielectric layer on the semiconductor substrate；
Step S21, etch described blanket dielectric layer in described Semiconductor substrate, form contact hole, described in connect
Contact hole is positioned in the first groove both sides and the second groove；And
Step S22, bottom described contact hole formed p type island region.
Grooved gate power device and manufacture method incorporated by reference to-11 couples of present invention of Fig. 2 and Fig. 3 are situated between in detail below
Continue.
First, step S11 is performed, as shown in Figure 3, it is provided that Semiconductor substrate 20.Preferably, described half
Conductor substrate 20 can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or people in the art
Member's other semiconductive material substrate known, use silicon substrate in the present embodiment.Further, this reality
Execute in example use silicon substrate could be formed with MOSFET (mos field effect transistor),
The semiconductor device such as IGBT (isolated-gate field effect transistor (IGFET)), Schottky diode.Described Semiconductor substrate
20 N-type and the p-type doping that can also carry out certain impurity level according to the characteristic of required product.
Then, step S12 is performed, with continued reference to shown in Fig. 3, shape successively in described Semiconductor substrate 20
Become the first trapping layer the 21, second trapping layer 22 and the 3rd trapping layer 23.Described shape in Semiconductor substrate 20
First trapping layer the 21, second trapping layer 22 become and the 3rd trapping layer 23 can use the means such as oxidation or deposit
Formed.Such as, the material of described first trapping layer the 21, second trapping layer 22 and the 3rd trapping layer 23 is permissible
One or more combinations for silicon dioxide, silicon nitride, silicon oxynitride, polysilicon etc..It is also preferred that the left it is described
The thickness of the first trapping layer isThe thickness of described second trapping layer isDescribed
The thickness of the 3rd trapping layer is
Then, perform step S13, etch the 3rd trapping layer the 23, second trapping layer the 22, first trapping layer 21
And the Semiconductor substrate 20 of segment thickness, i.e. etch described 3rd trapping layer 23 to described Semiconductor substrate 20
In to form the first groove 241 and the second groove 242.Refer to Fig. 4, the first groove 241 region is
First window district 24a, the second groove 242 region is the second window region 24b.Described first window district 24a
Referring to the primitive unit cell district of power device, the second window region 24b refers to the termination environment of power device.
In step s 13, by the selectively opened window of photoetching, photoresist is used to shelter, by open
After window region etches the most described 3rd trapping layer the 23, second trapping layer 21 and the first trapping layer 21 from top to bottom,
It is further continued for going deep into etch semiconductor substrates 20, to form first groove 241 He with one fixed width and the degree of depth
Second groove 242.Wherein, the layout of described first groove 241 and the second groove 242 can be according to product structure
And design, the width of described first groove 241 and the second groove 242 can be according to product structure and technological ability
Determining, the degree of depth can determine according to the parameter such as pressure of product.
Further, in the present embodiment, the first groove 241 of formation and the width of the second groove 242 are equal
Between 0.05 μm-5 μm, the degree of depth is all between 0.1 μm-50 μm.Concrete, for first window district 24a
In the first groove 241, its width L1 can according to product conducting density determine, minimum feature can be more than or equal to
The limit capacity of equipment, L1 can be 0.05 μm-1 μm；Degree of depth h1 can be come according to the parameter such as pressure of product
Determining, h1 can be 0.1-10 μm.For the second groove 242 in the second window region 24b, it is contemplated that its
To fill polysilicon in groove, width needs to meet carrying high pressure, the demand of big electric current, therefore wider width,
Also need on part-structure arrange fairlead on the interior polysilicon filled of groove later, therefore the second groove 242
Width L2 the relatively first groove 221 want width, L2 can be 0.5 μm-5 μm；In the case of wider width,
According to etching load effect, identical etch application is relatively deep to the big live width region etch degree of depth, therefore positive reason
H2 under condition > h1, h2 can be 0.1 μm-50 μm.It should be noted that can not be simply according to accompanying drawing
And draw the conclusion that the first groove 241 is consistent with the second groove 242 depth width.
It is also preferred that the left and then perform step S131, at a temperature of 1000 DEG C-1200 DEG C, aoxidize described quasiconductor lining
, the first groove 241 and the sidewall of the second groove 242 and diapire form the first oxide layer (in figure at the end 20
Not shown), so that described first groove 241 and the sidewall of the second groove 242 and diapire are repaired, institute
The thickness range stating the first oxide layer is
Then perform step S132, remove described first oxide layer, in the present embodiment, BOE can be used (slow
Rushing Fluohydric acid .) corrosive liquid or DHF (Fluohydric acid. of dilution) remove the first oxide layer；
Then, step S14 is performed, as it is shown in figure 5, in the present embodiment, in described Semiconductor substrate 20
Gate dielectric layer 25 is grown on described first groove 241 and the sidewall of the second groove 242 and diapire.Such as, institute
Stating gate dielectric layer 25 can be grid oxygen, concrete, and the employing of described gate dielectric layer 25 is mixed oxychloride and (i.e. contained
Chlorine, oxygen atmosphere under aoxidize) formed, be 1000 DEG C-1200 DEG C in temperature range and grow, to obtain
Obtaining thickness range isGate dielectric layer 25；The growth temperature of described gate dielectric layer 25 is the most high-quality
It is the best to measure, and mixes oxychloride and can effectively reduce the impurity in gate dielectric layer 25, improves the matter of gate dielectric layer 25
Amount.
Then, perform step S15, described first groove 241 and the second groove 242 are formed grid material
Layer 26, removes the 3rd trapping layer, and described gate material layers 26 has higher than described second trapping layer 22
Part.Refer to Fig. 6, such as, described gate material layers 26 can be doped polysilicon layer.Can first form sediment
The long-pending polysilicon that undopes, the polysilicon that undopes is doped by rear employing ion implanting；Or, first deposit not
DOPOS doped polycrystalline silicon, it is doped by rear employing phosphorus pre-deposited technique；Again or, use limit depositing polysilicon
The original position doping way of limit doping.
Concrete, in this step S15, to be deposited complete after, produce when also needing to remove deposit described the
Gate material layers 26 on three trapping layer surfaces, and make in described first groove 241 and the second groove 242
Gate material layers 26 flushes with described 3rd trapping layer surface, and this process can use has isotropic
Dry etching completes.Then use wet etching drift the 3rd trapping layer to the greatest extent, make described first groove 241 He
Gate material layers 26 in second groove 242 has the part higher than described second trapping layer 22, and it is high
Degree h3 is less than or equal to the thickness of the 3rd trapping layer in step S12.
Then, perform step S16, as it is shown in fig. 7, oxidation gate material layers 26 so that described grid material
The bed of material 26 produces the second oxide layer 27, and described second oxidation higher than a part for described second trapping layer 22
Layer 27 covering part the second trapping layer 22.Wet process oxidation technology can be used so that described gate material layers
26 produce the second oxide layer 27 higher than a part for described second trapping layer 22, concrete, described wet method oxygen
The temperature changed is 800 DEG C-1000 DEG C, and described second oxide layer 27 is silicon oxide layer, and thickness is
Afterwards, perform step S17, refer to Fig. 8, remove in described second trapping layer 22 not by the second oxygen
Change the part that layer 27 covers.Dry etching can be used, the second oxide layer 27 that will be formed in step S16
Unlapped second trapping layer 22 is most for quarter, exposes the first trapping layer 21.
And then, step S18, incorporated by reference to shown in Fig. 8, first ditch in described Semiconductor substrate 20 are performed
Groove 241 and the second groove 242 both sides form p-well 28a.Concrete, in described Semiconductor substrate 20 the
One groove 241 both sides and the second groove 242 both sides carry out ion implanting and annealing for the first time, form p-well 28a,
The junction depth degree of depth of described p-well 28a is less than the degree of depth of the first groove 241.Described first time ion implanting and moving back
Fire is for using boron (B) ion zero angle to inject, and Implantation Energy is 60KeV-150KeV, implantation dosage
1E13/cm2-1E15/cm2, annealing temperature is 1000 DEG C-1200 DEG C.
Afterwards, perform step S19, please continue to refer to shown in Fig. 8, in described Semiconductor substrate 20 first
N-type region 28b is formed in p-well 28a described in groove 241 and the second groove 242 both sides.Concrete, permissible
Be in described Semiconductor substrate 20 first groove 241 both sides and the second groove 242 both sides carry out second time from
Son injects and annealing, forms N-type region 28b, and junction depth degree of depth h4 of described N-type region 28b is 0.1 μm-0.5 μm.
Described second time ion implanting uses phosphorus (P) ion or arsenic (As) ion zero angle to inject with being annealed into, note
Entering energy is 60KeV-150Kev, implantation dosage 1E14/cm2-1E16/cm2, annealing temperature 800 DEG C-1100 DEG C.
From step S18 and the implantation dosage of step S19, the doping content of N-type region 28b of formation is more than P
The doping content of trap 28a, the most described N-type region 28b is N-type heavily doped region.
Afterwards, perform step S20, form blanket dielectric layer.Refer to Fig. 9, concrete, at the present embodiment
In, described blanket dielectric layer includes covering described first trapping layer the 21, second trapping layer 22 and the second oxide layer
The first medium layer 29a of 27 and cover second dielectric layer 29b of described first medium layer 29a.Described first is situated between
The material of matter layer 29a is plain silicon dioxide, silicon nitride, the one of silicon oxynitride or a combination thereof, adopts
Formed by techniques such as CVD.The thickness of described first medium layer 29a can beDescribed
The material of second medium layer 29b is BPSG (boron-phosphorosilicate glass), and thickness can beEqually
CVD technique can be used to be formed.Concrete, the reaction source gas of described second dielectric layer 29b includes SiH4、
B2H6And/or PH3Deng.Concrete, in described second dielectric layer 29b, the mass percent of B is 1～5%,
The mass percent of P is 2～6%.
Further, it is also possible to be described blanket dielectric layer only cover described Semiconductor substrate 20 first Jie
Matter layer 29a.
Further, if described first medium layer 29a uses silicon nitride, can be in follow-up contact hole system
Work utilizes the selection of first medium layer 29a, the 3rd dielectric layer 29b and silicon than difference, enable trench region
Protected, under the conditions of existing lithographic equipment, realized less live width and bigger alignment surplus further, from
And realize the production of the device architecture of less live width.
Afterwards, perform step S21, etch in described blanket dielectric layer extremely described Semiconductor substrate 20, formed
Contact hole 30, described contact hole 30 is positioned in the first groove 241 both sides and the second groove 242.Refer to figure
10, the contact hole 30 substantially inverted trapezoidal etched, i.e. shape with wide top and narrow bottom, the width bottom contact hole 30
For L5, open top width is L4, L5 < L4, thus the production intermediary of the device architecture of the less live width of realization
The filling of matter layer.Wherein, the sidewall of described contact hole 30 and the angle theta of diapire extended line are 80 °～89 °,
Described contact hole 30 is positioned at degree of depth h5 in described Semiconductor substrate 20 and is less than or equal to 1 μm.At contact hole 30
After formation, form the 3rd window region 30a in primitive unit cell district, form the 4th window region 30b in termination environment.
This step S21 is specially sequentially etched second dielectric layer 29b, first medium layer 29a and the first trapping layer
After 21, continue etch semiconductor substrates 20, it is thus achieved that the step of certain depth, thus N-type will be doping to
Semiconductor substrate etch away a part, make follow-up p-type inject and can penetrate N-type region.
Concrete, the region having contact hole 30 in described 3rd window region 30a is the source region between groove and groove,
Source as primitive unit cell district connects metal；Described 4th window region 30b has the region conduct of contact hole 30
The pressure ring of device or grid (Gate-PAD) end connect metal.
More specifically, in conjunction with Fig. 1, Fig. 3 and Figure 10, second dielectric layer 29b of primitive unit cell district shown in Figure 10 is pushed up
Portion's width is L3, and its width, more than the width L1 of the first groove 241 in Fig. 3, can make the first groove 241
Top protected by dielectric layer, it is not easy to produce the problem such as GS electric leakage.
More specifically, in primitive unit cell district shown in Figure 10, contact hole 30 open top width is L4, generally this
Width represents the contact hole 30 Limit Width under existing lithographic capabilities.
Then, perform step S22, please continue to refer to Figure 10, bottom described contact hole 30, form p type island region
30c.Concrete, carry out third time ion implanting and annealing, form described p type island region 30c.Described third time
Ion implanting injects B11 or BF for using zero angle2, can first inject B11 and reinject BF2, inject energy
Amount is 20KeV-100KeV, and implantation dosage is 1E14/cm2-1E16/cm2；Boiler tube or short annealing is used to exist
Anneal at 500 DEG C-1000 DEG C.From step S18 and the implantation dosage of step S22, the P of formation
The doping content of type district 30c is more than the doping content of p-well 28a, and the most described p type island region 30c is p-type
Heavily doped region.
Then, perform step S23, refer to Figure 11, described second dielectric layer 29b is formed metal level
31, described metal level 31 fills described contact hole.Concrete, the material of described metal level 31 can be titanium
(Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), silicated aluminum (AlSi), copper
Metal or the compounds of metal such as silico-aluminum (AlSiCu), copper (Cu) or nickel (Ni), its thickness is permissible
It it is 1 μm-8 μm.After metal level 31 is formed, perform a step etching technics, for example with dry etching, obtain
Obtain the 5th window region 31a and the 6th window region 31b of termination environment in primitive unit cell district.
Further, it is also possible to protect according to the increase passivation layer that needs of product, complete device Facad structure
Processing, and complete final device architecture through a series of postchannel process such as thinning, the back of the body gold, scribings.
Visible in conjunction with Fig. 3-Figure 11, that the present embodiment obtains grooved gate power device, including:
Semiconductor substrate 20；
The first trapping layer 21 being positioned in described Semiconductor substrate 20；
It is positioned at the second trapping layer 22 on described first trapping layer 21；It is also preferred that the left described first trapping layer 21
Thickness beThe thickness of described second trapping layer 22 isDescribed first resistance
Only the material of layer 21 and the second trapping layer 22 be silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon
Plant or combination；
Run through described second trapping layer the 22, first trapping layer 21 and extend in described Semiconductor substrate 20
First groove 241 and the second groove 242, it is also preferred that the left the width of described first groove 241 is 0.05 μm-1 μm,
The degree of depth is 0.1 μm-10 μm；The width of described second groove 242 is 0.5 μm-5 μm, and the degree of depth is
0.1μm-50μm；
It is positioned at the first groove 241 described in described Semiconductor substrate 20 and the sidewall of the second groove 242 and diapire
On gate dielectric layer 25；The thickness of described gate dielectric layer 25 is
It is positioned at the gate material layers 26 in described first groove 241 and the second groove 242；
It is positioned at the second oxide layer 27 in described second trapping layer 22 and described gate material layers 26, it is also preferred that the left
Described second oxidated layer thickness is
It is positioned at the first groove 241 and p-well 28a of the second groove 242 both sides in described Semiconductor substrate 20；
It is positioned at p-well 28a described in the first groove 241 and the second groove 242 both sides in described Semiconductor substrate 20
On N-type region 28b；The junction depth degree of depth of described N-type region 28b is less than the degree of depth of described p-well 28a, such as,
The junction depth degree of depth of described N-type region 28b is 0.1 μm-0.5 μm；
Being positioned at the blanket dielectric layer in described Semiconductor substrate 20, described blanket dielectric layer includes covering described
One trapping layer the 21, second trapping layer 22 and the first medium layer 29a of the second oxide layer 27 and cover described
Second dielectric layer 29b of one dielectric layer 29a；The material of described first medium layer 29a is plain titanium dioxide
Silicon, silicon nitride, the one of silicon oxynitride or a combination thereof, the material of described second dielectric layer 29b is boron phosphorus silicon
Glass, in described second dielectric layer 29b, the mass percent of boron is 1～5%, and the mass percent of phosphorus is 2～6%,
It is also preferred that the left the thickness of described first medium layer 29a isThe thickness of described second dielectric layer 29b
Degree isCertainly, described blanket dielectric layer can also be only second dielectric layer 29a；
Contact hole 30, described contact hole 30 be positioned at described first groove 241 both sides run through described blanket dielectric layer,
First trapping layer 21 also extends in described Semiconductor substrate 20, and is positioned in described second groove 242
Run through described blanket dielectric layer, the second oxide layer 27 and extend in described gate material layers 26, it is also preferred that the left
The described sidewall of contact hole 30 and the extended line of diapire are 80 ° of-89 ° of angles, and described contact hole 30 is positioned at described
The degree of depth in Semiconductor substrate 20 is less than or equal to 1 μm；
It is positioned at the p type island region 30c bottom described contact hole 30；
The metal level 31 being positioned in described blanket dielectric layer, described metal level 31 fills described contact hole 30；
It is also preferred that the left the material of described metal level 31 is titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten
(W), aluminum (Al), silicated aluminum (AlSi), copper silmin (AlSiCu), copper (Cu) or nickel (Ni)
Deng metal or the compound of metal；And
It is positioned at the passivation layer on described metal level 31.
Thus, a kind of grooved gate power device of present invention offer and manufacture method, by providing Semiconductor substrate；
Sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；Etching institute
State the Semiconductor substrate of the 3rd trapping layer, the second trapping layer, the first trapping layer and segment thickness to form
One groove and the second groove；The first groove and the sidewall of the second groove and the end described in described Semiconductor substrate
Gate dielectric layer is grown on wall；In described first groove and the second groove, form gate material layers, remove the 3rd
Trapping layer, described gate material layers has the part higher than described second trapping layer；Oxidation gate material layers,
Described gate material layers is made to produce the second oxide layer, and described the higher than a part for described second trapping layer
Dioxide layer covering part the second trapping layer；Remove in described second trapping layer not by the second oxide layer covering
Part；In described Semiconductor substrate, the first groove and the second groove both sides form p-well；At described quasiconductor
Substrate is formed in p-well described in the first groove and the second groove both sides N-type region；On the semiconductor substrate
Form blanket dielectric layer；Etch in described blanket dielectric layer extremely described Semiconductor substrate, form contact hole, institute
State contact hole to be positioned in the first groove both sides and the second groove；And bottom described contact hole, form p type island region.
So that whole slot grid structure is protected, make slot grid structure in processing technique under the conditions of existing lithographic equipment
In do not affected by contact hole instability technique, it is achieved less live width and the life of bigger alignment surplus product
Produce, make the parameter of product and reliability meet requirement.
It should be noted that the grooved gate power device structure of the present invention and manufacture method can be used in include but
It is not limited in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (28)
1. a manufacture method for grooved gate power device, including:
Semiconductor substrate is provided；
Sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Etch the quasiconductor lining of described 3rd trapping layer, the second trapping layer, the first trapping layer and segment thickness
The end, is to form the first groove and the second groove；
Grid dielectric is grown on first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate
Layer；
In described first groove and the second groove, form gate material layers, remove the 3rd trapping layer, described grid
Pole material layer has the part higher than described second trapping layer；
Oxidation gate material layers so that described gate material layers is higher than the part generation of described second trapping layer
Second oxide layer, and described second oxide layer covering part the second trapping layer；
Remove the part not covered by the second oxide layer in described second trapping layer；
In described Semiconductor substrate, the first groove and the second groove both sides form p-well；
N-type region is formed in p-well described in first groove and the second groove both sides in described Semiconductor substrate；
Form blanket dielectric layer on the semiconductor substrate；
Etching in described blanket dielectric layer extremely described Semiconductor substrate, form contact hole, described contact hole is positioned at
In first groove both sides and the second groove；And
P type island region is formed bottom described contact hole.
2. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that described first
The material of trapping layer, the second trapping layer and the 3rd trapping layer is silicon dioxide, silicon nitride, silicon oxynitride, many
The one of crystal silicon or combination.
3. the manufacture method of grooved gate power device as claimed in claim 1 or 2, it is characterised in that described
The thickness of the first trapping layer isThe thickness of described second trapping layer isDescribed
The thickness of the 3rd trapping layer is
4. the manufacture method of grooved gate power device as claimed in claim 3, it is characterised in that described first
The width of groove is 0.05 μm-1 μm, and the degree of depth is 0.1 μm-10 μm；The width of described second groove is
0.5 μm-5 μm, the degree of depth is 0.1 μm-50 μm.
5. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that forming the
After one groove and the second groove, before growth gate dielectric layer, also include:
Described in described Semiconductor substrate, the first groove and the sidewall of the second groove and diapire form the first oxidation
Layer；
Remove described first oxide layer.
6. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that described the
After one groove and the second groove form gate material layers, before removing the 3rd trapping layer, also include:
Produce the gate material layers on described 3rd trapping layer surface when removing deposit, make described grid material
The upper surface of layer and the upper surface flush of described 3rd trapping layer.
7. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that use wet method
Oxidation technology forms described second oxide layer.
8. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that described second
Oxidated layer thickness is
9. the manufacture method of grooved gate power device as claimed in claim 1, it is characterised in that described covering
Dielectric layer includes the first medium layer covering described Semiconductor substrate.
10. the manufacture method of grooved gate power device as claimed in claim 9, it is characterised in that described in cover
Lid dielectric layer also includes the second dielectric layer covering described first medium layer.
The manufacture method of 11. grooved gate power devices as claimed in claim 10, it is characterised in that described
The material of one dielectric layer is one or more combinations of plain silicon dioxide, silicon nitride, silicon oxynitride；
The material of described second dielectric layer is boron-phosphorosilicate glass.
The manufacture method of 12. grooved gate power devices as claimed in claim 10, it is characterised in that described
One dielectric layer and second dielectric layer are all formed by chemical vapor deposition method.
The manufacture method of 13. grooved gate power devices as claimed in claim 12, it is characterised in that form institute
The reaction source gas stating second dielectric layer includes SiH4、B2H6And/or PH3；The matter of boron in described second dielectric layer
Amount percentage ratio is 1～5%, and the mass percent of phosphorus is 2～6%.
The manufacture method of 14. grooved gate power devices as claimed in claim 10, it is characterised in that described
The thickness of one dielectric layer isThe thickness of described second dielectric layer is
The manufacture method of 15. grooved gate power devices as claimed in claim 1, it is characterised in that described in connect
The sidewall of contact hole and the extended line of diapire are 80 ° of-89 ° of angles, and the degree of depth of described contact hole is less than or equal to 1 μm.
The manufacture method of 16. grooved gate power devices as claimed in claim 1, it is characterised in that described
After forming p type island region bottom contact hole, also include:
Forming metal level in described blanket dielectric layer, described metal level fills described contact hole；And
Described metal level is formed passivation layer.
17. 1 kinds of grooved gate power devices, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove extending in described Semiconductor substrate
With the second groove；
It is positioned at the grid dielectric of the first groove and the sidewall of the second groove and diapire described in described Semiconductor substrate
Layer；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides and runs through described blanket dielectric layer, the first resistance
Only layer extending in described Semiconductor substrate, and be positioned in described second groove and run through described overwrite media
Layer, the second oxide layer also extend in described gate material layers；
It is positioned at the p type island region bottom described contact hole.
18. grooved gate power devices as claimed in claim 17, it is characterised in that described first trapping layer and
The material of the second trapping layer is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination.
19. grooved gate power devices as described in claim 17 or 18, it is characterised in that described first resistance
Only the thickness of layer isThe thickness of described second trapping layer is
20. grooved gate power devices as claimed in claim 17, it is characterised in that the width of described first groove
Degree is 0.05 μm-1 μm, and the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, deeply
Degree is 0.1 μm-50 μm.
21. grooved gate power devices as claimed in claim 17, it is characterised in that described second oxide layer
Thickness is
22. grooved gate power devices as claimed in claim 17, it is characterised in that described blanket dielectric layer bag
Include the first medium layer covering described Semiconductor substrate.
23. grooved gate power devices as claimed in claim 22, it is characterised in that described blanket dielectric layer is also
Including the second dielectric layer covering described first medium layer.
24. grooved gate power devices as claimed in claim 23, it is characterised in that described first medium layer
Material is one or more combinations of plain silicon dioxide, silicon nitride, silicon oxynitride；Described second is situated between
The material of matter layer is boron-phosphorosilicate glass.
25. grooved gate power devices as claimed in claim 24, it is characterised in that in described second dielectric layer
The mass percent of boron is 1～5%, and the mass percent of phosphorus is 2～6%.
26. grooved gate power devices as claimed in claim 23, it is characterised in that described first medium layer
Thickness isThe thickness of described second dielectric layer is
27. grooved gate power devices as claimed in claim 17, it is characterised in that the sidewall of described contact hole
Being 80 ° of-89 ° of angles with the extended line of diapire, the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than
Equal to 1 μm.
28. grooved gate power devices as claimed in claim 17, it is characterised in that also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
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