CN205863138U - Grooved gate power device - Google Patents
Grooved gate power device Download PDFInfo
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- CN205863138U CN205863138U CN201620738729.3U CN201620738729U CN205863138U CN 205863138 U CN205863138 U CN 205863138U CN 201620738729 U CN201620738729 U CN 201620738729U CN 205863138 U CN205863138 U CN 205863138U
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Abstract
This utility model discloses a kind of grooved gate power device.A kind of grooved gate power device that this utility model provides; by the described gate material layers in groove being had higher than a part for the second trapping layer and this partial oxidation being formed the second oxide layer; and described second oxide layer covering part the second trapping layer; so that whole slot grid structure is protected; slot grid structure is made not affected by contact hole instability technique in processing technique under the conditions of existing lithographic equipment; realize less live width and the production of bigger alignment surplus product, make the parameter of product and reliability meet requirement.
Description
Technical field
This utility model relates to field of semiconductor devices, particularly relates to a kind of grooved gate power device.
Background technology
Power device can be divided into Power IC (integrated circuit) device and power discrete device two class, and power discrete device wraps again
(insulated gate bipolar is brilliant to include power MOSFET (Metal-Oxide Semiconductor field-effect transistor), high power transistor and IGBT
Body pipe) etc. device.Power device is all based on planar technology and produces in early days, but along with the development of semiconductor technology, small size, big
Power, high-performance become main development trend.As a example by planar technology MOSFET element, due to itself internal JFET
The restriction of (junction field effect transistor) dead resistance, the area of single primitive unit cell reduces limited, thus makes increase primitive unit cell density
Become highly difficult, be difficult to make the conducting resistance (RDSON) of planar technology MOSFET to reduce further.Trench process is due to by raceway groove
Become vertical from level, eliminate the impact of planar structure parasitism JFET resistance, make cellular size be substantially reduced, on this basis
Primitive unit cell density can be increased, the overall width of raceway groove in raising unit are chip, it is possible to make device ditch on unit silicon chip
Road breadth length ratio increases so that electric current increases, conducting resistance declines and relevant parameter is optimized, it is achieved that smaller size of
Tube core has greater power and high performance target, and therefore trench process is more and more applies in New Type Power Devices.
Along with the development of semiconductor technology, persistently diminish to realize lower cost advantage and minimum feature, existing
In typical groove power device, the live width of groove and contact hole diminishes, and Pitch (pitch) width compresses simultaneously so that contact hole
With the spacing between gate trench narrows, if now the live width of contact hole is not accomplished sufficiently small, inclined precision cannot be met remaining
Amount requirement, and then occur the technological problems such as partially, it will the structure directly resulting in device is difficult to, and then causes Vth (threshold value
Voltage), the abnormal parameters such as BVds (drain-source breakdown voltage), Rdson even GS short circuit (grid source short circuit), form security risk.
Fig. 1 show MOSFET easy appearance under lithographic equipment limit capacity in groove power device in prior art
Problem schematic diagram.Wherein, what a-quadrant represented is the normal pattern of contact hole 4, and now contact hole 4 is in Semiconductor substrate 1 surface shape
The live width become is d1, and the spacing of the groove 5 that contact hole 4 is adjacent is respectively a1 and a2.When the width of d1 is at lithographic equipment
Time in limit of power, its contact hole 4 does not haves under-exposure, the resolution topography issues caused such as the best.When equipment alignment
Ability preferably in the case of, a1 and a2 all can meet product design to inclined margin range, a1-a2 is the smaller the better, works as a1-a2
When=0, illustrating that alignment precision is optimal, alignment ability is optimal.
B Regional Representative's is when the lithographic line width of contact hole 4 by the design of equipment limit capacity but still is unsatisfactory for predetermined
Live width design requirement, finally makes contact hole 4 will contact when having contacted upper with the grid oxygen 3 in groove 5, polysilicon 2
Abnormal pattern.The live width that now contact hole 4 is formed on Semiconductor substrate 1 surface is d2, the groove 5 that contact hole 4 is adjacent
Spacing is respectively b1 and b2.When b1 and b2 is respectively less than the pitch requirements that product allows, it may appear that Vth, BVds, Rdson etc. join
Number is abnormal, there is security risk.When b1 and b2 the most infinitely small even negative time, contact hole 4 with in groove 5
Grid oxygen 3, polysilicon 2 contact, it may appear that the abnormal parameters such as GS short circuit.This is that typical live width is bigger than normal, capacity of equipment can not meet
The failure conditions of product smaller szie processing.
C Regional Representative's is when the lithographic line width of contact hole 4 meets little linewidth requirements, but lithographic equipment alignment ability can not
Meet product structure requirement, finally make contact hole 4 not cause the structure and morphology of abnormal parameters in the centre of left and right groove 5.Now
The live width that contact hole 4 is formed on Semiconductor substrate 1 surface is d3, the spacing of the groove 5 that contact hole 4 is adjacent be respectively c1 and
C2, wherein, c1 much larger than product design to inclined margin range, c2 is again less than even the contacting inclined margin range of product design
Grid oxygen 3 in hole 4 infinite approach groove 5, polysilicon 2, the most easily occur that the parameters such as Vth, BVds, Rdson even GS short circuit are different
Often.This is that normally but alignment precision can not meet the smaller size of failure conditions of product to typical lithographic equipment live width ability.As
Fruit is in C region, c1 and c2 all then can avoid various inefficacy in product design in the range of partially.
Therefore, how under the conditions of existing lithographic equipment, less live width is realized, it is ensured that the spacing of contact hole to slot grid structure,
So that contact hole and groove set are carved with enough surpluses, thus realize the production of the device architecture of less live width, make product simultaneously
Parameter and the reliability of product meet requirement, are the contents that those skilled in the art is to be studied.
Utility model content
The purpose of this utility model is to provide a kind of grooved gate power device, protects slot grid structure, at existing lithographic equipment
Under the conditions of make slot grid structure not affected by contact hole instability technique in processing technique, it is achieved less live width and bigger
The production of alignment surplus product, makes the parameter of product and reliability meet requirement.
For solving above-mentioned technical problem, this utility model provides a kind of grooved gate power device, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove and second extending in described Semiconductor substrate
Groove；
It is positioned at described first groove and the sidewall of the second groove and the gate dielectric layer of diapire；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides and runs through described blanket dielectric layer, the first trapping layer also
Extend in described Semiconductor substrate, and be positioned in described second groove and run through described blanket dielectric layer, the second oxide layer also
Extend in described gate material layers.
Optionally, for described grooved gate power device, described first trapping layer and the second trapping layer are silicon dioxide resistance
Only layer, silicon nitride trapping layer, silicon oxynitride trapping layer, the one of polysilicon trapping layer or combination.
Optionally, for described grooved gate power device, the thickness of described first trapping layer isDescribed
The thickness of the second trapping layer is
Optionally, for described grooved gate power device, the width of described first groove is 0.05 μm-1 μm, and the degree of depth is
0.1μm-10μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
Optionally, for described grooved gate power device, the thickness of described second oxide layer is
Optionally, for described grooved gate power device, described blanket dielectric layer includes covering described Semiconductor substrate
First medium layer.
Optionally, for described grooved gate power device, described blanket dielectric layer also includes covering described first medium layer
Second dielectric layer.
Optionally, for described grooved gate power device, described first medium layer be plain silica dioxide medium layer,
Silicon nitride medium layer, one or more combinations of silicon oxynitride dielectric layer；Described second dielectric layer is boron-phosphorosilicate glass dielectric layer.
Optionally, for described grooved gate power device, in described second dielectric layer, the mass percent of boron is 1～5%,
The mass percent of phosphorus is 2～6%.
Optionally, for described grooved gate power device, the thickness of described first medium layer isDescribed
The thickness of second dielectric layer is
Optionally, for described grooved gate power device, the sidewall of described contact hole and the extended line of diapire are 80 °-89 °
Angle, the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than or equal to 1 μm.
Optionally, for described grooved gate power device, also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
Compared with prior art, a kind of grooved gate power device that this utility model provides, by by the described grid in groove
Pole material layer has higher than a part for the second trapping layer and this partial oxidation is formed the second oxide layer, and described second oxygen
Change layer covering part the second trapping layer, so that whole slot grid structure is protected, under the conditions of existing lithographic equipment, make groove grid
Structure is not affected by contact hole instability technique in processing technique, it is achieved less live width and bigger alignment surplus product
Production, make the parameter of product and reliability meet requirement.
Accompanying drawing explanation
Fig. 1 is MOSFET easy produced problem under lithographic equipment limit capacity in groove power device in prior art
Schematic diagram；
Fig. 2 is the flow chart of the grooved gate power device manufacture method in this utility model one embodiment；
Fig. 3-11 is the structural representation in the manufacturing process of the grooved gate power device in this utility model one embodiment.
Detailed description of the invention
Below in conjunction with schematic diagram, grooved gate power device of the present utility model and manufacture method are described in more detail,
Which show preferred embodiment of the present utility model, it should be appreciated that those skilled in the art can revise described here reality
With novel, and still realize advantageous effects of the present utility model.Therefore, description below is appreciated that for art technology
Personnel's is widely known, and is not intended as restriction of the present utility model.
Referring to the drawings this utility model the most more particularly described below in the following passage.According to following explanation and power
Profit claim, advantage of the present utility model and feature will be apparent from.It should be noted that, accompanying drawing all use the form simplified very much and
All use non-ratio accurately, only in order to purpose convenient, aid illustration this utility model embodiment lucidly.
This utility model provides a kind of grooved gate power device and manufacture method, the manufacture method bag of described grooved gate power device
Include:
Step S11, offer Semiconductor substrate；
Step S12, sequentially form the first trapping layer, the second trapping layer and the 3rd trapping layer on the semiconductor substrate；
Step S13, etch described 3rd trapping layer, the second trapping layer, the first trapping layer and the quasiconductor of segment thickness
Substrate is to form the first groove and the second groove；
Step S14, described in described Semiconductor substrate, grow grid on the first groove and the sidewall of the second groove and diapire
Dielectric layer；
Step S15, the gate material layers that formed in described first groove and the second groove, removal the 3rd trapping layer, described
Gate material layers has the part higher than described second trapping layer；
Step S16, oxidation gate material layers so that described gate material layers is higher than the part product of described second trapping layer
Raw second oxide layer, and described second oxide layer covering part the second trapping layer；
Step S17, remove in described second trapping layer the part not covered by the second oxide layer；
Step S18, in described Semiconductor substrate, the first groove and the second groove both sides form p-well；
Step S19, in described Semiconductor substrate, in p-well described in the first groove and the second groove both sides, form N-type region；
Step S20, form blanket dielectric layer on the semiconductor substrate；
Step S21, etch described blanket dielectric layer in described Semiconductor substrate, form contact hole, described contact hole position
In the first groove both sides and the second groove；And
Step S22, bottom described contact hole formed p type island region.
Incorporated by reference to Fig. 2 and Fig. 3-11, grooved gate power device of the present utility model and manufacture method are situated between in detail below
Continue.
First, step S11 is performed, as shown in Figure 3, it is provided that Semiconductor substrate 20.Preferably, described Semiconductor substrate 20 can
To be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or to well known to a person skilled in the art other semi-conducting materials
Substrate, uses silicon substrate in the present embodiment.Further, the silicon substrate used in the present embodiment could be formed with MOSFET
The quasiconductor such as (mos field effect transistor), IGBT (isolated-gate field effect transistor (IGFET)), Schottky diode
Device.Described Semiconductor substrate 20 can also carry out N-type and the p-type doping of certain impurity level according to the characteristic of required product.
Then, perform step S12, with continued reference to shown in Fig. 3, described Semiconductor substrate 20 sequentially forms the first prevention
Layer the 21, second trapping layer 22 and the 3rd trapping layer 23.Described the first trapping layer 21, second formed in Semiconductor substrate 20 hinders
Only layer 22 and the 3rd trapping layer 23 can use the means such as oxidation or deposit to be formed.Such as, described first trapping layer 21, second stops
The material of layer 22 and the 3rd trapping layer 23 can be one or more groups of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon etc.
Close.It is also preferred that the left the thickness of described first trapping layer isThe thickness of described second trapping layer isThe thickness of described 3rd trapping layer is
Then, perform step S13, etch the 3rd trapping layer the 23, second trapping layer the 22, first trapping layer 21 and segment thickness
Semiconductor substrate 20, i.e. etch described 3rd trapping layer 23 in described Semiconductor substrate 20 to form the first groove 241 He
Second groove 242.Refer to Fig. 4, the first groove 241 region is first window district 24a, the second groove 242 region
It is the second window region 24b.Described first window district 24a refers to the primitive unit cell district of power device, and the second window region 24b refers to merit
The termination environment of rate device.
In step s 13, by the selectively opened window of photoetching, use photoresist to shelter, by the window region opened from
On down after etching to the greatest extent described 3rd trapping layer the 23, second trapping layer 21 and the first trapping layer 21, be further continued for deep etching and partly lead
Body substrate 20, to form first groove 241 and second groove 242 with one fixed width and the degree of depth.Wherein, described first groove
241 and second the layout of groove 242 can design according to product structure, described first groove 241 and the width of the second groove 242
Can determine according to product structure and technological ability, the degree of depth can determine according to the parameter such as pressure of product.
Further, in the present embodiment, the width of the first groove 241 of formation and the second groove 242 all 0.05 μm-
Between 5 μm, the degree of depth is all between 0.1 μm-50 μm.Concrete, for the first groove 241 in first window district 24a, its width
L1 can determine according to product conducting density, and minimum feature can be more than or equal to the limit capacity of equipment, and L1 can be 0.05 μm-1 μm；
Degree of depth h1 can determine according to the parameter such as pressure of product, and h1 can be 0.1-10 μm.For second in the second window region 24b
Groove 242, it is contemplated that will fill polysilicon in its groove, width needs to meet carrying high pressure, the demand of big electric current, and therefore width is relatively
Width, part-structure also needs to arrange fairlead on the interior polysilicon filled of groove later, the therefore width L2 of the second groove 242
Relatively first groove 221 wants width, and L2 can be 0.5 μm-5 μm；In the case of wider width, according to etching load effect, identical
Etch application relatively deep to the big live width region etch degree of depth, h2 the most under normal circumstances > h1, h2 can be 0.1 μm-50 μm.Need
It is noted that and simply can not show that the first groove 241 is consistent with the second groove 242 depth width according to accompanying drawing
Conclusion.
It is also preferred that the left and then perform step S131, aoxidize at a temperature of 1000 DEG C-1200 DEG C in described Semiconductor substrate 20
Described first groove 241 and the sidewall of the second groove 242 and diapire form the first oxide layer (not shown), with to described
One groove 241 and the sidewall of the second groove 242 and diapire are repaired, and the thickness range of described first oxide layer is
Then perform step S132, remove described first oxide layer, in the present embodiment, BOE (buffering hydrogen fluorine can be used
Acid) corrosive liquid or DHF (Fluohydric acid. of dilution) remove the first oxide layer；
Then, step S14 is performed, as it is shown in figure 5, in the present embodiment, first ditch described in described Semiconductor substrate 20
Gate dielectric layer 25 is grown on groove 241 and the sidewall of the second groove 242 and diapire.Such as, described gate dielectric layer 25 can be grid oxygen,
Concrete, described gate dielectric layer 25 uses mixes oxychloride (i.e. contain and aoxidize under the atmosphere of chlorine, oxygen) formation, in temperature range
It is 1000 DEG C-1200 DEG C to grow, obtaining thickness range isGate dielectric layer 25；Described gate dielectric layer
The growth temperature of 25 more high-quality is the best, mixes oxychloride and can effectively reduce the impurity in gate dielectric layer 25, improves gate dielectric layer
The quality of 25.
Then, perform step S15, described first groove 241 and the second groove 242 are formed gate material layers 26, goes
Except the 3rd trapping layer, described gate material layers 26 has the part higher than described second trapping layer 22.Refer to Fig. 6, such as,
Described gate material layers 26 can be doped polysilicon layer.Can first deposit the polysilicon that undopes, rear employing ion implanting is not to
DOPOS doped polycrystalline silicon is doped；Or, first depositing the polysilicon that undopes, it is doped by rear employing phosphorus pre-deposited technique；Again
Or, use the original position doping way of depositing polysilicon limit, limit doping.
Concrete, in this step S15, to be deposited complete after, produce at described 3rd trapping layer when also needing to remove deposit
Gate material layers 26 on surface, and make gate material layers in described first groove 241 and the second groove 242 26 and described the
Three trapping layer surfaces flush, and this process can use the dry etching with isotropic to complete.Then wet method is used to carve
Erosion drift to the greatest extent the 3rd trapping layer, makes the gate material layers 26 in described first groove 241 and the second groove 242 have higher than described the
A part for two trapping layers 22, its height h3 is less than or equal to the thickness of the 3rd trapping layer in step S12.
Then, perform step S16, as it is shown in fig. 7, oxidation gate material layers 26 so that described gate material layers 26 is higher than
A part for described second trapping layer 22 produces the second oxide layer 27, and described second oxide layer 27 covering part the second trapping layer
22.Wet process oxidation technology can be used so that described gate material layers 26 is higher than the part generation of described second trapping layer 22
Second oxide layer 27, concrete, the temperature of described wet oxidation is 800 DEG C-1000 DEG C, and described second oxide layer 27 is silicon oxide
Layer, thickness is
Afterwards, perform step S17, refer to Fig. 8, remove in described second trapping layer 22 and do not covered by the second oxide layer 27
Part.Dry etching can be used, the second oxide layer 27 unlapped second trapping layer 22 quarter that will be formed in step S16
To the greatest extent, the first trapping layer 21 is exposed.
And then, perform step S18, incorporated by reference to shown in Fig. 8, first groove 241 and the in described Semiconductor substrate 20
Two groove 242 both sides form p-well 28a.Concrete, first groove 241 both sides and the second groove in described Semiconductor substrate 20
242 both sides carry out ion implanting and annealing for the first time, form p-well 28a, and the junction depth degree of depth of described p-well 28a is less than the first groove
The degree of depth of 241.Described first time ion implanting is injected with being annealed into employing boron (B) ion zero angle, and Implantation Energy is 60KeV-
150KeV, implantation dosage 1E13/cm2-1E15/cm2, annealing temperature is 1000 DEG C-1200 DEG C.
Afterwards, step S19, please continue to refer to shown in Fig. 8, first groove 241 He in described Semiconductor substrate 20 are performed
N-type region 28b is formed in p-well 28a described in second groove 242 both sides.Concrete, can be in described Semiconductor substrate 20 first
Groove 241 both sides and the second groove 242 both sides carry out second time ion implanting and annealing, form N-type region 28b, described N-type region
Junction depth degree of depth h4 of 28b is 0.1 μm-0.5 μm.Described second time ion implanting uses phosphorus (P) ion or arsenic (As) with being annealed into
Ion zero angle is injected, and Implantation Energy is 60KeV-150Kev, implantation dosage 1E14/cm2-1E16/cm2, annealing temperature 800 DEG C-
1100℃.From step S18 and the implantation dosage of step S19, the doping content of N-type region 28b of formation is more than p-well 28a
Doping content, the most described N-type region 28b is N-type heavily doped region.
Afterwards, perform step S20, form blanket dielectric layer.Refer to Fig. 9, concrete, in the present embodiment, described in cover
Lid dielectric layer include covering described first trapping layer the 21, second trapping layer 22 and the first medium layer 29a of the second oxide layer 27 and
Cover second dielectric layer 29b of described first medium layer 29a.The material of described first medium layer 29a is plain titanium dioxide
Silicon, silicon nitride, the one of silicon oxynitride or a combination thereof, use the techniques such as CVD to be formed.The thickness of described first medium layer 29a can
ThinkThe material of described second dielectric layer 29b is BPSG (boron-phosphorosilicate glass), and thickness can beCVD technique is equally used to be formed.Concrete, the reaction source gas bag of described second dielectric layer 29b
Include SiH4、B2H6And/or PH3Deng.Concrete, in described second dielectric layer 29b, the mass percent of B is 1～5%, the matter of P
Amount percentage ratio is 2～6%.
Further, it is also possible to be the described blanket dielectric layer first medium layer that only covers described Semiconductor substrate 20
29a。
Further, if described first medium layer 29a uses silicon nitride, can utilize in follow-up contact hole makes
The selection of first medium layer 29a, the 3rd dielectric layer 29b and silicon, than difference, enables trench region to be protected, further existing
Realize less live width and bigger alignment surplus under the conditions of having lithographic equipment, thus realize the life of the device architecture of less live width
Produce.
Afterwards, perform step S21, etch in described blanket dielectric layer extremely described Semiconductor substrate 20, form contact hole 30,
Described contact hole 30 is positioned in the first groove 241 both sides and the second groove 242.Refer to Figure 10, the contact hole 30 etched is big
Causing to be inverted trapezoidal, i.e. shape with wide top and narrow bottom, the width bottom contact hole 30 is L5, and open top width is L4, L5 < L4, thus real
The filling producing dielectric layer of the device architecture of the least live width.Wherein, the sidewall of described contact hole 30 and diapire extended line
Angle theta be 80 °～89 °, described contact hole 30 is positioned in described Semiconductor substrate 20 degree of depth h5 less than or equal to 1 μm.In contact
After hole 30 is formed, form the 3rd window region 30a in primitive unit cell district, form the 4th window region 30b in termination environment.
After this step S21 is specially sequentially etched second dielectric layer 29b, first medium layer 29a and the first trapping layer 21, continue
Continuous etch semiconductor substrates 20, it is thus achieved that the step of certain depth, thus the Semiconductor substrate being doping to N-type is etched away one
Part, makes follow-up p-type inject and can penetrate N-type region.
Concrete, the region having contact hole 30 in described 3rd window region 30a is the source region between groove and groove, as primitive unit cell
The source in district connects metal；Described 4th window region 30b has the region of contact hole 30 as the pressure ring of device or grid
(Gate-PAD) end connects metal.
More specifically, in conjunction with Fig. 1, Fig. 3 and Figure 10, the second dielectric layer 29b top width of primitive unit cell district shown in Figure 10 is L3,
Its width, more than the width L1 of the first groove 241 in Fig. 3, can make the top of the first groove 241 be protected by dielectric layer, no
Easily produce the problems such as GS electric leakage.
More specifically, in primitive unit cell district shown in Figure 10, contact hole 30 open top width is L4, and generally this width represents
The contact hole 30 Limit Width under existing lithographic capabilities.
Then, perform step S22, please continue to refer to Figure 10, bottom described contact hole 30, form p type island region 30c.Specifically
, carry out third time ion implanting and annealing, form described p type island region 30c.Described third time ion implanting is for using zero degree subscript
Enter B11 or BF2, can first inject B11 and reinject BF2, Implantation Energy is 20KeV-100KeV, and implantation dosage is 1E14/cm2-
1E16/cm2；Boiler tube or short annealing is used to anneal at 500 DEG C-1000 DEG C.By step S18 and the injection of step S22
Dosage understands, and the doping content of the p type island region 30c of formation is more than the doping content of p-well 28a, and the most described p type island region 30c is p-type
Heavily doped region.
Then, perform step S23, refer to Figure 11, described second dielectric layer 29b is formed metal level 31, described gold
Belong to layer 31 and fill described contact hole.Concrete, the material of described metal level 31 can be titanium (Ti), titanium nitride (TiN), titanium silicide
(TiSi), metal or the gold such as tungsten (W), aluminum (Al), silicated aluminum (AlSi), copper silmin (AlSiCu), copper (Cu) or nickel (Ni)
The compound belonged to, its thickness can be 1 μm-8 μm.After metal level 31 is formed, perform a step etching technics, for example with dry method
Etching, it is thus achieved that the 5th window region 31a and the 6th window region 31b of termination environment in primitive unit cell district.
Further, it is also possible to according to product need increase passivation layer protection, complete the processing of device Facad structure, and
Final device architecture is completed through a series of postchannel process such as thinning, the back of the body gold, scribings.
Visible in conjunction with Fig. 3-Figure 11, that the present embodiment obtains grooved gate power device, including:
Semiconductor substrate 20；
The first trapping layer 21 being positioned in described Semiconductor substrate 20；
It is positioned at the second trapping layer 22 on described first trapping layer 21；It is also preferred that the left the thickness of described first trapping layer 21 isThe thickness of described second trapping layer 22 isDescribed first trapping layer 21 and the second trapping layer
The material of 22 is silicon dioxide, silicon nitride, silicon oxynitride, the one of polysilicon or combination；
Run through described second trapping layer the 22, first trapping layer 21 and extend to the first groove in described Semiconductor substrate 20
241 and second groove 242, it is also preferred that the left the width of described first groove 241 is 0.05 μm-1 μm, the degree of depth is 0.1 μm-10 μm；Institute
The width stating the second groove 242 is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm；
It is positioned at the grid on the first groove 241 described in described Semiconductor substrate 20 and the sidewall of the second groove 242 and diapire
Dielectric layer 25；The thickness of described gate dielectric layer 25 is
It is positioned at the gate material layers 26 in described first groove 241 and the second groove 242；
It is positioned at the second oxide layer 27 in described second trapping layer 22 and described gate material layers 26, it is also preferred that the left described
Dioxide layer thickness is
It is positioned at the first groove 241 and p-well 28a of the second groove 242 both sides in described Semiconductor substrate 20；
It is positioned at the N-type region in p-well 28a described in the first groove 241 and the second groove 242 both sides in described Semiconductor substrate 20
28b；The junction depth degree of depth of described N-type region 28b is less than the degree of depth of described p-well 28a, and such as, the junction depth degree of depth of described N-type region 28b is
0.1μm-0.5μm；
Being positioned at the blanket dielectric layer in described Semiconductor substrate 20, described blanket dielectric layer includes that covering described first stops
Layer the 21, second trapping layer 22 and the first medium layer 29a of the second oxide layer 27 and cover described first medium layer 29a second Jie
Matter layer 29b；The material of described first medium layer 29a is plain silicon dioxide, silicon nitride, the one of silicon oxynitride or its group
Close, the material of described second dielectric layer 29b is boron-phosphorosilicate glass, in described second dielectric layer 29b the mass percent of boron be 1～
5%, the mass percent of phosphorus is 2～6%, it is also preferred that the left the thickness of described first medium layer 29a isDescribed
The thickness of second dielectric layer 29b isCertainly, described blanket dielectric layer can also be only second dielectric layer
29a；
Contact hole 30, described contact hole 30 is positioned at described first groove 241 both sides and runs through described blanket dielectric layer, the first resistance
Only layer 21 extending in described Semiconductor substrate 20, and be positioned in described second groove 242 run through described blanket dielectric layer,
Second oxide layer 27 also extends in described gate material layers 26, it is also preferred that the left the sidewall of described contact hole 30 and the prolongation of diapire
Line is 80 ° of-89 ° of angles, and the degree of depth that described contact hole 30 is positioned in described Semiconductor substrate 20 is less than or equal to 1 μm；
It is positioned at the p type island region 30c bottom described contact hole 30；
The metal level 31 being positioned in described blanket dielectric layer, described metal level 31 fills described contact hole 30；It is also preferred that the left institute
State the material of metal level 31 be titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), silicated aluminum (AlSi),
Metal or the compounds of metal such as copper silmin (AlSiCu), copper (Cu) or nickel (Ni)；And
It is positioned at the passivation layer on described metal level 31.
Thus, a kind of grooved gate power device of this utility model offer and manufacture method, by providing Semiconductor substrate；?
The first trapping layer, the second trapping layer and the 3rd trapping layer is sequentially formed in described Semiconductor substrate；Etch described 3rd trapping layer,
The Semiconductor substrate of the second trapping layer, the first trapping layer and segment thickness is to form the first groove and the second groove；Described
Gate dielectric layer is grown on first groove described in Semiconductor substrate and the sidewall of the second groove and diapire；At described first groove and
Forming gate material layers in second groove, remove the 3rd trapping layer, described gate material layers has higher than described second trapping layer
A part；Oxidation gate material layers so that described gate material layers produces second higher than a part for described second trapping layer
Oxide layer, and described second oxide layer covering part the second trapping layer；Remove in described second trapping layer not by the second oxide layer
The part covered；In described Semiconductor substrate, the first groove and the second groove both sides form p-well；In described Semiconductor substrate
N-type region is formed in p-well described in first groove and the second groove both sides；Form blanket dielectric layer on the semiconductor substrate；Carve
Losing described blanket dielectric layer in described Semiconductor substrate, form contact hole, described contact hole is positioned at the first groove both sides and the
In two grooves；And bottom described contact hole, form p type island region.So that whole slot grid structure is protected, in existing photoetching
Slot grid structure is made not affected by contact hole instability technique in processing technique under appointed condition, it is achieved less live width and more
The production of big alignment surplus product, makes the parameter of product and reliability meet requirement.
It should be noted that grooved gate power device structure of the present utility model and manufacture method can be used in include but not
It is limited in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Obviously, those skilled in the art can carry out various change and modification without deviating from this practicality to this utility model
Novel spirit and scope.So, if of the present utility model these amendment and modification belong to this utility model claim and
Within the scope of its equivalent technologies, then this utility model is also intended to comprise these change and modification.
Claims (11)
1. a grooved gate power device, including:
Semiconductor substrate；
The first trapping layer being positioned in described Semiconductor substrate；
It is positioned at the second trapping layer on described first trapping layer；
Run through described second trapping layer, the first trapping layer the first groove extending in described Semiconductor substrate and the second ditch
Groove；
It is positioned at the first groove described in described Semiconductor substrate and the sidewall of the second groove and the gate dielectric layer of diapire；
It is positioned at the gate material layers in described first groove and the second groove；
It is positioned at the second oxide layer in described second trapping layer and described gate material layers；
It is positioned at the first groove and the p-well of the second groove both sides in described Semiconductor substrate；
It is positioned at the N-type region in p-well described in the first groove and the second groove both sides in described Semiconductor substrate；
It is positioned at the blanket dielectric layer in described Semiconductor substrate；
Contact hole, described contact hole is positioned at described first groove both sides to be run through described blanket dielectric layer, the first trapping layer and extends
To in described Semiconductor substrate, and it is positioned in described second groove and runs through described blanket dielectric layer, the second oxide layer and extend
To described gate material layers；
It is positioned at the p type island region bottom described contact hole.
2. grooved gate power device as claimed in claim 1, it is characterised in that described first trapping layer and the second trapping layer are two
Silicon oxide trapping layer, silicon nitride trapping layer, silicon oxynitride trapping layer, the one of polysilicon trapping layer.
3. grooved gate power device as claimed in claim 1 or 2, it is characterised in that the thickness of described first trapping layer isThe thickness of described second trapping layer is
4. grooved gate power device as claimed in claim 1, it is characterised in that the width of described first groove is 0.05 μm-1 μ
M, the degree of depth is 0.1 μm-10 μm；The width of described second groove is 0.5 μm-5 μm, and the degree of depth is 0.1 μm-50 μm.
5. grooved gate power device as claimed in claim 1, it is characterised in that the thickness of described second oxide layer is
6. grooved gate power device as claimed in claim 1, it is characterised in that described blanket dielectric layer includes covering described half
The first medium layer of conductor substrate.
7. grooved gate power device as claimed in claim 6, it is characterised in that described blanket dielectric layer also includes covering described the
The second dielectric layer of one dielectric layer.
8. grooved gate power device as claimed in claim 7, it is characterised in that described first medium layer is plain titanium dioxide
Silicon dielectric layer, silicon nitride medium layer, the one of silicon oxynitride dielectric layer；Described second dielectric layer is boron-phosphorosilicate glass dielectric layer.
9. grooved gate power device as claimed in claim 7, it is characterised in that the thickness of described first medium layer isThe thickness of described second dielectric layer is
10. grooved gate power device as claimed in claim 1, it is characterised in that the sidewall of described contact hole and the prolongation of diapire
Line is 80 ° of-89 ° of angles, and the degree of depth that described contact hole is positioned in described Semiconductor substrate is less than or equal to 1 μm.
11. grooved gate power devices as claimed in claim 1, it is characterised in that also include:
Being positioned at the metal level in described blanket dielectric layer, described metal level fills described contact hole；And
It is positioned at the passivation layer on described metal level.
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| CN201620738729.3U CN205863138U (en) | 2016-07-12 | 2016-07-12 | Grooved gate power device |
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| CN201620738729.3U CN205863138U (en) | 2016-07-12 | 2016-07-12 | Grooved gate power device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024636A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Grooved gate power device and manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024636A (en) * | 2016-07-12 | 2016-10-12 | 杭州士兰集成电路有限公司 | Grooved gate power device and manufacturing method |
| CN106024636B (en) * | 2016-07-12 | 2023-08-04 | 杭州士兰集成电路有限公司 | Groove gate power device and manufacturing method |
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