CN106024636B - Groove gate power device and manufacturing method - Google Patents
Groove gate power device and manufacturing method Download PDFInfo
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- CN106024636B CN106024636B CN201610551898.0A CN201610551898A CN106024636B CN 106024636 B CN106024636 B CN 106024636B CN 201610551898 A CN201610551898 A CN 201610551898A CN 106024636 B CN106024636 B CN 106024636B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a trench gate power device and a manufacturing method thereof. According to the trench gate power device and the manufacturing method, the gate material layer in the trench is provided with the part higher than the second blocking layer, the part is oxidized to form the second oxide layer, and the second oxide layer covers part of the second blocking layer, so that the whole trench gate structure is protected, the trench gate structure is not influenced by the unstable process of the contact hole in the processing process under the condition of the existing photoetching equipment, the production of products with smaller line width and larger overlay allowance is realized, and the parameters and reliability of the products meet the requirements.
Description
Technical Field
The invention relates to the field of semiconductor equipment, in particular to a trench gate power device and a manufacturing method thereof.
Background
Power devices can be classified into two types, i.e., power IC (integrated circuit) devices and power discrete devices, which in turn include power MOSFETs (metal-oxide semiconductor field effect transistors), high power transistors, IGBTs (insulated gate bipolar transistors), and the like. Early power devices were produced based on planar technology, but with the development of semiconductor technology, small size, high power and high performance have become major trends. Taking a planar process MOSFET device as an example, the area of a single cell is reduced only to a limited extent due to the limitation of the parasitic resistance of the JFET (junction field effect transistor) in itself, which makes it difficult to increase the cell density and makes it difficult to further reduce the on-Resistance (RDSON) of the planar process MOSFET. The trench technology changes the channel from horizontal to vertical, eliminates the influence of parasitic JFET resistance of a planar structure, greatly reduces the cell size, can increase the cell density on the basis of the channel width, improves the total width of the channel in a unit area chip, and can increase the channel width-to-length ratio of the device on a unit silicon wafer so as to increase the current, reduce the on-resistance and optimize related parameters, thereby realizing the aim that a smaller-sized die has higher power and high performance, and the trench technology is increasingly applied to novel power devices.
With the development of semiconductor technology, in order to realize lower cost advantage and continuously smaller minimum line width, the line widths of the trenches and the contact holes in the conventional typical trench power device become smaller, pitch width is compressed simultaneously, so that the distance between the contact holes and the gate trenches becomes narrower, at this time, if the line width of the contact holes is not small enough, the offset precision cannot meet the allowance requirement, and further the offset technological problem occurs, the structure of the device is difficult to realize, and further parameters such as Vth (threshold voltage), BVds (drain-source breakdown voltage), rdson even GS short circuit (gate-source short circuit) and the like are abnormal, so that reliability risks are formed.
Fig. 1 is a schematic diagram showing a problem that a MOSFET in a trench power device in the prior art easily occurs under the limit capability of a photolithography apparatus. The area a represents the normal morphology of the contact hole 4, and at this time, the line width of the contact hole 4 formed on the surface of the semiconductor substrate 1 is d1, and the distances between the contact hole 4 and the adjacent trench 5 are a1 and a2, respectively. When the width of d1 is within the capacity of the lithographic apparatus, the contact hole 4 will not have morphology problems caused by underexposure, poor resolution, etc. When the equipment alignment capability is better, both a1 and a2 can meet the offset range of the product design, and the smaller the |a1-a2| the better, when a1-a2=0, the best alignment precision and the best alignment capability are indicated.
Region B represents an abnormal topography when the photolithographic linewidth of the contact hole 4 is designed to the device limit capability but still does not meet the predetermined linewidth design requirements, eventually causing the gate oxide 3, polysilicon 2 within the contact hole 4 and trench 5 to be or even to have been contacted. At this time, the line width of the contact hole 4 formed on the surface of the semiconductor substrate 1 is d2, and the pitches of the contact hole 4 and the adjacent trench 5 are b1 and b2, respectively. When b1 and b2 are smaller than the allowable spacing requirement of the product, parameters such as Vth, BVds, rdson and the like are abnormal, and reliability risks exist. When b1 and b2 are infinitely small or even negative, the contact hole 4 is in contact with the gate oxide 3 and the polysilicon 2 in the trench 5, and abnormal parameters such as GS short circuit and the like can occur. This is a failure condition where the typical line width is large and the equipment capacity is insufficient for smaller size processing of the product.
The region C represents the structural morphology of the contact hole 4, which is not in the middle of the left and right grooves 5 and causes abnormal parameters, when the photolithographic line width of the contact hole 4 meets the requirement of small line width, but the overlay capability of the photolithographic equipment cannot meet the structural requirement of the product. At this time, the line width of the contact hole 4 formed on the surface of the semiconductor substrate 1 is d3, and the distances between the contact hole 4 and the adjacent grooves 5 are c1 and c2, wherein c1 is far greater than the offset margin range of the product design, c2 is smaller than the offset margin range of the product design, and even the contact hole 4 approaches the gate oxide 3 and the polysilicon 2 in the grooves 5 infinitely, the parameter anomalies such as Vth, BVds, rdson and even GS short circuit are easy to occur. This is a failure condition where the linewidth capability of a typical lithographic apparatus is normal but the overlay accuracy cannot meet the smaller size of the product. If in region C, both C1 and C2 are within the range of the product design bias, various failures can be avoided.
Therefore, how to realize smaller line width under the condition of the existing photoetching equipment and ensure the distance from the contact hole to the slot grid structure, so that enough allowance is reserved between the contact hole and the slot, thereby realizing the production of the device structure with smaller line width, and simultaneously, the parameters and the reliability of the product meet the requirements, which is the content to be researched by the person skilled in the art.
Disclosure of Invention
The invention aims to provide a trench gate power device and a manufacturing method thereof, which protect a trench gate structure, prevent the trench gate structure from being influenced by an unstable process of a contact hole in a processing process under the condition of the existing photoetching equipment, realize the production of products with smaller line width and larger alignment allowance, and ensure that the parameters and the reliability of the products meet the requirements.
In order to solve the technical problems, the invention provides a manufacturing method of a trench gate power device, comprising the following steps:
providing a semiconductor substrate;
forming a first blocking layer, a second blocking layer and a third blocking layer on the semiconductor substrate in sequence;
etching the third blocking layer, the second blocking layer, the first blocking layer and a part of the thickness of the semiconductor substrate to form a first groove and a second groove;
growing a gate dielectric layer on the side walls and the bottom walls of the first groove and the second groove in the semiconductor substrate;
forming a gate material layer in the first trench and the second trench, removing the third blocking layer, the gate material layer having a portion higher than the second blocking layer;
oxidizing the gate material layer such that a portion of the gate material layer above the second blocking layer creates a second oxide layer, and the second oxide layer covers a portion of the second blocking layer;
removing the part of the second blocking layer which is not covered by the second oxide layer;
forming P wells at two sides of a first groove and a second groove in the semiconductor substrate;
forming an N-type region on the P well at two sides of the first groove and the second groove in the semiconductor substrate;
forming a covering dielectric layer on the semiconductor substrate;
etching the covering dielectric layer into the semiconductor substrate to form contact holes, wherein the contact holes are positioned at two sides of the first groove and in the second groove; and
and forming a P-type region at the bottom of the contact hole.
Optionally, for the method for manufacturing a trench gate power device, the materials of the first blocking layer, the second blocking layer and the third blocking layer are one or a combination of silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.
Optionally, for the method for manufacturing a trench gate power device, the thickness of the first blocking layer isThe thickness of the second blocking layer is +.>The thickness of the third blocking layer is
Optionally, for the method for manufacturing the trench gate power device, the width of the first trench is 0.05 μm-1 μm, and the depth is 0.1 μm-10 μm; the second grooves have a width of 0.5 μm to 5 μm and a depth of 0.1 μm to 50 μm.
Optionally, for the method for manufacturing the trench gate power device, after forming the first trench and the second trench, before growing the gate dielectric layer, the method further includes:
forming a first oxide layer on the side walls and the bottom walls of the first groove and the second groove in the semiconductor substrate;
and removing the first oxide layer.
Optionally, for the method for manufacturing a trench gate power device, after forming the gate material layer in the first trench and the second trench, before removing the third blocking layer, the method further includes:
the gate material layer that is created on the surface of the third stop layer upon deposition is removed such that the upper surface of the gate material layer is flush with the upper surface of the third stop layer.
Optionally, for the manufacturing method of the trench gate power device, a wet oxidation process is used to form the second oxide layer.
Optionally, for the method for manufacturing a trench gate power device, the thickness of the second oxide layer is
Optionally, for the method for manufacturing a trench gate power device, the dielectric layer includes a first dielectric layer covering the semiconductor substrate.
Optionally, for the method for manufacturing a trench gate power device, the dielectric layer covering the trench gate power device further includes a second dielectric layer covering the first dielectric layer.
Optionally, for the method for manufacturing a trench gate power device, the material of the first dielectric layer is one or more combinations of undoped silicon dioxide, silicon nitride and silicon oxynitride; and the second dielectric layer is made of borophosphosilicate glass.
Optionally, for the method for manufacturing a trench gate power device, the first dielectric layer and the second dielectric layer are both formed by a chemical vapor deposition process.
Optionally, for the method for manufacturing a trench gate power device, the reaction source gas for forming the second dielectric layer includes SiH 4 、B 2 H 6 And/or pH 3 The method comprises the steps of carrying out a first treatment on the surface of the The mass percentage of boron in the second dielectric layer is 1-5%, and the mass percentage of phosphorus is 2-6%.
Optionally, for the method for manufacturing a trench gate power device, the thickness of the first dielectric layer isThe thickness of the second dielectric layer is +.>
Optionally, for the manufacturing method of the trench gate power device, the side wall of the contact hole and the extension line of the bottom wall form an angle of 80 ° -89 °, and the depth of the contact hole is less than or equal to 1 μm.
Optionally, for the method for manufacturing a trench gate power device, after forming the P-type region at the bottom of the contact hole, the method further includes:
forming a metal layer on the covering dielectric layer, wherein the metal layer fills the contact hole; and
and forming a passivation layer on the metal layer.
The invention also provides a trench gate power device, comprising:
a semiconductor substrate;
a first blocking layer on the semiconductor substrate;
a second blocking layer located on the first blocking layer;
a first trench and a second trench penetrating the second stopper layer, the first stopper layer, and extending into the semiconductor substrate;
gate dielectric layers located on the side walls and the bottom walls of the first groove and the second groove;
a gate material layer located in the first and second trenches;
a second oxide layer on the second blocking layer and the gate material layer;
p wells positioned at two sides of the first groove and the second groove in the semiconductor substrate;
the N-type region is positioned on the P well at two sides of the first groove and the second groove in the semiconductor substrate;
a capping dielectric layer on the semiconductor substrate;
the contact holes are located at two sides of the first groove, penetrate through the covering dielectric layer and the first blocking layer and extend into the semiconductor substrate, and are located in the second groove, penetrate through the covering dielectric layer and the second oxidation layer and extend into the grid electrode material layer.
Optionally, for the trench gate power device, the material of the first blocking layer and the second blocking layer is one or a combination of silicon dioxide, silicon nitride, silicon oxynitride, and polysilicon.
Optionally, for the trench gate power device, the thickness of the first blocking layer isThe thickness of the second blocking layer is +.>
Optionally, for the trench gate power device, the width of the first trench is 0.05 μm-1 μm, and the depth is 0.1 μm-10 μm; the second grooves have a width of 0.5 μm to 5 μm and a depth of 0.1 μm to 50 μm.
Optionally, for the trench gate power device, the thickness of the second oxide layer is
Optionally, for the trench gate power device, the dielectric layer includes a first dielectric layer covering the semiconductor substrate.
Optionally, for the trench gate power device, the dielectric layer further includes a second dielectric layer covering the first dielectric layer.
Optionally, for the trench gate power device, the material of the first dielectric layer is one or more combinations of undoped silicon dioxide, silicon nitride and silicon oxynitride; and the second dielectric layer is made of borophosphosilicate glass.
Optionally, for the trench gate power device, the mass percentage of boron in the second dielectric layer is 1-5%, and the mass percentage of phosphorus is 2-6%.
Optionally, for the trench gate power device, the thickness of the first dielectric layer isThe thickness of the second dielectric layer is +.>
Optionally, for the trench gate power device, the side wall of the contact hole and the extension line of the bottom wall form an angle of 80 ° -89 °, and the depth of the contact hole in the semiconductor substrate is less than or equal to 1 μm.
Optionally, for the trench gate power device, the method further includes:
the metal layer is positioned on the covering dielectric layer and fills the contact hole; and
and a passivation layer on the metal layer.
Compared with the prior art, the trench gate power device and the manufacturing method thereof provided by the invention have the advantages that the gate material layer in the trench is provided with a part higher than the second blocking layer, the part is oxidized to form the second oxide layer, and the second oxide layer covers part of the second blocking layer, so that the whole trench gate structure is protected, the trench gate structure is not influenced by the unstable process of the contact hole in the processing process under the condition of the existing photoetching equipment, the production of products with smaller line width and larger overlay allowance is realized, and the parameters and the reliability of the products meet the requirements.
Drawings
FIG. 1 is a schematic diagram of a problem that occurs easily in a trench power device under the limiting capability of a photolithography apparatus in the prior art;
FIG. 2 is a flow chart of a method for fabricating a trench gate power device in accordance with an embodiment of the present invention;
fig. 3-11 are schematic structural diagrams of a trench gate power device according to an embodiment of the invention.
Detailed Description
The trench gate power device and method of fabrication of the present invention will now be described in more detail with reference to the drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the beneficial effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a trench gate power device and a manufacturing method thereof, wherein the manufacturing method of the trench gate power device comprises the following steps:
step S11, providing a semiconductor substrate;
step S12, sequentially forming a first stopping layer, a second stopping layer and a third stopping layer on the semiconductor substrate;
step S13, etching the third stopping layer, the second stopping layer, the first stopping layer and a part of thickness of the semiconductor substrate to form a first groove and a second groove;
step S14, growing a gate dielectric layer on the side wall and the bottom wall of the first groove and the second groove in the semiconductor substrate;
step S15, forming a gate material layer in the first groove and the second groove, and removing a third blocking layer, wherein the gate material layer is higher than a part of the second blocking layer;
step S16, oxidizing the gate material layer so that a part of the gate material layer higher than the second blocking layer generates a second oxide layer, and the second oxide layer covers a part of the second blocking layer;
step S17, removing the part of the second blocking layer which is not covered by the second oxide layer;
step S18, forming P wells at two sides of a first groove and a second groove in the semiconductor substrate;
s19, forming N-type regions on the P-well at two sides of the first groove and the second groove in the semiconductor substrate;
step S20, forming a covering dielectric layer on the semiconductor substrate;
s21, etching the covering dielectric layer into the semiconductor substrate to form contact holes, wherein the contact holes are positioned at two sides of the first groove and in the second groove; and
and S22, forming a P-type region at the bottom of the contact hole.
The trench gate power device and the method of manufacturing the same of the present invention are described in detail below with reference to fig. 2 and fig. 3-11.
First, step S11 is performed, and as shown in fig. 3, a semiconductor substrate 20 is provided. Preferably, the semiconductor substrate 20 may be a silicon substrate, a silicon germanium substrate, a group iii-v element compound substrate, or other semiconductor material substrate known to those skilled in the art, and in this embodiment, a silicon substrate is used. Further, the silicon substrate used in the present embodiment may be formed with a semiconductor device such as a MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate field effect transistor), a schottky diode, or the like. The semiconductor substrate 20 may also be doped with a certain amount of impurities, both N-type and P-type, depending on the characteristics of the desired product.
Next, step S12 is performed, and as shown in fig. 3, a first stopper 21, a second stopper 22, and a third stopper 23 are sequentially formed on the semiconductor substrate 20. The first, second and third stopper layers 21, 22 and 23 formed on the semiconductor substrate 20 may be formed by oxidation or deposition. For example, the materials of the first, second and third blocking layers 21, 22 and 23 may be one or more combinations of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, etc. Preferably, the thickness of the first blocking layer isThe thickness of the second blocking layer isThe thickness of the third blocking layer is +.>
Next, step S13 is performed to etch the third stopper 23, the second stopper 22, the first stopper 21, and the semiconductor substrate 20 having a partial thickness, i.e., etch the third stopper 23 into the semiconductor substrate 20 to form the first trench 241 and the second trench 242. Referring to fig. 4, the area where the first trench 241 is located is a first window area 24a, and the area where the second trench 242 is located is a second window area 24b. The first window region 24a refers to a cell region of the power device, and the second window region 24b refers to a terminal region of the power device.
In step S13, a window is selectively opened by photolithography, and a photoresist is used as a mask, and after the third stop layer 23, the second stop layer 21 and the first stop layer 21 are etched from top to bottom, the semiconductor substrate 20 is further etched deep to form a first trench 241 and a second trench 242 having a certain width and depth. The layout of the first grooves 241 and the second grooves 242 may be designed according to the product structure, the widths of the first grooves 241 and the second grooves 242 may be determined according to the product structure and the process capability, and the depth may be determined according to the pressure resistance of the product, etc.
Further, in the present embodiment, the first and second trenches 241 and 242 are formed to have widths of 0.05 μm to 5 μm and depths of 0.1 μm to 50 μm. Specifically, for the first trench 241 in the first window region 24a, the width L1 thereof may be determined according to the on-density of the product, the minimum line width may be equal to or greater than the limit capability of the device, and L1 may be 0.05 μm to 1 μm; the depth h1 can be determined according to the pressure resistance of the product and the like, and h1 can be 0.1-10 mu m. Regarding the second trench 242 in the second window region 24b, considering that the trench is to be filled with polysilicon, the width needs to meet the requirements of carrying high voltage and large current, and thus the width is wider, and part of the structure needs to be provided with a lead hole on the polysilicon filled in the subsequent trench, so the width L2 of the second trench 242 is wider than the first trench 221, and L2 can be 0.5 μm-5 μm; in the case of a wider width, the same etching procedure etches deeper for large linewidth regions, depending on the etching loading effect, so h2> h1, h2 may be normally 0.1 μm-50 μm. It should be noted that, it is not possible to draw a conclusion that the depth and width of the first trench 241 and the second trench 242 are identical to each other simply according to the drawings.
Preferably, step S131 is performed immediately after oxidizing the sidewalls and bottom walls of the first trench 241 and the second trench 242 in the semiconductor substrate 20 at a temperature of 1000 ℃ to 1200 ℃ to form a first oxide layer (not shown) for repairing the sidewalls and bottom walls of the first trench 241 and the second trench 242, wherein the thickness of the first oxide layer is in a range of
Then, step S132 is performed to remove the first oxide layer, where in this embodiment, a BOE (buffered hydrofluoric acid) etching solution or DHF (diluted hydrofluoric acid) may be used to remove the first oxide layer;
next, step S14 is performed, as shown in fig. 5, in the present embodiment, on the side walls and the bottom walls of the first trench 241 and the second trench 242 in the semiconductor substrate 20A gate dielectric layer 25 is grown. For example, the gate dielectric layer 25 may be gate oxide, specifically, the gate dielectric layer 25 is formed by chlorine doped oxidation (i.e. oxidation in atmosphere containing chlorine and oxygen), and grown at a temperature ranging from 1000deg.C to 1200deg.C to obtain a thickness ranging fromA gate dielectric layer 25 of (a); the higher the growth temperature of the gate dielectric layer 25 is, the better the quality is, and the chlorine-doped oxidation can effectively reduce the impurities in the gate dielectric layer 25 and improve the quality of the gate dielectric layer 25.
Then, step S15 is performed to form a gate material layer 26 in the first trench 241 and the second trench 242, and remove the third blocking layer, wherein the gate material layer 26 has a portion higher than the second blocking layer 22. Referring to fig. 6, the gate material layer 26 may be a doped polysilicon layer, for example. Undoped polysilicon can be deposited firstly, and then doped by ion implantation; or firstly depositing undoped polysilicon, and then doping the undoped polysilicon by adopting a phosphorus pre-deposition process; or an in-situ doping mode of doping while depositing the polysilicon is adopted.
Specifically, in this step S15, after the deposition is completed, the gate material layer 26 generated on the surface of the third blocking layer during the deposition needs to be removed, and the gate material layer 26 in the first trench 241 and the second trench 242 is flush with the surface of the third blocking layer, which may be accomplished by dry etching having isotropy. The third blocking layer is then rinsed by wet etching, so that the gate material layer 26 in the first trench 241 and the second trench 242 has a portion higher than the second blocking layer 22, and the height h3 is less than or equal to the thickness of the third blocking layer in step S12.
Then, step S16 is performed, as shown in fig. 7, to oxidize the gate material layer 26, so that a portion of the gate material layer 26 higher than the second stopper layer 22 generates a second oxide layer 27, and the second oxide layer 27 covers a portion of the second stopper layer 22. A wet oxidation process may be employed such that a portion of the gate material layer 26 above the second stop layer 22 creates a secondThe temperature of the wet oxidation is 800-1000 ℃, the second oxide layer 27 is a silicon oxide layer with the thickness of
After that, step S17 is performed, please refer to fig. 8, and the portion of the second blocking layer 22 not covered by the second oxide layer 27 is removed. The second blocking layer 22, which is not covered by the second oxide layer 27 formed in step S16, may be etched away using dry etching, exposing the first blocking layer 21.
Next, step S18 is performed, and as shown in fig. 8, P-wells 28a are formed on both sides of the first trench 241 and the second trench 242 in the semiconductor substrate 20. Specifically, the first ion implantation and annealing are performed on two sides of the first trench 241 and two sides of the second trench 242 in the semiconductor substrate 20, so as to form a P-well 28a, and the junction depth of the P-well 28a is smaller than the depth of the first trench 241. The first ion implantation and annealing adopts boron (B) ion zero-degree angle implantation, the implantation energy is 60KeV-150KeV, and the implantation dosage is 1E13/cm 2 -1E15/cm 2 The annealing temperature is 1000-1200 ℃.
Thereafter, step S19 is performed, and as shown in fig. 8, N-type regions 28b are formed on the P-well 28a at both sides of the first trench 241 and the second trench 242 in the semiconductor substrate 20. Specifically, the second ion implantation and annealing may be performed on both sides of the first trench 241 and both sides of the second trench 242 in the semiconductor substrate 20 to form the N-type region 28b, where the junction depth h4 of the N-type region 28b is 0.1 μm to 0.5 μm. The second ion implantation and annealing adopts zero-degree angle implantation of phosphorus (P) ions or arsenic (As) ions, the implantation energy is 60KeV-150KeV, and the implantation dosage is 1E14/cm 2 -1E16/cm 2 Annealing temperature is 800-1100 ℃. As can be seen from the implantation doses in step S18 and step S19, the doping concentration of the N-type region 28b is greater than that of the P-well 28a, so that the N-type region 28b is an N-type heavily doped region.
After that, step S20 is performed to form a capping dielectric layer. Referring to fig. 9, specifically, in this embodiment, the covering the dielectric layer includes covering the first layerA first dielectric layer 29a of the stopper layer 21, the second stopper layer 22, and the second oxide layer 27, and a second dielectric layer 29b covering the first dielectric layer 29a. The material of the first dielectric layer 29a is one or a combination of undoped silicon dioxide, silicon nitride and silicon oxynitride, and is formed by CVD or the like. The thickness of the first dielectric layer 29a may beThe second dielectric layer 29b is made of BPSG (borophosphosilicate glass) and has a thickness ofAlso CVD processes may be used. Specifically, the reactive source gas of the second dielectric layer 29b includes SiH 4 、B 2 H 6 And/or pH 3 Etc. Specifically, in the second dielectric layer 29B, the mass percentage of B is 1-5%, and the mass percentage of P is 2-6%.
Further, the capping dielectric layer may be only the first dielectric layer 29a that caps the semiconductor substrate 20.
Further, if the first dielectric layer 29a is made of silicon nitride, the trench region can be protected by using different selection ratios of the first dielectric layer 29a, the third dielectric layer 29b and silicon in the subsequent contact hole manufacturing, and further, smaller line width and larger overlay margin can be realized under the condition of the existing lithography equipment, thereby realizing the production of the device structure with smaller line width.
After that, step S21 is performed to etch the capping dielectric layer into the semiconductor substrate 20, so as to form contact holes 30, where the contact holes 30 are located at both sides of the first trench 241 and in the second trench 242. Referring to fig. 10, the etched contact hole 30 is approximately in an inverted trapezoid shape, i.e. has a wide top and a narrow bottom, the width of the bottom of the contact hole 30 is L5, and the width of the top opening is L4, L5< L4, so as to fill the dielectric layer in the production of the device structure with smaller line width. Wherein, the included angle θ between the side wall of the contact hole 30 and the extended line of the bottom wall is 80 ° to 89 °, and the depth h5 of the contact hole 30 in the semiconductor substrate 20 is less than or equal to 1 μm. After the contact hole 30 is formed, a third window region 30a is formed in the cell region, and a fourth window region 30b is formed in the terminal region.
In this step S21, the second dielectric layer 29b, the first dielectric layer 29a and the first blocking layer 21 are etched sequentially, and then the semiconductor substrate 20 is etched continuously to obtain steps with a certain depth, so that a portion of the semiconductor substrate doped into the N-type is etched away, and the N-type region can be penetrated by the subsequent P-type implantation.
Specifically, the area with the contact hole 30 in the third window area 30a is a source area between the grooves, and the source end serving as a primitive cell area is connected with metal; the area of the fourth window area 30b with the contact hole 30 is used as a voltage-resistant ring or Gate-PAD (Gate-PAD) end of the device to be connected with metal.
More specifically, referring to fig. 1, 3 and 10, the width of the top of the second dielectric layer 29b in the cell region shown in fig. 10 is L3, which is greater than the width L1 of the first trench 241 in fig. 3, so that the top of the first trench 241 is protected by the dielectric layer, and the GS leakage problem is not easy to occur.
More specifically, the width of the top opening of the contact hole 30 in the cell region shown in fig. 10 is L4, which generally represents the ultimate width of the contact hole 30 under the existing lithographic capability.
Then, step S22 is performed, please continue to refer to fig. 10, and a P-type region 30c is formed at the bottom of the contact hole 30. Specifically, a third ion implantation and annealing are performed to form the P-type region 30c. The third ion implantation adopts zero angle implantation B11 or BF 2 B11 can be injected first and BF can be injected later 2 The implantation energy is 20KeV-100KeV, and the implantation dosage is 1E14/cm 2 -1E16/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the Annealing is carried out at 500-1000 ℃ by adopting a furnace tube or rapid annealing. As can be seen from the implantation doses in step S18 and step S22, the doping concentration of the formed P-type region 30c is greater than that of the P-well 28a, so that the P-type region 30c is a P-type heavily doped region.
Then, step S23 is performed, please refer to fig. 11, a metal layer 31 is formed on the second dielectric layer 29b, and the metal layer 31 fills the contact hole. Specifically, the material of the metal layer 31 may be a metal or a compound of metals such as titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), aluminum silicide (AlSi), copper silicon aluminum alloy (AlSiCu), copper (Cu), or nickel (Ni), and the thickness thereof may be 1 μm to 8 μm. After the metal layer 31 is formed, a one-step etching process, for example, dry etching is performed to obtain a fifth window region 31a of the cell region and a sixth window region 31b of the terminal region.
Furthermore, passivation layer protection can be added according to the requirements of products, the processing of the front structure of the device is completed, and the final device structure is completed through a series of subsequent processes such as thinning, gold backing, scribing and the like.
As can be seen in fig. 3 to 11, the trench gate power device obtained in this embodiment includes:
a semiconductor substrate 20;
a first stopper layer 21 on the semiconductor substrate 20;
a second stopper layer 22 on the first stopper layer 21; preferably, the thickness of the first blocking layer 21 isThe thickness of the second stopper layer 22 is +.>The first blocking layer 21 and the second blocking layer 22 are made of one or a combination of silicon dioxide, silicon nitride, silicon oxynitride and polysilicon;
a first trench 241 and a second trench 242 penetrating the second stopper 22, the first stopper 21 and extending into the semiconductor substrate 20, preferably, the first trench 241 has a width of 0.05 μm to 1 μm and a depth of 0.1 μm to 10 μm; the second grooves 242 have a width of 0.5 μm to 5 μm and a depth of 0.1 μm to 50 μm;
a gate dielectric layer 25 on sidewalls and bottom walls of the first and second trenches 241 and 242 in the semiconductor substrate 20; the gate dielectric layer 25 has a thickness of
A gate material layer 26 located in the first and second trenches 241 and 242;
a second oxide layer 27 on the second blocking layer 22 and the gate material layer 26, preferably having a thickness of
P-wells 28a located on both sides of the first and second trenches 241 and 242 in the semiconductor substrate 20;
an N-type region 28b located in the semiconductor substrate 20 on the P-well 28a on both sides of the first trench 241 and the second trench 242; the junction depth of the N-type region 28b is less than the depth of the P-well 28a, e.g., the junction depth of the N-type region 28b is 0.1 μm to 0.5 μm;
a capping dielectric layer on the semiconductor substrate 20, the capping dielectric layer including a first dielectric layer 29a covering the first blocking layer 21, the second blocking layer 22 and the second oxide layer 27, and a second dielectric layer 29b covering the first dielectric layer 29a; the material of the first dielectric layer 29a is undoped silicon dioxide, silicon nitride, silicon oxynitride or a combination thereof, the material of the second dielectric layer 29b is borophosphosilicate glass, the mass percentage of boron in the second dielectric layer 29b is 1-5%, the mass percentage of phosphorus is 2-6%, the thickness of the first dielectric layer 29a is preferably thatThe thickness of the second dielectric layer 29b is +.>Of course, the covering dielectric layer may be just the second dielectric layer 29a;
a contact hole 30, wherein the contact hole 30 is located at two sides of the first trench 241, penetrates through the covering dielectric layer and the first blocking layer 21 and extends into the semiconductor substrate 20, and is located in the second trench 242, penetrates through the covering dielectric layer and the second oxide layer 27 and extends into the gate material layer 26, preferably, the side wall of the contact hole 30 forms an angle of 80 ° -89 ° with the extension line of the bottom wall, and the depth of the contact hole 30 in the semiconductor substrate 20 is less than or equal to 1 μm;
a P-type region 30c located at the bottom of the contact hole 30;
a metal layer 31 on the dielectric layer, wherein the metal layer 31 fills the contact hole 30; preferably, the material of the metal layer 31 is a metal or a compound of metals such as titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), aluminum silicide (AlSi), copper silicon aluminum alloy (AlSiCu), copper (Cu), or nickel (Ni); and
a passivation layer on the metal layer 31.
Therefore, the trench gate power device and the manufacturing method provided by the invention are characterized in that a semiconductor substrate is provided; forming a first blocking layer, a second blocking layer and a third blocking layer on the semiconductor substrate in sequence; etching the third blocking layer, the second blocking layer, the first blocking layer and a part of the thickness of the semiconductor substrate to form a first groove and a second groove; growing a gate dielectric layer on the side walls and the bottom walls of the first groove and the second groove in the semiconductor substrate; forming a gate material layer in the first trench and the second trench, removing the third blocking layer, the gate material layer having a portion higher than the second blocking layer; oxidizing the gate material layer such that a portion of the gate material layer above the second blocking layer creates a second oxide layer, and the second oxide layer covers a portion of the second blocking layer; removing the part of the second blocking layer which is not covered by the second oxide layer; forming P wells at two sides of a first groove and a second groove in the semiconductor substrate; forming an N-type region on the P well at two sides of the first groove and the second groove in the semiconductor substrate; forming a covering dielectric layer on the semiconductor substrate; etching the covering dielectric layer into the semiconductor substrate to form contact holes, wherein the contact holes are positioned at two sides of the first groove and in the second groove; and forming a P-type region at the bottom of the contact hole. Therefore, the whole groove gate structure is protected, the groove gate structure is not influenced by an unstable process of a contact hole in the processing process under the condition of the existing photoetching equipment, the production of products with smaller line width and larger alignment allowance is realized, and the parameters and the reliability of the products meet the requirements.
It should be noted that the trench gate power device structure and the manufacturing method of the present invention may be applied to products including, but not limited to, CMOS, BCD, power MOSFET, high power transistor, IGBT, schottky, etc.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (27)
1. A manufacturing method of a trench gate power device comprises the following steps:
providing a semiconductor substrate;
forming a first blocking layer, a second blocking layer and a third blocking layer on the semiconductor substrate in sequence;
etching the third blocking layer, the second blocking layer, the first blocking layer and a part of the thickness of the semiconductor substrate to form a first groove and a second groove;
growing a gate dielectric layer on the side walls and the bottom walls of the first groove and the second groove in the semiconductor substrate;
forming a gate material layer in the first trench and the second trench, removing the third blocking layer, the gate material layer having a portion higher than the second blocking layer;
oxidizing the gate material layer by a wet oxidation process, so that a part of the gate material layer higher than the second blocking layer generates a second oxide layer, and the second oxide layer covers a part of the second blocking layer;
removing the part of the second blocking layer which is not covered by the second oxide layer and exposing the first blocking layer;
forming P wells at two sides of a first groove and a second groove in the semiconductor substrate;
forming an N-type region on the P well at two sides of the first groove and the second groove in the semiconductor substrate;
forming a covering dielectric layer on the semiconductor substrate, wherein the covering dielectric layer covers the first blocking layer, the second blocking layer and the second oxide layer;
etching the covering dielectric layer and the first blocking layer into the semiconductor substrate to form contact holes, wherein the contact holes are positioned at two sides of the first groove and in the second groove, and the side wall of the contact hole and the extension line of the bottom wall form an angle of 80-89 degrees; and
and forming a P-type region at the bottom of the contact hole.
2. The method of claim 1, wherein the first, second and third blocking layers are formed of one or a combination of silicon dioxide, silicon nitride, silicon oxynitride, and polysilicon.
3. The method of manufacturing a trench gate power device of claim 1 or 2, wherein the first blocking layer has a thickness of 100 a-800 a, the second blocking layer has a thickness of 100 a-2000 a, and the third blocking layer has a thickness of 100 a-20000 a.
4. The method of manufacturing a trench gate power device of claim 3 wherein the first trench has a width of 0.05 μm to 1 μm and a depth of 0.1 μm to 10 μm; the second grooves have a width of 0.5 μm to 5 μm and a depth of 0.1 μm to 50 μm.
5. The method of fabricating a trench gate power device of claim 1, further comprising, after forming the first trench and the second trench, prior to growing the gate dielectric layer:
forming a first oxide layer on the side walls and the bottom walls of the first groove and the second groove in the semiconductor substrate;
and removing the first oxide layer.
6. The method of fabricating a trench-gate power device of claim 1, further comprising, after forming a gate material layer in the first trench and the second trench, before removing the third blocking layer:
the gate material layer that is created on the surface of the third stop layer upon deposition is removed such that the upper surface of the gate material layer is flush with the upper surface of the third stop layer.
7. The method of claim 1, wherein the second oxide layer has a thickness of 500 a-10000 a.
8. The method of claim 1, wherein the capping dielectric layer comprises a first dielectric layer capping the semiconductor substrate.
9. The method of manufacturing a trench gate power device of claim 8, wherein the capping dielectric layer further comprises a second dielectric layer capping the first dielectric layer.
10. The method for manufacturing the trench gate power device of claim 9, wherein the material of the first dielectric layer is one or more combinations of undoped silicon dioxide, silicon nitride, silicon oxynitride; and the second dielectric layer is made of borophosphosilicate glass.
11. The method of claim 9, wherein the first dielectric layer and the second dielectric layer are formed by a chemical vapor deposition process.
12. The method of fabricating a trench gate power device of claim 11 wherein the reactive source gas forming the second dielectric layer comprises SiH 4 、B 2 H 6 And/or pH 3 The method comprises the steps of carrying out a first treatment on the surface of the And the mass percentage of boron in the second dielectric layer is 1-5%, and the mass percentage of phosphorus is 2-6%.
13. The method of claim 9, wherein the first dielectric layer has a thickness of 100 a-5000 a and the second dielectric layer has a thickness of 2000 a-15000 a.
14. The method for manufacturing the trench gate power device according to claim 1, wherein the depth of the contact hole is 1 μm or less.
15. The method for manufacturing the trench gate power device of claim 1, further comprising, after forming the P-type region at the bottom of the contact hole:
forming a metal layer on the covering dielectric layer, wherein the metal layer fills the contact hole; and
and forming a passivation layer on the metal layer.
16. A trench gate power device comprising:
a semiconductor substrate;
a first blocking layer on the semiconductor substrate;
a second blocking layer located on the first blocking layer;
a first trench and a second trench penetrating the second stopper layer, the first stopper layer, and extending into the semiconductor substrate;
gate dielectric layers located in sidewalls and bottom walls of the first trench and the second trench in the semiconductor substrate;
a gate material layer located in the first and second trenches;
a second oxide layer on the second blocking layer and the gate material layer;
p wells positioned at two sides of the first groove and the second groove in the semiconductor substrate;
the N-type region is positioned on the P well at two sides of the first groove and the second groove in the semiconductor substrate;
the covering dielectric layer is positioned on the semiconductor substrate and covers the upper surface of the first blocking layer, the side surface of the second blocking layer and the second oxide layer;
the contact holes are positioned at two sides of the first groove, penetrate through the covering dielectric layer and the first blocking layer and extend into the semiconductor substrate, and are positioned in the second groove, penetrate through the covering dielectric layer and the second oxide layer and extend into the grid material layer, and the side wall of the contact hole and the extension line of the bottom wall form an angle of 80-89 degrees;
and the P-type region is positioned at the bottom of the contact hole.
17. The trench gate power device of claim 16 wherein the material of the first and second blocking layers is one or a combination of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon.
18. The trench gate power device of claim 16 or 17, wherein the first blocking layer has a thickness of 100 a-800 a and the second blocking layer has a thickness of 100 a-2000 a.
19. The trench gate power device of claim 16 wherein the first trench has a width of 0.05 μm to 1 μm and a depth of 0.1 μm to 10 μm; the second grooves have a width of 0.5 μm to 5 μm and a depth of 0.1 μm to 50 μm.
20. The trench gate power device of claim 16, wherein the second oxide layer has a thickness of 500 a-10000 a.
21. The trench gate power device of claim 16, wherein the capping dielectric layer comprises a first dielectric layer capping the semiconductor substrate.
22. The trench gate power device of claim 21, wherein the capping dielectric layer further comprises a second dielectric layer capping the first dielectric layer.
23. The trench gate power device of claim 22 wherein the material of the first dielectric layer is one or more combinations of undoped silicon dioxide, silicon nitride, silicon oxynitride; and the second dielectric layer is made of borophosphosilicate glass.
24. The trench gate power device of claim 23 wherein the second dielectric layer comprises 1-5% boron by mass and 2-6% phosphorus by mass.
25. The trench gate power device of claim 22, wherein the first dielectric layer has a thickness of 100 a-5000 a and the second dielectric layer has a thickness of 2000 a-15000 a.
26. The trench gate power device of claim 16 wherein said contact hole is located in said semiconductor substrate to a depth of 1 μm or less.
27. The trench gate power device of claim 16, further comprising:
the metal layer is positioned on the covering dielectric layer and fills the contact hole; and
and a passivation layer on the metal layer.
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