CN106024609B - Groove power device and production method - Google Patents
Groove power device and production method Download PDFInfo
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- CN106024609B CN106024609B CN201610554280.XA CN201610554280A CN106024609B CN 106024609 B CN106024609 B CN 106024609B CN 201610554280 A CN201610554280 A CN 201610554280A CN 106024609 B CN106024609 B CN 106024609B
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- 239000000463 material Substances 0.000 claims description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
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- 238000001259 photo etching Methods 0.000 claims description 7
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Present invention discloses a kind of groove power device and production methods.A kind of groove power device provided by the invention and production method, there is certain thickness first medium layer by being formed on the top of first groove and second groove, so that trench-gate region distance semiconductor substrate surface has certain distance, the first trapping layer is deposited again defines contact hole in the minimum dimension of semiconductor substrate surface, to the line width of contact hole be made further to do smaller when carrying out contact hole etching.And guarantees that contact hole realizes the production of the device architecture of smaller line width so that the set of contact hole and first groove and second groove be made to be carved with enough surpluses to the spacing of first groove and second groove, while meet the requirements the parameter of product and reliability.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of groove power device and production method.
Background technique
Power device can be divided into two class of Power IC (integrated circuit) device and power discrete device, and power discrete device wraps again
Including power MOSFET (Metal-Oxide Semiconductor field effect transistor), high power transistor and IGBT, (insulated gate bipolar is brilliant
Body pipe) etc. devices.Early stage power device is all based on planar technology production, but with the development of semiconductor technology, small size, big
Power, high-performance become main development trend.By taking planar technology MOSFET element as an example, due to itself internal JFET
The area reduction of the limitation of (junction field effect transistor) dead resistance, single primitive unit cell is limited, thus makes to increase primitive unit cell density
Become highly difficult, is difficult to make the conducting resistance (RDSON) of planar technology MOSFET to further decrease.Trench process is due to by channel
Become the influence for vertically eliminating planar structure parasitism JFET resistance from level, is substantially reduced cellular size, on this basis
Primitive unit cell density can be increased, improve the overall width of unit area chip interior raceway groove, so that it may so that ditch of the device on unit silicon wafer
Road breadth length ratio increases to optimize electric current increase, conducting resistance decline and relevant parameter, realizes smaller size of
Tube core possesses more high-power and high performance target, therefore trench process is more and more applies in New Type Power Devices.
It is existing in order to realize that lower cost advantage and minimum feature persistently become smaller with the development of semiconductor technology
The line width of groove and contact hole becomes smaller in typical groove power device, and Pitch (pitch) width compresses simultaneously, so that contact hole
Spacing between gate trench narrows, and at this time if the line width of contact hole is not accomplished sufficiently small, cannot meet to inclined precision remaining
Amount requires, and then appearance is to partially equal technological problems, it will the structure for directly resulting in device is difficult to realize, and then leads to Vth (threshold value
Voltage), BVds (drain-source breakdown voltage), the abnormal parameters such as Rdson even GS short circuit (grid source short circuit), form security risk.
Fig. 1 show what MOSFET in groove power device in the prior art was easy to appear under lithographic equipment limit capacity
Problem schematic diagram.Wherein, what a-quadrant represented is the normal pattern of contact hole 4, and contact hole 4 is in 1 surface shape of semiconductor substrate at this time
At line width be d1, the spacing of the groove 5 adjacent thereto of contact hole 4 is respectively a1 and a2.When the width of d1 is in lithographic equipment
When in limit of power, contact hole 4 is not in under-exposed, topography issues caused by resolution ratio is bad etc..When equipment alignment
In the preferable situation of ability, a1 and a2 be able to satisfy product design to inclined margin range, ︱ a1-a2 ︱ is the smaller the better, works as a1-a2
When=0, illustrate that alignment precision is best, alignment ability is best.
What B area represented is when the lithographic line width of contact hole 4 is designed but still is unsatisfactory for scheduled by equipment limit capacity
Line width design requirement, when finally making the grid oxygen 3 in contact hole 4 and groove 5, polysilicon 2 that will contact or even contact
Abnormal pattern.Contact hole 4 is d2 in the line width that 1 surface of semiconductor substrate is formed at this time, the groove 5 adjacent thereto of contact hole 4
Spacing is respectively b1 and b2.When b1 and b2 are respectively less than the pitch requirements of product permission, it may appear that the ginseng such as Vth, BVds, Rdson
Number is abnormal, and there are security risks.When b1 and b2 infinitely small even negative, contact hole 4 is and in groove 5
Grid oxygen 3, polysilicon 2 contact, it may appear that the abnormal parameters such as GS short circuit.This is that typical line width is bigger than normal, capacity of equipment is not able to satisfy
The failure conditions of product smaller szie processing.
C Regional Representative's is when the lithographic line width of contact hole 4 meets small linewidth requirements, but lithographic equipment alignment ability cannot
Meet product structure requirement, finally making contact hole 4 not leads to the structure and morphology of abnormal parameters in the centre of left and right trench 5.At this time
The line width that contact hole 4 is formed on 1 surface of semiconductor substrate is d3, the spacing of the groove 5 adjacent thereto of contact hole 4 be respectively c1 and
C2, wherein for c1 much larger than product design to inclined margin range, c2 is less than even contacting to inclined margin range for product design again
It is different to be also easy to appear the parameters such as Vth, BVds, Rdson even GS short circuit for grid oxygen 3, polysilicon 2 in 4 infinite approach groove 5 of hole
Often.This is that typical lithographic equipment line width ability is normal but alignment precision is not able to satisfy the smaller size of failure conditions of product.Such as
Fruit is in the region C, and c1 and c2 are in product design to then can be to avoid various failures in inclined range.
Therefore, how to realize smaller line width under the conditions of existing lithographic equipment, guarantee contact hole to slot grid structure spacing,
To make contact hole and groove set be carved with enough surpluses, to realize the production of the device architecture of smaller line width, while making to produce
The parameter and reliability of product are met the requirements, and are the contents to be studied of those skilled in the art.
Summary of the invention
The purpose of the present invention is to provide a kind of groove power device and production methods, real under the conditions of existing lithographic equipment
Now smaller line width, the spacing of guarantee contact hole to slot grid structure, so that contact hole and groove set is made to be carved with enough surpluses, thus
It realizes the production of the device architecture of smaller line width, while meets the requirements the parameter of product and reliability.
In order to solve the above technical problems, the present invention provides a kind of production method of groove power device, comprising:
Semiconductor substrate is provided；
First groove and second groove are formed in the semiconductor substrate；
Grow gate dielectric layer on the semiconductor substrate and on the side wall and bottom wall of the first groove and second groove；
Gate material layers are formed in the first groove and second groove；
First medium layer is formed in the gate material layers in the first groove and second groove；
First groove and second groove two sides form p-well in the semiconductor substrate；
N-type region is formed in p-well described in first groove and second groove two sides in the semiconductor substrate；
The first trapping layer is formed on the semiconductor substrate, and forms opening in first trapping layer to expose
The semiconductor substrate and part second groove, and first trapping layer covers the first groove；
Blanket dielectric layer is formed on the semiconductor substrate；
Photoetching simultaneously etches the blanket dielectric layer into the semiconductor substrate, forms the contact hole, the contact hole
In first groove two sides and second groove, the width of the opening is the contact hole in the semiconductor substrate surface
Minimum dimension；
P type island region is formed in the contact hole bottom.
Optionally, for the production method of the groove power device, the material of first trapping layer is silicon nitride
And/or silicon oxynitride.
Optionally, for the production method of the groove power device, first trapping layer with a thickness of
Optionally, for the production method of the groove power device, the width of the first groove is 0.05 μm of -1 μ
M, depth are 0.1 μm -10 μm；The width of the second groove is 0.5 μm -5 μm, and depth is 0.1 μm -50 μm.
Optionally, for the production method of the groove power device, the width of the opening is 0.02 μm -2 μm, small
Spacing between adjacent first groove, and it is less than the width of the second groove.
Optionally, for the production method of the groove power device, the second resistance is formed in the semiconductor substrate
Only layer.
Optionally, for the production method of the groove power device, the material of second trapping layer is titanium dioxide
One or more combinations of silicon, silicon nitride, silicon oxynitride, polysilicon.
Optionally, for the production method of the groove power device, second trapping layer with a thickness of
Optionally, for the production method of the groove power device, the first ditch is formed in the semiconductor substrate
After slot and second groove, before growing gate dielectric layer, further includes:
The first oxide layer is formed in the side wall and bottom wall of the first groove and second groove；
Remove first oxide layer and second trapping layer.
Optionally, for the production method of the groove power device, the shape in the first groove and second groove
It after gate material layers, is formed before first medium layer in gate material layers in the first groove and second groove, also
Include:
Gate material layers on the semiconductor substrate surface are generated when removal deposit, and make the first groove and the
Gate material layers in two grooves are lower than the semiconductor substrate surface.
Optionally, for the production method of the groove power device, the gate material layers upper surface is lower than described
The distance of semiconductor substrate surface is less than or equal to 0.8 μm.
Optionally, for the production method of the groove power device, the material of the first medium layer is titanium dioxide
One or more combinations of silicon, silicon nitride, silicon oxynitride, polysilicon.
Optionally, for the production method of the groove power device, the blanket dielectric layer includes covering described half
The second dielectric layer of conductor substrate.
Optionally, for the production method of the groove power device, the blanket dielectric layer further includes described in covering
The third dielectric layer of second dielectric layer.
Optionally, for the production method of the groove power device, the material of the second dielectric layer is to undope
Silica, silicon nitride, silicon oxynitride one or more combinations；The material of the third dielectric layer is boron-phosphorosilicate glass.
Optionally, for the production method of the groove power device, the second dielectric layer and third dielectric layer are all
It is formed by chemical vapor deposition process.
Optionally, for the production method of the groove power device, the reaction source gas of the third dielectric layer is formed
Including SiH4、B2H6And/or PH3；The mass percent of boron is 1~5% in the third dielectric layer, and the mass percent of phosphorus is 2
~6%.
Optionally, for the production method of the groove power device, the second dielectric layer with a thickness ofThe third dielectric layer with a thickness of
Optionally, for the production method of the groove power device, the extension of the side wall and bottom wall of the contact hole
Line is in 80 ° of -89 ° of angles, and the depth of the contact hole is less than or equal to 1 μm.
Optionally, for the production method of the groove power device, the contact hole bottom formed p type island region it
Afterwards, further includes:
Metal layer is formed in the blanket dielectric layer, the metal layer fills the contact hole；And
Passivation layer is formed on the metal layer.
The present invention also provides a kind of groove power devices, comprising:
Semiconductor substrate；
First groove and second groove in the semiconductor substrate；
Gate dielectric layer in the semiconductor substrate and on the side wall and bottom wall of the first groove and second groove；
Gate material layers in the first groove and second groove are located in the first groove and second groove
Gate material layers on first medium layer；
The p-well of first groove and second groove two sides in the semiconductor substrate；
N-type region in p-well described in first groove in the semiconductor substrate and second groove two sides；
The first trapping layer in the semiconductor substrate is formed with opening in first trapping layer to expose
Semiconductor substrate and part second groove are stated, and first trapping layer covers the first groove；
Blanket dielectric layer in the semiconductor substrate and on covering first trapping layer；
Contact hole, the contact hole is through the blanket dielectric layer, the first trapping layer, gate dielectric layer and semiconductor lining
Bottom, the contact hole are located in the first groove two sides and the second groove, and the width of the opening is the contact hole
In the minimum dimension of the semiconductor substrate surface；
Positioned at the p type island region of the contact hole bottom.
Optionally, for the groove power device, the material of first trapping layer is silicon nitride and/or nitrogen oxidation
Silicon.
Optionally, for the groove power device, first trapping layer with a thickness of
Optionally, for the groove power device, the width of the first groove is 0.05 μm -1 μm, and depth is
0.1μm-10μm；The width of the second groove is 0.5 μm -5 μm, and depth is 0.1 μm -50 μm.
Optionally, for the groove power device, the width of the opening is 0.02 μm -2 μm, less than adjacent the
Spacing between one groove, and it is less than the width of the second groove.
Optionally, for the groove power device, the gate material layers upper surface is lower than the semiconductor substrate
The distance on surface is less than or equal to 0.8 μm.
Optionally, for the groove power device, the material of the first medium layer be silica, silicon nitride,
One or more combinations of silicon oxynitride, polysilicon.
Optionally, for the groove power device, the blanket dielectric layer includes covering the semiconductor substrate
Second dielectric layer.
Optionally, for the groove power device, the blanket dielectric layer further includes covering the second dielectric layer
Third dielectric layer.
Optionally, for the groove power device, the material of the second dielectric layer be the silica to undope,
One or more combinations of silicon nitride, silicon oxynitride；The material of the third dielectric layer is boron-phosphorosilicate glass.
Optionally, for the groove power device, the mass percent of boron is 1~5% in the third dielectric layer,
The mass percent of phosphorus is 2~6%.
Optionally, for the groove power device, the second dielectric layer with a thickness ofIt is described
Third dielectric layer with a thickness of
Optionally, for the groove power device, the side wall of the contact hole and the extended line of bottom wall are in 80 ° -89 °
The depth at angle, the contact hole is less than or equal to 1 μm.
Optionally, for the groove power device, further includes:
Metal layer in the blanket dielectric layer, the metal layer fill the contact hole；And
Passivation layer on the metal layer.
Compared with prior art, a kind of groove power device provided by the invention and production method, by first groove
Being formed with the top of second groove has certain thickness first medium layer, so that trench-gate region distance semiconductor substrate surface
There is certain distance, then deposit the first trapping layer and define contact hole in the minimum dimension of semiconductor substrate surface, thus carrying out
When contact hole etching, the line width of contact hole can be made further to do smaller, and guarantee contact hole to first groove and second
The spacing of groove realizes smaller line width so that the set of contact hole and first groove and second groove be made to be carved with enough surpluses
The production of device architecture, while meet the requirements the parameter of product and reliability.
Detailed description of the invention
The problem of Fig. 1 is easy to appear under lithographic equipment limit capacity for MOSFET in groove power device in the prior art
Schematic diagram；
Fig. 2 is the flow chart of the groove power device production method in one embodiment of the invention；
Fig. 3-12 is the structural schematic diagram in the manufacturing process of the groove power device in one embodiment of the embodiment of the present invention.
Specific embodiment
Groove power device and production method of the invention are described in more detail below in conjunction with schematic diagram, wherein
Illustrating the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still
So realize advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art,
And it is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The present invention provides a kind of groove power device and production method, the production method of the groove power device include:
Step S11, semiconductor substrate is provided；
Step S12, first groove and second groove are formed in the semiconductor substrate；
Step S13, it grows on the semiconductor substrate and on the side wall and bottom wall of the first groove and second groove
Gate dielectric layer；
Step S14, gate material layers are formed in the first groove and second groove；
Step S15, first medium layer is formed in the gate material layers in the first groove and second groove；
Step S16, first groove and second groove two sides form p-well in the semiconductor substrate；
Step S17, N-type region is formed in p-well described in first groove and second groove two sides in the semiconductor substrate；
Step S18, the first trapping layer is formed on the semiconductor substrate, and opening is formed in first trapping layer
To expose the semiconductor substrate and part second groove, and first trapping layer covers the first groove；
Step S19, blanket dielectric layer is formed on the semiconductor substrate；
Step S20, photoetching and the blanket dielectric layer is etched into the semiconductor substrate, form the contact hole, institute
It states contact hole to be located in first groove two sides and second groove, the width of the opening is that the contact hole is served as a contrast in the semiconductor
The minimum dimension of bottom surface；
Step S21, p type island region is formed in the contact hole bottom.
It describes in detail below incorporated by reference to Fig. 2 and Fig. 3-12 pairs of groove power device and production method of the invention.
Firstly, step S11 is executed, as shown in figure 3, providing semiconductor substrate 20.Preferably, the semiconductor substrate 20 can
To be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate or well known to a person skilled in the art other semiconductor materials
Substrate, using silicon substrate in the present embodiment.Further, the silicon substrate used in the present embodiment could be formed with MOSFET
The semiconductors such as (Metal Oxide Semiconductor Field Effect Transistor), IGBT (isolated-gate field effect transistor (IGFET)), Schottky diode
Device.The semiconductor substrate 20 can also carry out the N-type and p-type doping of certain impurity level according to the characteristic of required product.
As a unrestricted example, as shown in figure 3, forming the second trapping layer in the semiconductor substrate 20
21.Second trapping layer 21 formed in semiconductor substrate 20 can be used the means such as oxidation or deposit and be formed.For example, described
Second trapping layer 21 can be one or more combinations of the materials such as silica, silicon nitride, silicon oxynitride, polysilicon.Preferably
, second trapping layer 21 with a thickness of
Then, step S12 is executed, forms first groove 221 and second groove 222 in the semiconductor substrate 20.Please
With reference to Fig. 4,221 region of first groove is first window area 22a, and 222 region of second groove is the second window region
22b.The first window area 22a refers to the primitive unit cell area of power device, and the second window region 22b refers to the terminal of power device
Area.
This step S12 is sheltered using photoresist by the selectively opened window of photoetching, by open window region from upper past
It after lower etching second trapping layer 21 to the greatest extent, is further continued for going deep into etch semiconductor substrates 20, there is one fixed width and depth to be formed
The first groove 221 and second groove 222 of degree.Wherein, the layout of the first groove 221 and second groove 222 can be according to production
Product structure and design, the width of the first groove 221 and second groove 222 can be according to product structure and technological ability come really
Fixed, depth can be determined according to parameters such as the pressure resistances of product.
Further, in the present embodiment, the width of the first groove 221 and second groove 222 of formation 0.05 μm-
Between 5 μm, depth is between 0.1 μm -50 μm.Specifically, for the first groove 221 in first window area 22a, width
L1 can be connected density according to product and determine, minimum feature can be more than or equal to the limit capacity of equipment, and L1 can be 0.05 μm -1 μm；
Depth h1 can determine that h1 can be 0.1-10 μm according to parameters such as the pressure resistances of product.For second in the second window region 22b
Groove 222, it is contemplated that will fill polysilicon in its slot, width needs meet the needs of carrying high pressure, high current, thus width compared with
Width, also need on part-structure pit in fairlead, therefore the width L2 of second groove 222 are set on the polysilicon filled
Want wide compared with first groove 221, L2 can be 0.5 μm -5 μm；It is identical according to etching load effect in the case where wider width
Etch application it is deeper to big line width region etch depth, therefore h2 > h1 under normal circumstances, h2 can be 0.1 μm -50 μm.It needs
It is noted that simple can not show that first groove 221 and 222 depth width of second groove are consistent according to attached drawing
Conclusion.
Preferably, and then executing step S121,221 He of first groove is aoxidized at a temperature of 1000 DEG C -1200 DEG C
The side wall and bottom wall of second groove 222 form the first oxide layer (not shown), to the first groove 221 and the second ditch
The side wall and bottom wall of slot 222 are repaired.The thickness range of first oxide layer is
Then step S122 is executed, first oxide layer and second trapping layer 21 are removed.If described second prevents
The material of layer 21 is silica, then can be removed using BOE corrosive liquid or DHF (diluted hydrofluoric acid).
Then step S13 is executed, as shown in figure 5, in the present embodiment, in the semiconductor substrate 20 and first ditch
Gate dielectric layer 23 is grown on slot 221 and the side wall and bottom wall of second groove 222.For example, the gate dielectric layer 23 can be grid oxygen,
Specifically, the gate dielectric layer 23 use mix oxychloride (i.e. containing chlorine, oxygen atmosphere under aoxidized) formed, in temperature model
It encloses and is grown for 1000 DEG C -1200 DEG C, be to obtain thickness rangeGate dielectric layer 23.The grid dielectric
The growth temperature more high quality of layer 23 is better, and impurity in gate dielectric layer 23 can be effectively reduced by mixing oxychloride, improves grid dielectric
The quality of layer 23.
Then, step S14 is executed, forms gate material layers 24, example in the first groove 221 and second groove 222
It such as can be doped polysilicon layer.The polysilicon that undopes can be first deposited, the polysilicon that undopes is carried out using ion implanting afterwards
Doping；The polysilicon alternatively, first deposit undopes, is afterwards doped it using phosphorus pre-deposited technique；Again alternatively, being deposited using side
The doping way in situ of polysilicon side doping.
As shown in fig. 6, generating the gate material layers on 20 surface of semiconductor substrate when removal deposit, and make described
Gate material layers 24 in first groove 221 and second groove 222 are lower than 20 surface of semiconductor substrate, this process can be with
It is completed using the dry etching with isotropic.The upper surface of the gate material layers 24 is lower than the semiconductor substrate 20
The distance h3 on surface can be less than or equal to 0.8 μm.Termination environment is using placement grid in sipes (i.e. second groove 222) as a result,
The mode of pole material layer completes device terminal pressure resistance and grid lead in deep trouth, to reduce semiconductor substrate surface
The flatness of step difference guarantee silicon chip surface；Make lead genesis analysis simultaneously, reduces the area of chip surface.
It should be noted that due to foring gate dielectric layer 23 (grid oxygen) before, and need to carry out ion implanting later, because
This, if the thickness of gate dielectric layer 23 is greater thanThe grid material on 20 surface of semiconductor substrate is generated when removing deposit
And then the part that the gate dielectric layer 23 is located at 20 surface of semiconductor substrate is removed after the bed of material.For the gate dielectric layer 23
Thickness is greater thanWhen, it can be generated after the gate material layers on 20 surface of semiconductor substrate immediately when removing deposit
The thinned gate dielectric layer 23 be located at part to the gate dielectric layer 23 on 20 surface of semiconductor substrate and be located at semiconductor substrate
The thickness of the part on 20 surfaces is less than or equal toIf the thickness of the gate dielectric layer 23 is less than or equal toIt is removing
It is generated when deposit and retains the gate dielectric layer 23 after the gate material layers on 20 surface of semiconductor substrate.Certainly, the grid
Whether dielectric layer 23 removes can be determined according to actual conditions, and after the removal of gate dielectric layer 23, subsequent needs are re-formed,
Specifically, after formation grid oxygen is removed before for example, it is subsequent to need to form pad oxygen, ion implanting is carried out with auxiliary and completes p-well and N
The formation in type area.As shown in fig. 6, the portion that the present embodiment is located at 20 surface of semiconductor substrate using the gate dielectric layer 23 is removed
Point.
Then, step S15, incorporated by reference to Fig. 7, the gate material layers in the first groove 221 and second groove 222 are executed
First medium layer 25 is formed on 24.The material of the first medium layer 25 can be silica, silicon nitride, silicon oxynitride, more
One or more combinations of crystal silicon etc., are formed using techniques such as such as CVD.
Then, the first medium layer on 20 surface of semiconductor substrate is generated when removal deposit, makes first ditch
The first medium layer 25 filled at the top of slot 221 and second groove 222 is flushed with 20 surface of semiconductor substrate.Specifically, can
It is completed, can also be planarized using chemically mechanical polishing (CMP) using the dry etching with isotropic.
And then, step S16 is executed, incorporated by reference to shown in Fig. 8, the first groove 221 and the in the semiconductor substrate 20
Two grooves, 222 two sides form p-well 26a.Specifically, the case where for removing gate dielectric layer in the present invention, first in institute
It states growth pad oxygen 26 in semiconductor substrate 20 and is used as gate dielectric layer.Preferably, the thickness range of the pad oxygen 26 can beThen first groove 221 and 222 two sides of second groove carry out the first secondary ion in the semiconductor substrate 20
Injection and annealing, form p-well 26a, and the junction depth depth of the p-well 26a is less than the depth of first groove 221.The first time from
Son is injected and is annealed into and injected using boron (B) ion zero angle, Implantation Energy 60KeV-150KeV, implantation dosage 1E13/
cm2-1E15/cm2, annealing temperature is 1000 DEG C -1200 DEG C.
Later, step S17, please continue to refer to shown in Fig. 8,221 He of first groove in the semiconductor substrate 20 are executed
N-type region 26b is formed on p-well 26a described in 222 two sides of second groove.Specifically, can be first in the semiconductor substrate 20
Groove 221 and 222 two sides of second groove carry out second of ion implanting and annealing, form N-type region 26b, the N-type region 26b's
Junction depth depth h4 is greater than the gate material layers 24 in the first groove 221 and second groove 222 apart from the semiconductor substrate
The distance (i.e. h3) on 20 surfaces.It second of ion implanting and is annealed into using phosphorus (P) ion or arsenic (As) ion zero angle
Injection, Implantation Energy 60KeV-150Kev, implantation dosage 1E14/cm2-1E16/cm2, 800 DEG C -1100 DEG C of annealing temperature.By
The implantation dosage of step S16 and step S17 it is found that formed N-type region 26b doping concentration be greater than p-well 26a doping concentration,
Therefore the N-type region 26b is N-type heavily doped region.
Later, step S18 is executed, referring to FIG. 9, the first trapping layer 27 is formed in the semiconductor substrate 20, and
Opening is formed in first trapping layer 27 to expose the semiconductor substrate 20 and part second groove 222, and described the
One trapping layer 27 covers the first groove 211, and the opening width L3 is contact hole on 20 surface of semiconductor substrate
Minimum dimension.It is understood that due to foring pad oxygen 26 before, what the opening directly exposed is pad oxygen 26.
The material of first trapping layer 27 is silicon nitride or silicon oxynitride, and thickness can beThe opening
It can be completed via lithographic etch process, the opening width L3 can in conjunction with specific requirements and photolithographic minimum dimension ability and most
Good alignment precision exposure is common to be completed.
Moreover, being open on first trapping layer 27,27 surface smoothness of the first trapping layer is allowed for
Height, structure is simple, and photo-etching machine exposal condition is best, can define the smallest contact pore size (i.e. opening width L3).The ruler
It is very little depending on specific exposure sources ability, such as can be 0.02 μm -2 μm, preferably, be less than adjacent first trenches 221 it
Between spacing, and be less than the second groove 222 width.The first trapping layer 27 positioned at the first groove 221 top
Width L4 is then greater than the width L1 of the first groove 221, and realization shelters from first groove 221 completely.So, in primitive unit cell area
Described in 221 outside spacing of extended distance first groove be respectively d4, d5, wherein d4, d5 are all satisfied product design and equipment set
It carves and requires.Likewise, 222 inside gate dielectric layer of extended distance second groove, 23 spacing described in termination environment is respectively d6, d7,
Middle d6, d7 are all satisfied product design and equipment alignment requirement.
Later, step S19 is executed, referring to FIG. 10, blanket dielectric layer is formed in the semiconductor substrate 20, it is described to cover
Lid dielectric layer covers first trapping layer 27.Specifically, in the present embodiment, the blanket dielectric layer includes opening described in covering
The third dielectric layer 28b of the second dielectric layer 28a and the covering second dielectric layer 28a of mouth.The material of the second dielectric layer 28a
Material can be one kind or combinations thereof of silica, silicon nitride, silicon oxynitride to undope etc., be formed using techniques such as CVD.Institute
The thickness for stating second dielectric layer 28a can beThe third dielectric layer 28b is BPSG (boron-phosphorosilicate glass),
Thickness can beIt can equally be formed using CVD technique.Specifically, the third dielectric layer 28b
Reaction source gas includes SiH4、B2H6And/or PH3Deng.Specifically, the mass percent of B is 1 in the third dielectric layer 28b
The mass percent of~5%, P are 2~6%.
Further, being also possible to the blanket dielectric layer is only to cover the second dielectric layer of first trapping layer 27
28a。
Further, it if the second dielectric layer 28a uses silicon nitride, can be utilized in the production of subsequent contact hole
The selection of second dielectric layer 28a, third dielectric layer 28b and silicon enable trench region to be protected than difference, further existing
Have and realize smaller line width and bigger alignment surplus under the conditions of lithographic equipment, to realize the life of the device architecture of smaller line width
It produces.
Then, step S20 is executed, please refers to Figure 11, photoetching simultaneously etches the blanket dielectric layer to the semiconductor substrate
In 20, contact hole 29 is formed, the contact hole 29 is located in 221 two sides of first groove and second groove 222, the width of the opening
Degree is minimum dimension of the contact hole 29 on 20 surface of semiconductor substrate.As shown in Figure 11, the contact hole 29 etched
Substantially inverted trapezoidal, i.e. shape with wide top and narrow bottom, the width of 29 bottom of contact hole are L7, and top opening width is L6, and middle part is by first
Minimum dimension defined by trapping layer 27 on 20 surface of semiconductor substrate is L3, and meets L7 < L3 < L6.Wherein, the contact
The side wall in hole 29 and the angle theta of bottom wall extended line are 80 °~89 °, and depth h5 is less than or equal to 1 μm.After the formation of contact hole 29,
Primitive unit cell area forms third window region 30a, forms the 4th window region 30b in termination environment.
This step S20 is specially to be sequentially etched third dielectric layer 28b, after second dielectric layer 28a and pad oxygen 26, continues to etch
Semiconductor substrate 20 obtains depth and is the step of h5, so that the semiconductor substrate for being doped to N-type is etched away into a part,
Make subsequent p-type injection that can penetrate N-type region.
Specifically, source region of the region of contact hole 29 between slot and slot is provided in the third window region 30a, as primitive unit cell
The source in area connects metal；Pressure ring or grid of the region as device of contact hole 29 are provided in the 4th window region 30b
(Gate-PAD) end connection metal.
More specifically, in conjunction with Fig. 1, Fig. 3 and Figure 11, the third dielectric layer 28b top width of primitive unit cell area shown in Figure 11 is L5,
Its width is greater than the width L1 of first groove 221 in Fig. 3, the top of first groove 221 can be made by the protection of dielectric layer, no
The problems such as being easy to produce GS electric leakage.
More specifically, contact hole top opening width is L6 in primitive unit cell area shown in Figure 11, this usual width represents
The Limit Width of contact hole photoetching.
More specifically, in primitive unit cell area shown in Figure 11 contact hole 27 position width of the first trapping layer be L3, this width
L3 is exactly minimum dimension of the minimal-contact hole in semiconductor substrate surface of the definition.
More specifically, when second dielectric layer 28a, third dielectric layer 28b are oxide layer materials, contact hole quarter is being carried out
When losing program and arriving semiconductor substrate, even if due to expose and to inclined ability it is poor, there is contact hole and do greatly, to inclined situation,
Etching can also be stopped when being etched to the first trapping layer 27, only etch the unlapped contact bore region of the first trapping layer 27, have
Effect avoids contact with hole line width and becomes larger, inclined situation occurs.
More specifically, first groove 221 and the top of second groove 222 be due to adulterating non-conductive first medium layer 25, because
Under electrical namely first groove 221 and second groove 222 are not embodied only in this first groove 221 and 222 top of second groove
The operation of subparticipation device, therefore 29 effective coverage of contact hole of device is effective line width near 29 bottom section of contact hole
For L7.The characteristic that pattern is tilted in conjunction with contact hole 29, along with due to the certain thickness of first groove 221 and 222 top of second groove
The filling of the first medium layer 25 of degree makes L7 be less than L3, and far smaller than L6 to form deeper contact hole, thus existing
Smaller line width and bigger alignment surplus are realized under the conditions of some lithographic equipments, to realize the life of the device architecture of smaller line width
It produces.
Then, step S21 is executed, please continue to refer to Figure 11, forms p type island region 29a in 29 bottom of contact hole.Specifically
, third time ion implanting and annealing are carried out, the p type island region 29a is formed.The third time ion implanting is using zero degree subscript
Enter B11 or BF2, can first inject B11 and reinject BF2, Implantation Energy 20KeV-100KeV, implantation dosage 1E14/cm2-
1E16/cm2；It is annealed at 500 DEG C -1000 DEG C using boiler tube or short annealing.By the injection of step S16 and step S21
Dosage is it is found that the doping concentration of the p type island region 29a formed is greater than the doping concentration of p-well 26a, therefore the p type island region 29a is p-type
Heavily doped region.
Then, step S22 is executed, Figure 12 is please referred to, forms metal layer 31, the gold on the third dielectric layer 28b
Belong to layer 31 and fills the contact hole.Specifically, the material of the metal layer 31 can be titanium (Ti), titanium nitride (TiN), titanium silicide
(TiSi), metals or the gold such as tungsten (W), aluminium (Al), silicated aluminum (AlSi), copper silmin (AlSiCu), copper (Cu) or nickel (Ni)
The compound of category, thickness can be 1 μm -8 μm.After the formation of metal layer 31, a step etching technics is executed, for example, by using dry method
Etching obtains the 5th window region 31a in primitive unit cell area and the 6th window region 31b of termination environment.
Further, it can also need to increase passivation layer protection according to product, complete the processing of device Facad structure, and
Final device architecture is completed by being thinned, carrying on the back a series of postchannel process such as gold, scribing.
In conjunction with Fig. 3-Figure 12 as it can be seen that the groove power device that the present invention obtains, comprising:
Semiconductor substrate 20；
First groove 221 and second groove 222 in the semiconductor substrate 20；Preferably, the first groove
221 width L1 is 0.05 μm -1 μm, and depth h1 is 0.1 μm -10 μm；The width L2 of the second groove 222 is 0.5 μm of -5 μ
M, depth h1 are 0.1 μm -50 μm；
In the semiconductor substrate 20 and on the side wall and bottom wall of the first groove 221 and second groove 222
Gate dielectric layer 23, specifically, being pad oxygen 26 in the semiconductor substrate 20, in the first groove 221 and second groove 222
Side wall and bottom wall on be grid oxygen；It is of course also possible to all be grid oxygen or other feasible film layers；The thickness of the gate dielectric layer 23
Degree is
Gate material layers 24 in the first groove 221 and second groove 222 are located at the first groove 221
With the first medium layer 25 in the gate material layers 24 in second groove 222；Preferably, 24 upper surface of gate material layers is low
Distance h3 in 20 surface of semiconductor substrate is less than or equal to 0.8 μm；Preferably, the material of the first medium layer 25 is
One or more combinations of silica, silicon nitride, silicon oxynitride, polysilicon；
The p-well 26a of 222 two sides of first groove 221 and second groove in the semiconductor substrate 20；
Positioned at the N-type in the semiconductor substrate 20 on the p-well 26a of 222 two sides of first groove 221 and second groove
The junction depth depth of area 26b, the p-well 26a are less than the depth of first groove 221, and the junction depth depth of the N-type region 26b is greater than institute
State distance of the gate material layers 24 apart from 20 surface of semiconductor substrate in first groove 221 and second groove 222；
The first trapping layer 27 in the semiconductor substrate 20 is formed with opening in first trapping layer 27 with sudden and violent
Expose the semiconductor substrate 20 and part second groove 222, and first trapping layer 27 covers the first groove 221；
Preferably, the material of first trapping layer 27 be silicon nitride and/or silicon oxynitride, first trapping layer 27 with a thickness of
Blanket dielectric layer in the semiconductor substrate 20 and on covering first trapping layer 27；The covering is situated between
Matter layer includes the third medium for covering the second dielectric layer 28a and the covering second dielectric layer 28a of first trapping layer 27
Layer 28b, the material of the second dielectric layer 28a is one kind or its group of the silica to undope, silicon nitride, silicon oxynitride
It closes；The material of the third dielectric layer 28b is boron-phosphorosilicate glass, in the third dielectric layer 28b mass percent of boron be 1~
5%, the mass percent of phosphorus is 2~6%, preferably, the second dielectric layer 28a with a thickness ofIt is described
Third dielectric layer 28b with a thickness ofCertainly, the blanket dielectric layer can also be only second dielectric layer
28a；
Contact hole 29, the contact hole 29 is through the blanket dielectric layer, the first trapping layer 27, gate dielectric layer 23 and described
Semiconductor substrate 20, the contact hole 29 is located in 221 two sides of first groove and the second groove 222, wherein first
The width of the opening of trapping layer 27 is minimum dimension of the contact hole 29 on 20 surface of semiconductor substrate；The opening
Width is 0.02 μm -2 μm, less than the spacing between adjacent first groove 221, and is less than the width of the second groove 222；
Preferably, the side wall of the contact hole 29 and the extended line of bottom wall are in 80 ° of -89 ° of angles, the depth of the contact hole 29 is less than or equal to
1μm；
P type island region 29a positioned at 29 bottom of contact hole；
Metal layer 31 in the blanket dielectric layer, the metal layer 31 fill the contact hole 29；Preferably, institute
The material for stating metal layer 31 is metals or the metals such as titanium, titanium nitride, titanium silicide, tungsten, aluminium, silicated aluminum, copper silmin, copper or nickel
Compound；And
Passivation layer on the metal layer 31.
A kind of groove power device provided by the invention and production method as a result, by first groove and second groove
Top formed have certain thickness first medium layer so that trench-gate region distance semiconductor substrate surface has a spacing
From, then deposit the first trapping layer and define contact hole in the minimum dimension of semiconductor substrate surface, thus carrying out contact hole quarter
When erosion, the line width of contact hole can be made further to do smaller.And guarantee contact hole between first groove and second groove
Away from so that the set of contact hole and first groove and second groove be made to be carved with enough surpluses, the device architecture of the smaller line width of realization
Production, while meet the requirements the parameter of product and reliability.
Further, a kind of trench power device structure of the invention and production method, can be used in including but it is unlimited
In the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (34)
1. a kind of production method of groove power device, comprising:
Semiconductor substrate is provided；
First groove and second groove are formed in the semiconductor substrate；
Grow gate dielectric layer on the semiconductor substrate and on the side wall and bottom wall of the first groove and second groove；
Gate material layers are formed in the first groove and second groove；
First medium layer is formed in the gate material layers in the first groove and second groove；
First groove and second groove two sides form p-well in the semiconductor substrate；
N-type region is formed in p-well described in first groove and second groove two sides in the semiconductor substrate；
The first trapping layer is formed on the semiconductor substrate, and formation opening is described to expose in first trapping layer
Semiconductor substrate and part second groove, and first trapping layer covers the first groove；
Blanket dielectric layer is formed on the semiconductor substrate；
Photoetching simultaneously etches the blanket dielectric layer into the semiconductor substrate, forms the contact hole of shape with wide top and narrow bottom, described to connect
Contact hole is located in first groove two sides and second groove, and the width of the opening is the contact hole in the semiconductor substrate table
The minimum dimension in face；
P type island region is formed in the contact hole bottom.
2. the production method of groove power device as described in claim 1, which is characterized in that the material of first trapping layer
For silicon nitride and/or silicon oxynitride.
3. the production method of groove power device as claimed in claim 1 or 2, which is characterized in that first trapping layer
With a thickness of
4. the production method of groove power device as described in claim 1, which is characterized in that the width of the first groove is
0.05 μm -1 μm, depth is 0.1 μm -10 μm；The width of the second groove is 0.5 μm -5 μm, and depth is 0.1 μm -50 μm.
5. the production method of groove power device as claimed in claim 4, which is characterized in that the width of the opening is 0.02
μm -2 μm, less than the spacing between adjacent first groove, and it is less than the width of the second groove.
6. the production method of groove power device as described in claim 1, which is characterized in that formed in the semiconductor substrate
There is the second trapping layer.
7. the production method of groove power device as claimed in claim 6, which is characterized in that the material of second trapping layer
For one or more combinations of silica, silicon nitride, silicon oxynitride, polysilicon.
8. the production method of groove power device as claimed in claim 6, which is characterized in that the thickness of second trapping layer
For
9. the production method of groove power device as claimed in claim 6, which is characterized in that shape in the semiconductor substrate
After first groove and second groove, before growing gate dielectric layer, further includes:
The first oxide layer is formed in the side wall and bottom wall of the first groove and second groove；
Remove first oxide layer and second trapping layer.
10. the production method of groove power device as described in claim 1, which is characterized in that in the first groove and
It is formed after gate material layers in two grooves, forms first medium in gate material layers in the first groove and second groove
Before layer, further includes:
The gate material layers on the semiconductor substrate surface are generated when removal deposit, and make the first groove and the second ditch
Gate material layers in slot are lower than the semiconductor substrate surface.
11. the production method of groove power device as claimed in claim 10, which is characterized in that table in the gate material layers
Face is less than or equal to 0.8 μm lower than the distance of the semiconductor substrate surface.
12. the production method of groove power device as described in claim 1, which is characterized in that the material of the first medium layer
Matter is one or more combinations of silica, silicon nitride, silicon oxynitride, polysilicon.
13. the production method of groove power device as described in claim 1, which is characterized in that the blanket dielectric layer includes
Cover the second dielectric layer of the semiconductor substrate.
14. the production method of groove power device as claimed in claim 13, which is characterized in that the blanket dielectric layer is also wrapped
Include the third dielectric layer for covering the second dielectric layer.
15. the production method of groove power device as claimed in claim 14, which is characterized in that the material of the second dielectric layer
Material is one or more combinations of the silica, silicon nitride, silicon oxynitride that undope；The material of the third dielectric layer is boron
Phosphorosilicate glass.
16. the production method of groove power device as claimed in claim 14, which is characterized in that the second dielectric layer and
Three dielectric layers are all formed by chemical vapor deposition process.
17. the production method of groove power device as claimed in claim 16, which is characterized in that form the third dielectric layer
Reaction source gas include SiH4、B2H6And/or PH3；The mass percent of boron is 1~5% in the third dielectric layer, the matter of phosphorus
Measuring percentage is 2~6%.
18. the production method of groove power device as claimed in claim 14, which is characterized in that the thickness of the second dielectric layer
Degree isThe third dielectric layer with a thickness of
19. the production method of groove power device as described in claim 1, which is characterized in that the side wall of the contact hole with
The extended line of bottom wall is in 80 ° of -89 ° of angles, and the depth of the contact hole is less than or equal to 1 μm.
20. the production method of groove power device as described in claim 1, which is characterized in that in contact hole bottom shape
After p type island region, further includes:
Metal layer is formed in the blanket dielectric layer, the metal layer fills the contact hole；And
Passivation layer is formed on the metal layer.
21. a kind of groove power device, comprising:
Semiconductor substrate；
First groove and second groove in the semiconductor substrate；
Gate dielectric layer in the semiconductor substrate and on the side wall and bottom wall of the first groove and second groove；
Gate material layers in the first groove and second groove, the grid in the first groove and second groove
First medium layer in the material layer of pole；
The p-well of first groove and second groove two sides in the semiconductor substrate；
N-type region in p-well described in first groove in the semiconductor substrate and second groove two sides；
The first trapping layer in the semiconductor substrate is formed with opening in first trapping layer to expose described half
Conductor substrate and part second groove, and first trapping layer covers the first groove；
Blanket dielectric layer in the semiconductor substrate and on covering first trapping layer；
The contact hole of shape with wide top and narrow bottom, the contact hole is through the blanket dielectric layer, the first trapping layer, gate dielectric layer and described
Semiconductor substrate, the contact hole are located in the first groove two sides and the second groove, and the width of the opening is institute
Contact hole is stated in the minimum dimension of the semiconductor substrate surface；
Positioned at the p type island region of the contact hole bottom.
22. groove power device as claimed in claim 21, which is characterized in that the material of first trapping layer is silicon nitride
And/or silicon oxynitride.
23. the groove power device as described in claim 21 or 22, which is characterized in that first trapping layer with a thickness of
24. groove power device as claimed in claim 21, which is characterized in that the width of the first groove is 0.05 μm -1
μm, depth is 0.1 μm -10 μm；The width of the second groove is 0.5 μm -5 μm, and depth is 0.1 μm -50 μm.
25. groove power device as claimed in claim 24, which is characterized in that the width of the opening is 0.02 μm -2 μm,
Less than the spacing between adjacent first groove, and it is less than the width of the second groove.
26. groove power device as claimed in claim 21, which is characterized in that the gate material layers upper surface is lower than described
The distance of semiconductor substrate surface is less than or equal to 0.8 μm.
27. groove power device as claimed in claim 21, which is characterized in that the material of the first medium layer is titanium dioxide
One or more combinations of silicon, silicon nitride, silicon oxynitride, polysilicon.
28. groove power device as claimed in claim 21, which is characterized in that the blanket dielectric layer includes covering described half
The second dielectric layer of conductor substrate.
29. groove power device as claimed in claim 28, which is characterized in that the blanket dielectric layer further includes described in covering
The third dielectric layer of second dielectric layer.
30. groove power device as claimed in claim 29, which is characterized in that the material of the second dielectric layer is to undope
Silica, silicon nitride, silicon oxynitride one or more combinations；The material of the third dielectric layer is boron-phosphorosilicate glass.
31. groove power device as claimed in claim 30, which is characterized in that the quality percentage of boron in the third dielectric layer
Than being 1~5%, the mass percent of phosphorus is 2~6%.
32. groove power device as claimed in claim 29, which is characterized in that the second dielectric layer with a thickness ofThe third dielectric layer with a thickness of
33. groove power device as claimed in claim 21, which is characterized in that the extension of the side wall and bottom wall of the contact hole
Line is in 80 ° of -89 ° of angles, and the depth of the contact hole is less than or equal to 1 μm.
34. groove power device as claimed in claim 21, which is characterized in that further include:
Metal layer in the blanket dielectric layer, the metal layer fill the contact hole；And
Passivation layer on the metal layer.
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| CN104538452A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Structure of groove type MOSFET and manufacturing method |
| CN205911285U (en) * | 2016-07-12 | 2017-01-25 | 杭州士兰集成电路有限公司 | Slot power device |
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| CN104538452A (en) * | 2014-12-29 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Structure of groove type MOSFET and manufacturing method |
| CN205911285U (en) * | 2016-07-12 | 2017-01-25 | 杭州士兰集成电路有限公司 | Slot power device |
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