CN103021867B - The forming method of trench metal-oxide-semicondbarrier barrier Schottky - Google Patents
The forming method of trench metal-oxide-semicondbarrier barrier Schottky Download PDFInfo
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- CN103021867B CN103021867B CN201210564065.XA CN201210564065A CN103021867B CN 103021867 B CN103021867 B CN 103021867B CN 201210564065 A CN201210564065 A CN 201210564065A CN 103021867 B CN103021867 B CN 103021867B
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- 230000004888 barrier function Effects 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 238000005530 etching Methods 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- -1 silicon-oxygen nitride Chemical class 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical group [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 claims 1
- 239000011574 phosphorus Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 187
- 238000005036 potential barrier Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses the forming method of a kind of trench metal-oxide barrier potential of a semiconductor schottky device, in the method, Schottky Barrier Contact opening is to utilize the first etching and second two steps of etching to be formed, and structure is detected as etching terminal in barrier layer in the first etch step, the accurate control of the first etching etching terminal therefore can be realized；In addition, it is not necessary that measure the thickness of dielectric layer and utilize different etch periods to carry out the first etching according to the difference measuring thickness so that the forming method of Schottky Barrier Contact opening is the simplest.Owing to the first etching can stop over the barrier layer exactly, therefore only by controlling the degree of depth that the second etch process parameters i.e. can determine that the part of Schottky Barrier Contact opening entrance semiconductor region in the second etch step after the first etch step, the degree of depth making the part of Schottky Barrier Contact opening entrance semiconductor region can be precisely controlled, and then improves the stability of the performance of device.
Description
Technical field
The invention belongs to semiconductor power device (Power Device) field, particularly relate to a kind of groove
(Trench MOS Barrier Schottky is called for short type Metal-oxide-semicondutor barrier schottky device
TMBS) forming method.
Background technology
Along with the development of semiconductor technology, power device, as a kind of new device, widely should
For the field such as disk drive, automotive electronics.Power device is required to bear bigger voltage, electric current
And power termination.And the devices such as existing MOS transistor cannot meet the demand, therefore, in order to full
The needs of foot application, various power devices become focus of attention.
In order to improve the friendship frequency characteristic of power device, a kind of the most universal method is at groove crystal
Integrated schottky potential barrier in pipe.
Below in conjunction with Fig. 1 to Fig. 5 to existing a kind of trench metal-Oxidc-Semiconductor barrier schottky device
The forming method of part is briefly described:
As shown in Figure 1, it is provided that N+Type Semiconductor substrate 1, Semiconductor substrate 1 includes trench transistor district
Territory 1a and Schottky barrier area 1b, Semiconductor substrate 1 is formed with N-Type epitaxial layer 2, epitaxial layer 2
Surface is formed with P type trap zone 3, and the part in addition to well region 3 of epitaxial layer 2 is epitaxial layer 2a, groove
The first groove 4, the epitaxial layer of Schottky barrier area 1b it is formed with on the epitaxial layer 2 of transistor area 1a
Being formed with the second groove 5 on 2, the opening of the first groove 4 and the second groove 5 is arranged on epitaxial layer 2 surface
S, bottom are positioned at the epitaxial layer 2a below well region 3, and sidewall and the bottom of the first groove 4 are coated with two
Silicon oxide layer 7, is filled with polysilicon layer 6, the sidewall of the second groove 5 and bottom and covers in the first groove 4
There is silicon dioxide layer 9, in the second groove 5, be filled with polysilicon layer 8, the well region 3 of the first groove 4 both sides
Inside it is formed with N+Type source area 10, and source area 10 is formed at the surface of well region 3.Wherein, the first ditch
The polysilicon layer 6 filled in groove 4 is as the grid of trench transistor, polysilicon layer 6 and the first groove 4
Between silicon dioxide layer 7 as the gate dielectric layer of trench transistor, source area 10 is as trench transistor
Source electrode, N+Type Semiconductor substrate 1 is as the drain electrode of trench transistor.
As in figure 2 it is shown, form oxide layer 11 on epitaxial layer 2 surface S, be positioned at above oxide layer 11
Intermediate dielectric layer (inter layer dielectric) 12 and be positioned at the graphical photoresist layer above dielectric layer 12
13, wherein, the thickness of dielectric layer 12 is h1, is formed with opening and (does not marks in graphical photoresist layer 13
Know), this opening exposes the dielectric layer 12 of part of trench transistor area 1a.Graphically change photoresist layer
13 perform etching for mask, to form the trench transistor contacts opening exposing source area 10 and well region 3
14。
Shown in Fig. 2 and Fig. 3, remove graphical photoresist layer 13, at dielectric layer 12 and groove crystal
Form graphical photoresist layer 15 on pipe contact openings 14, in graphical photoresist layer 15, be formed with opening
(mark), this opening exposes the dielectric layer 12 of part Schottky barrier area 1b, graphically changes light
Photoresist layer 15 carries out the first etching for mask, and to form opening 16 in dielectric layer 12, opening 16 exposes
Go out remaining dielectric layer 12, after the first etching, be positioned at the thickness remaining dielectric layer 12 below opening 16
For h2。
Shown in Fig. 3 and Fig. 4, continue graphically to change photoresist layer 15 and carry out the second etching for mask,
To form Schottky Barrier Contact opening 17, the bottom of Schottky Barrier Contact opening 17 extends to epitaxial layer
Below 2 surface S, thus expose epitaxial layer 2a and polysilicon layer 8, wherein, Schottky Barrier Contact
It is h that opening 17 enters the degree of depth of the part of epitaxial layer 23, in other words, Schottky Barrier Contact opening 17
Distance between bottom and epitaxial layer 2 surface S is h3。
Shown in Fig. 4 and Fig. 5, remove graphical photoresist layer 15, at dielectric layer 12, groove crystal
The first metal layer BL is formed, then first on pipe contact openings 14 and Schottky Barrier Contact opening 17
Form the second metal level M, the first metal layer BL and the second metal level M on metal level BL to collectively form
Metal level 18, source area 10 and well region 3 below metal level 18 and trench transistor contacts opening 14 connect
Touch；Metal level 18 contacts with the epitaxial layer 2a below Schottky Barrier Contact opening 17, thus constitutes Xiao
Special base potential barrier, wherein, metal level 18 as the anode of Schottky barrier, Schottky barrier area 1b's
Epitaxial layer 2a is as the negative electrode of Schottky barrier.
As in figure 2 it is shown, when forming dielectric layer 12, owing to the impact of many factors is (such as board deposition speed
The normal fluctuation of degree, dielectric layer Normal variations of sedimentation rate in wafer), the actual thickness of dielectric layer 12
Degree h1It is generally not accurate setting value, but fluctuates in certain deviation range.Such as, dielectric layer
The setting thickness h of 121ForTime, the actual (real) thickness of dielectric layer 12 can beIn the range of fluctuate,
In other words, the actual (real) thickness h of dielectric layer 121ForActual thickness due to dielectric layer 12
Degree can fluctuate within the specific limits, as it is shown on figure 3, therefore utilizing identical etching condition to carry out first
When etching to form opening 16, the thickness h of the residue dielectric layer 12 below opening 162Also can certain limit
Interior fluctuation；It addition, due to the process conditions affecting the first etching of many factors during actual fabrication
Can there is deviation (the such as normal fluctuation of board etch rate), therefore the residue dielectric layer below opening 16
The thickness h of 122Can fluctuate in certain limit.Owing to remaining the thickness h of dielectric layer 122Can be in certain limit
Interior fluctuation, as shown in Figure 4, therefore is utilizing identical etching condition to carry out the second etching to form Xiao Te
During base barrier contact opening 17, Schottky Barrier Contact opening 17 enters the degree of depth of the part of epitaxial layer 2
h3Also can fluctuate within the specific limits.
And Schottky Barrier Contact opening 17 enters degree of depth h of part of epitaxial layer 23Directly affect groove-shaped
The performance of Metal-oxide-semicondutor barrier schottky device: when Schottky Barrier Contact opening 17 enters
Degree of depth h of the part of epitaxial layer 23Time less than normal, in the second etching to form Schottky Barrier Contact opening 17
Afterwards, the oxide layer 11 above polysilicon layer 8 and epitaxial layer 2a there may be residual, results in Xiao
Metal level 18(above special base barrier contact opening 17 is with reference to shown in Fig. 5) can not with polysilicon layer 8 and
Epitaxial layer 2a completely attaches to, it is impossible to form groove type MOS schottky barrier device structure；Work as Schottky
Barrier contact opening 17 enters degree of depth h of the part of epitaxial layer 23Time bigger than normal, device cannot utilize metal-
Oxidc-Semiconductor structure produces depletion layer complete pinch off conductive channel, and bigger source-leakage can be caused to leak electricity
Electric current.
So that Schottky Barrier Contact opening 17 enters degree of depth h of the part of epitaxial layer 23Can obtain relatively
Controlling accurately, existing a kind of solution is: as it is shown on figure 3, dielectric layer 12 was being carried out the first quarter
Lose before forming opening 16, first measure the actual (real) thickness h of dielectric layer 121If, the reality of dielectric layer 12
Border thickness h1ForTime, utilize the first etch technological condition to carry out the first etching；If being situated between
The actual (real) thickness h of electric layer 121ForTime, utilize the second etch technological condition to carry out
One etching；If the actual (real) thickness h of dielectric layer 121ForTime, utilize the 3rd etching technics
Condition carries out the first etching, described first etch technological condition, the second etch technological condition, the 3rd quarter
In etching technique condition, etch period is different so that under three circumstances first etching after remain dielectric
The actual (real) thickness h of layer 122Can control in less scope, and then make Schottky Barrier Contact opening 17 enter
Enter degree of depth h of the part of epitaxial layer 23Also can control in smaller range.
But finding during actual fabrication, the effect that said method is realized is very limited.Such as,
Actual (real) thickness h when dielectric layer 121ForResidue dielectric layer 12 below opening 16
Set thickness h2ForTime, utilize said method to be formed the actual (real) thickness h of residue dielectric layer 122
Meeting existsIn the range of fluctuate, in other words, residue dielectric layer 12 actual (real) thickness h2For
Schottky Barrier Contact opening 17 is made to enter the thickness h of part of epitaxial layer 23Still in a big way
Fluctuation.
Forming method more about trench metal-oxide-semicondbarrier barrier Schottky can be joined
According to open, the Chinese patent of Publication No. CN101454882A on June 10th, 2009.
Summary of the invention
The technical problem to be solved in the present invention is to form trench metal-Oxidc-Semiconductor potential barrier Xiao Te
During base device, the most accurately control the degree of depth that Schottky Barrier Contact opening enters the part of epitaxial layer, enter
And improve the performance of device.
In order to solve the problems referred to above, the invention provides a kind of trench metal-Oxidc-Semiconductor potential barrier Xiao
The forming method of special base device, comprising:
Thering is provided Semiconductor substrate, it is provided above semiconductor region, and described Semiconductor substrate includes that groove is brilliant
Territory, body area under control and Schottky barrier area, wherein, be formed with ditch in the semiconductor region in trench transistor region
Groove transistor, is formed with the first ditch filled by gate material layers in the semiconductor region of Schottky barrier area
Groove；
Described semiconductor region is formed barrier layer and is positioned at the dielectric layer above described barrier layer；
Forming graphical photoresist layer on described dielectric layer, the part of dielectric layer of Schottky barrier area is not
Covered by described graphical photoresist layer, for mask, described dielectric layer is entered with described graphical photoresist layer
Row first etches to form the opening exposing described barrier layer；
Carry out the second etching with described graphical photoresist layer for mask, expose described grid material to be formed
The Schottky Barrier Contact opening of the bed of material and semiconductor region；
After removing described graphical photoresist layer, on described dielectric layer and Schottky Barrier Contact opening
Forming metal level, the semiconductor region below described Schottky Barrier Contact opening contacts with described metal level,
To form Schottky barrier.
Alternatively, the material on described barrier layer is silicon nitride or silicon-oxygen nitride, the material of described dielectric layer
For utilizing the silicon oxide or borophosphosilicate glass that TEOS formed.
Alternatively, the degree of depth of the part that described Schottky Barrier Contact opening enters described semiconductor region is
Alternatively, the material of described gate material layers is polysilicon.
Alternatively, described metal level includes the first metal layer and the second metal level being positioned above, described
The material of the first metal layer is titanium-tungsten and/or titanium-silicon compound, and the material of described second metal level is aluminum
Or aluminium copper.
Alternatively, it is formed with trench transistor and Schottky barrier in the semiconductor region in trench transistor region
The forming method being formed with the first groove filled by gate material layers in the semiconductor region in region includes:
Forming described first groove and the second groove in described semiconductor region, described second groove is arranged on
In the semiconductor region in trench transistor region；
Described gate material layers is formed in described first groove and the second groove；
Well region, the bottom of described second groove is formed on the semiconductor region surface in described trench transistor region
Being arranged in the semiconductor region below described well region, the doping type of described semiconductor region is the first doping,
The doping type of described well region is the second doping；
The source area of the first doping type, described source area is formed in the well region of described second groove both sides
It is arranged on the surface of described well region.
Alternatively, before described dielectric layer forms graphical photoresist layer, to described dielectric layer and resistance
Barrier performs etching to be formed trench transistor contacts opening, and described trench transistor contacts opening exposes
Described source area and well region, source area below described metal level and described trench transistor contacts opening and
Well region contacts.
Alternatively, the doping type of described semiconductor region is N-type, and the doping type of described well region is p-type,
The doping type of described source area is N-type.
Alternatively, described semiconductor region is epitaxial layer, and its material is silicon.
Compared with prior art, technical scheme has the advantage that
In a technical scheme of the present invention, Schottky Barrier Contact opening is to utilize the first etching and
Two two steps of etching are formed, and in the first etch step barrier layer as etching terminal barrier structure,
Therefore the accurate control of the first etching etching terminal can be realized；In addition, it is not necessary that measure the thickness of dielectric layer
Degree also utilizes different etch periods to carry out the first etching according to the difference measuring thickness so that Schottky
The forming method of barrier contact opening is the simplest.Owing to the first etching can stop at barrier layer exactly
On, therefore only by controlling the second etch process parameters in the second etch step after the first etch step
I.e. can determine that Schottky Barrier Contact opening enters the degree of depth of the part of semiconductor region so that Schottky barrier
The degree of depth of the part that contact openings enters semiconductor region can be precisely controlled, and then improves the property of device
The stability of energy.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is that existing a kind of trench metal-oxide-semicondbarrier barrier Schottky is at each
The sectional view of production phase；
Fig. 6 to Figure 12 is trench metal in one embodiment of the present of invention-Oxidc-Semiconductor potential barrier Xiao
Special base device is at the sectional view of each production phase.
Detailed description of the invention
Below in conjunction with the accompanying drawings, by specific embodiment, technical scheme is carried out clear, complete
Description, it is clear that described embodiment is only a part for the embodiment of the present invention, and not
It is that they are whole.According to these embodiments, those of ordinary skill in the art is before without creative work
Put obtainable other embodiments all, broadly fall into protection scope of the present invention.
As shown in Figure 6, it is provided that the Semiconductor substrate 100 of the first doping type, Semiconductor substrate 100 includes
Trench transistor region 101 and Schottky barrier area 102.The material of Semiconductor substrate 100 can be single
Crystal silicon, it is also possible to be silicon, germanium, GaAs or silicon Germanium compound, it is also possible to be silicon-on-insulator (SOI,
Silicon On Insulator) substrate, in one embodiment, Semiconductor substrate 100 is N+Type silicon substrate.
The semiconductor region 110 of the first doping type, in one embodiment, half it is formed with in Semiconductor substrate 100
Conductor region 110 is N-Type epitaxial layer, its material is silicon.Epitaxial layer 110 has with Semiconductor substrate 100
Identical lattice structure, simply purity is higher, and lattice defect is less.
As shown in Figure 8, in the semiconductor region 110 in trench transistor region 101, it is formed with trench transistor,
The first groove filled by gate material layers it is formed with in the semiconductor region 110 of Schottky barrier area 102.
In one embodiment, in the semiconductor region 110 in trench transistor region 101, it is formed with trench transistor,
The first groove filled by gate material layers it is formed with in the semiconductor region 110 of Schottky barrier area 102
Forming method comprise the steps:
As it is shown in fig. 7, form the first groove 131 and the second groove 132 in semiconductor region 110, wherein,
First groove 131 is arranged in the semiconductor region 110 of Schottky barrier area 102, the second groove 132
It is arranged in the semiconductor region 110 in trench transistor region 101.In one embodiment, the first groove
131 and second the forming method of groove 132 include: on semiconductor region 110, form graphical photoresist layer
(not shown), performs etching epitaxial layer 110 with described graphical photoresist layer for mask.This area skill
Art personnel can determine concrete etching depth according to specific requirement, it should be noted that, trench metal-
In Oxidc-Semiconductor barrier schottky device, the quantity of the first groove 131 and the second groove 132 should be not only
It is confined to accompanying drawing.
As shown in Figure 8, in the first groove 131, insulating barrier 141 and gate material layers 151, insulation are formed
Layer 141, between the first groove 131 and gate material layers 151, is formed absolutely in the second groove 132
Edge layer 142 and gate material layers 152, insulating barrier 142 is positioned at the second groove 132 and gate material layers 152
Between.In one embodiment, the material of insulating barrier 141 and insulating barrier 142 is silicon oxide, grid material
The material of the bed of material 151 and gate material layers 152 is polysilicon.In one embodiment, first it is filled in
Insulating barrier in groove 131 141 and gate material layers 151, the insulating barrier being filled in the second groove 132
142 include with the forming method of gate material layers 152: at semiconductor region the 110, first groove 131 and
Form insulating barrier (not shown) on two grooves 132 and be positioned at the gate material layers above insulating barrier and (do not scheme
Show), described insulating barrier covers on the first groove 131 and the sidewall of the second groove 132 and bottom, described
First groove 131 and the second groove 132 are filled up by gate material layers；Utilize cmp (CMP)
Technique removes unnecessary gate material layers.Wherein, the gate material layers 152 in the second groove 132 it is filled in
As the grid of trench transistor, it is filled in the insulating barrier 142 in the second groove 132 as groove crystal
The gate dielectric layer of pipe.
With continued reference to shown in Fig. 8, form the on semiconductor region 110 surface in trench transistor region 101
The well region 111 of two doping types, in one embodiment, the doping type of well region 111 is p-type, its shape
One-tenth method includes: the semiconductor region 110 in trench transistor region 101 carries out ion implanting, thus
The semiconductor region 110 in trench transistor region 101 forms well region 111, semiconductor region 110 except well region 111
Part in addition is semiconductor region 112.Those skilled in the art can as required to Semiconductor substrate 100,
The doping content of semiconductor region 110 and well region 111 is selected.Wherein, the bottom of the second groove 132 sets
Put in the semiconductor region 112 below well region 111.In the present embodiment, due to the first groove 131 and
When two grooves 132 concurrently form, therefore the bottom of the first groove 131 is also disposed at below well region 111 half
In conductor region 112.
With continued reference to shown in Fig. 8, in the well region 111 of the first groove 131 both sides, form the first doping class
The source area 113 of type, source area 113 is arranged on the surface of well region 111.In one embodiment, source electrode
The doping type in district 113 is N+Type, its forming method is ion implanting.Source area 113 is brilliant as groove
The source electrode of body pipe, Semiconductor substrate 100 as the drain electrode of trench transistor, well region 111 except source area
Part beyond 113 is as the channel region of trench transistor.
It should be noted that, trench transistor and be filled with the shape of the first groove 131 of gate material layers 151
One-tenth method is not limited to above-described embodiment, it is also possible to other existing trench metal-Oxidc-Semiconductor gesture
The forming method building schottky device forms above-mentioned trench transistor and is filled with gate material layers 151
First groove 131.
Alternatively, make annealing treatment, to advance source area 113 ion after forming source area 113
Redistribution and repair the damage in ion implantation process, lattice structure caused.After an annealing treatment,
As it is shown in figure 9, oxide layer 160 can be formed on semiconductor region 110 surface.
With continued reference to shown in Fig. 9, oxide layer 160 is formed barrier layer 170 and is positioned at barrier layer 170
The dielectric layer 180 of top.Then on dielectric layer 180, form graphical photoresist layer 190, groove crystal
The part of dielectric layer 180 in territory, area under control 101 is not patterned immediately photoresist layer 190 and covers, and graphically changes photoetching
Dielectric layer 180, barrier layer 170 and oxide layer 160 are performed etching by glue-line 190 for mask, sudden and violent to be formed
Expose the trench transistor contacts opening 181 of source area 113 and well region 111.
As shown in Figure 10, after removing the graphical photoresist layer 190 shown in Fig. 9, at dielectric layer 180
The graphical photoresist layer of upper formation 200, the part of dielectric layer 180 of Schottky barrier area 102 is not by figure
Changing photoresist layer 200 to cover, trench transistor contacts opening 181 is covered by graphical photoresist layer 200
Live.Graphically change photoresist layer 200 and for mask, dielectric layer 180 is carried out the first etching, to form exposure
Going out the opening 182 on barrier layer 170, opening 182 is for defining the position of Schottky Barrier Contact opening.?
In one embodiment, the material on barrier layer 170 is silicon nitride or silicon-oxygen nitride, the material of dielectric layer 180
Material is for utilizing TEOS(tetraethyl orthosilicate) silicon oxide that formed or borophosphosilicate glass (BPSG), at this
A kind of lithographic method can be selected, barrier layer 170 and dielectric layer 180 in this lithographic method under the conditions of Zhong
Etching selection ratio much smaller than 1.Owing to the etching selection ratio on barrier layer 170 with dielectric layer 180 is less than 1,
Therefore structure can be detected as etching terminal in barrier layer 170 in the first etch step, i.e. exposing resistance
The first etching is stopped during barrier 170.Certainly, the material of barrier layer 170 and dielectric layer 180 does not limit to
It is possible with other material in above-described embodiment, barrier layer 170 and dielectric layer 180 to make, as long as stopping
The material of layer 170 and dielectric layer 180 makes it possible to select such a lithographic method to form opening 182
: in this lithographic method, barrier layer 170 and the etching selection ratio of dielectric layer 180 are less than 1.
As shown in figure 11, graphically change photoresist layer 200 and carry out the second etching for mask, to form Xiao Te
Base barrier contact opening 183, Schottky Barrier Contact opening 183 exposes gate material layers 151 and partly leads
Body district 112.In one embodiment, the second etching is dry etching, and the etching gas used is to resistance
The etch rate of barrier 170, oxide layer 160, gate material layers 151 and semiconductor region 110 is equal, this
Sample is so that the bottom of formed Schottky Barrier Contact opening 183 is the most smooth.An embodiment
In, Schottky Barrier Contact opening 183 enters degree of depth h of the part of semiconductor region 110 and isSo that trench metal-oxide-semicondbarrier barrier Schottky has preferably property
Energy.
Shown in comparison Fig. 3 to Fig. 5, existing trench metal-oxide-semicondbarrier barrier Schottky
In forming method, Schottky Barrier Contact opening 17 is to utilize the first etching and second two step shapes of etching
Become, and the first etching stopping in dielectric layer 12 (as shown in Figure 3), due to the actual thickness of dielectric layer 12
Degree h1Can fluctuate in the larger context, can first measure the reality of dielectric layer 12 before carrying out the first etching
Border thickness h1, then according to the actual (real) thickness h of dielectric layer 121Select different technological parameters, so that surplus
The actual (real) thickness h of remaining dielectric layer 122Can fluctuate in less scope, and then make Schottky Barrier Contact
Opening 17 enters degree of depth h of the part of epitaxial layer 23Can fluctuate in smaller range.
And in the present invention, Schottky Barrier Contact opening 183 is to utilize the first etching and the second etching two
Individual step is formed, and in the first etch step, structure is detected as etching terminal in barrier layer 170, therefore
The accurate control of the first etching etching terminal can be realized；In addition, it is not necessary that measure the thickness of dielectric layer 180
Degree also utilizes different etch periods to carry out the first etching according to the difference measuring thickness so that Schottky
The forming method of barrier contact opening 183 is the simplest.Owing to the first etching can stop at resistance exactly
In barrier 170, therefore only by controlling the second etching in the second etch step after the first etch step
Technological parameter i.e. can determine that Schottky Barrier Contact opening 183 enters the degree of depth of the part of semiconductor region 110
H so that Schottky Barrier Contact opening 183 enters degree of depth h of the part of semiconductor region 110 can be accurate
Control.
As shown in figure 12, remove after the graphical photoresist layer 200 shown in Figure 11, dielectric layer 180,
Metal level 210, Xiao Te is formed on Schottky Barrier Contact opening 183 and trench transistor contacts opening 181
Semiconductor region 112 below base barrier contact opening 183 contacts with metal level 210, to form Schottky
Potential barrier, wherein, metal level 210 is as the anode of Schottky barrier, and semiconductor region 112 is as Schottky
The negative electrode of potential barrier.It addition, metal level 210 contacts with source area 113 and well region 111.An embodiment
In, metal level 210 includes the first metal layer 211 and is positioned at the second metal above the first metal layer 211
Layer 212, wherein, the material of the first metal layer 211 is titanium-tungsten and/or titanium-silicon compound, the second gold medal
The material belonging to layer 212 is aluminum or albronze.
In other embodiments, can be according to the need of trench metal-oxide-semicondbarrier barrier Schottky
Semiconductor substrate 100, semiconductor region 110, well region 111 and source area 113 are adjusted to contrary mixing
Miscellany type.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to be more fully understood that the present invention,
And can reproduce and use the present invention.Those skilled in the art can according to principle specifically described herein
To above-described embodiment as various changes and modifications to be without departing from the spirit and scope of the present invention
Obviously.Therefore, the present invention should not be construed as being limited to above-described embodiment shown in this article, its
Protection domain should be defined by appending claims.
Claims (9)
1. a forming method for trench metal-oxide-semicondbarrier barrier Schottky, its feature exists
In, including:
Thering is provided Semiconductor substrate, it is provided above semiconductor region, and described Semiconductor substrate includes that groove is brilliant
Territory, body area under control and Schottky barrier area, wherein, be formed with ditch in the semiconductor region in trench transistor region
Groove transistor, is formed with the first ditch filled by gate material layers in the semiconductor region of Schottky barrier area
Groove；
Described semiconductor region is formed barrier layer and is positioned at the dielectric layer above described barrier layer；
Forming graphical photoresist layer on described dielectric layer, the part of dielectric layer of Schottky barrier area is not
Covered by described graphical photoresist layer, for mask, described dielectric layer is entered with described graphical photoresist layer
Row first etches to form the opening exposing described barrier layer；
Carry out the second etching with described graphical photoresist layer for mask, expose described grid material to be formed
The Schottky Barrier Contact opening of the bed of material and semiconductor region；
After removing described graphical photoresist layer, on described dielectric layer and Schottky Barrier Contact opening
Forming metal level, the semiconductor region below described Schottky Barrier Contact opening contacts with described metal level,
To form Schottky barrier.
Forming method the most according to claim 1, it is characterised in that the material on described barrier layer is nitrogen
SiClx or silicon-oxygen nitride, the material of described dielectric layer is the silicon oxide utilizing TEOS to be formed or boron-doping phosphorus
Silica glass.
Forming method the most according to claim 1, it is characterised in that described Schottky Barrier Contact is opened
The degree of depth of the part that mouth enters described semiconductor region is
Forming method the most according to claim 1, it is characterised in that the material of described gate material layers
For polysilicon.
Forming method the most according to claim 1, it is characterised in that described metal level includes the first gold medal
Belonging to layer and the second metal level being positioned above, the material of described the first metal layer is titanium-tungsten and/or titanium
Silicon compound, the material of described second metal level is aluminum or aluminium copper.
Forming method the most according to claim 1, it is characterised in that partly leading of trench transistor region
It is formed by grid material in being formed with the semiconductor region of trench transistor and Schottky barrier area in body district
The forming method of the first groove that layer is filled includes:
Forming described first groove and the second groove in described semiconductor region, described second groove is arranged on
In the semiconductor region in trench transistor region；
Described gate material layers is formed in described first groove and the second groove；
Well region, the bottom of described second groove is formed on the semiconductor region surface in described trench transistor region
Being arranged in the semiconductor region below described well region, the doping type of described semiconductor region is the first doping,
The doping type of described well region is the second doping；
The source area of the first doping type, described source area is formed in the well region of described second groove both sides
It is arranged on the surface of described well region.
Forming method the most according to claim 6, it is characterised in that form figure on described dielectric layer
Before shape photoresist layer, perform etching to form trench transistor contacts to described dielectric layer and barrier layer
Opening, described trench transistor contacts opening exposes described source area and well region, described metal level and institute
State the source area below trench transistor contacts opening and well region contact.
Forming method the most according to claim 6, it is characterised in that the doping class of described semiconductor region
Type is N-type, and the doping type of described well region is p-type, and the doping type of described source area is N-type.
Forming method the most according to claim 1, it is characterised in that described semiconductor region is epitaxial layer,
Its material is silicon.
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| CN104183483B (en) * | 2013-05-20 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | The preparation method of groove-shaped Schottky diode |
| CN103346087B (en) * | 2013-06-03 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing groove-type metal-oxide semiconductor Schottky barrier device |
| CN105097517B (en) * | 2014-04-25 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and its manufacturing method, electronic device |
| CN103985627B (en) * | 2014-05-12 | 2017-03-08 | 上海先进半导体制造股份有限公司 | Improve the process of TMBS yield |
| MY185098A (en) * | 2014-08-29 | 2021-04-30 | Mimos Berhad | A method for manufacturing a large schottky diode |
| US9691780B2 (en) | 2015-09-25 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interdigitated capacitor in split-gate flash technology |
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| CN102088020A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Device with schottky diode integrated in power metal oxide semiconductor (MOS) transistor and manufacturing method thereof |
| CN102768994A (en) * | 2011-05-02 | 2012-11-07 | 万国半导体股份有限公司 | Integrating schottky diode into power mosfet |
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| CN102088020A (en) * | 2009-12-08 | 2011-06-08 | 上海华虹Nec电子有限公司 | Device with schottky diode integrated in power metal oxide semiconductor (MOS) transistor and manufacturing method thereof |
| CN102768994A (en) * | 2011-05-02 | 2012-11-07 | 万国半导体股份有限公司 | Integrating schottky diode into power mosfet |
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