CN103021867A - Trench metal-oxide-semiconductor barrier Schottky forming method - Google Patents
Trench metal-oxide-semiconductor barrier Schottky forming method Download PDFInfo
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- CN103021867A CN103021867A CN201210564065XA CN201210564065A CN103021867A CN 103021867 A CN103021867 A CN 103021867A CN 201210564065X A CN201210564065X A CN 201210564065XA CN 201210564065 A CN201210564065 A CN 201210564065A CN 103021867 A CN103021867 A CN 103021867A
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- 230000004888 barrier function Effects 0.000 title claims abstract description 133
- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims description 51
- 230000015572 biosynthetic process Effects 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- -1 silicon-oxygen nitride Chemical class 0.000 claims description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical group [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 3
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 2
- 238000001514 detection method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 161
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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Abstract
The invention discloses a trench metal-oxide-semiconductor barrier Schottky forming method. A Schottky barrier contact opening is formed by a first etching step and a second etching step, and a barrier layer is used as an etching end point detection structure at the first etching step, so that precision control of etching end points during first etching can be realized. Additionally, measuring the thickness of a dielectric layer and using different etching time for first etching according to different measured thicknesses are not needed, and accordingly the Schottky barrier contact opening forming method is simpler. Since the first etching can be accurately stopped on the barrier layer, the depth of the portion, entering a semiconductor region, of the Schottky barrier contact opening can be determined only by controlling second etching technological parameters at the second etching step after the first etching step and can be controlled more precisely, and performance stability of the trench metal-oxide-semiconductor barrier Schottky is further improved.
Description
Technical field
The invention belongs to semiconductor power device (Power Device) field, particularly relate to a kind of groove-shaped Metal-oxide-semicondutor barrier schottky device formation method of (Trench MOS Barrier Schottky is called for short TMBS).
Background technology
Along with the development of semiconductor technology, power device is widely used in the fields such as disk drive, automotive electronics as a kind of new device.Power device needs to bear larger voltage, electric current and power termination.And the devices such as existing MOS transistor can't satisfy the demand, and therefore, in order to satisfy the needs of using, various power devices become the focus of concern.
In order to improve the friendship frequency characteristic of power device, comparatively general a kind of method is integrated schottky potential barrier in trench transistor at present.
Below in conjunction with Fig. 1 to Fig. 5 the formation method of existing a kind of groove-shaped Metal-oxide-semicondutor barrier schottky device is done simple the introduction:
As shown in Figure 1, provide N
+ Type Semiconductor substrate 1, Semiconductor substrate 1 comprise trench transistor zone 1a and Schottky barrier zone 1b, are formed with N on the Semiconductor substrate 1
-Type epitaxial loayer 2, epitaxial loayer 2 surfaces are formed with P type well region 3, the part except well region 3 of epitaxial loayer 2 is epitaxial loayer 2a, be formed with the first groove 4 on the epitaxial loayer 2 of trench transistor zone 1a, be formed with the second groove 5 on the epitaxial loayer 2 of Schottky barrier zone 1b, the opening of the first groove 4 and the second groove 5 is arranged on epitaxial loayer 2 surperficial S, the bottom is positioned at the epitaxial loayer 2a of well region 3 belows, the sidewall of the first groove 4 and bottom are coated with silicon dioxide layer 7, be filled with polysilicon layer 6 in the first groove 4, the sidewall of the second groove 5 and bottom are coated with silicon dioxide layer 9, be filled with in the second groove 5 in the well region 3 of polysilicon layer 8, the first grooves 4 both sides and be formed with N
+ Type source area 10, and source area 10 is formed on the surface of well region 3.Wherein, the polysilicon layer 6 of the first groove 4 interior fillings is as the grid of trench transistor, and the silicon dioxide layer 7 between polysilicon layer 6 and the first groove 4 is as the gate dielectric layer of trench transistor, and source area 10 is as the source electrode of trench transistor, N
+ Type Semiconductor substrate 1 is as the drain electrode of trench transistor.
As shown in Figure 2, form oxide layers 11 at the surperficial S of epitaxial loayer 2, be positioned at the intermediate dielectric layer (inter layer dielectric) 12 above the oxide layer 11 and be positioned at the graphical photoresist layer 13 of dielectric layer 12 tops, wherein, the thickness of dielectric layer 12 is h1, be formed with opening (not sign) in the graphical photoresist layer 13, this opening exposes the dielectric layer 12 of part trench transistor zone 1a.Carry out etching take graphical photoresist layer 13 as mask, expose the trench transistor contact openings 14 of source area 10 and well region 3 with formation.
In conjunction with Fig. 2 and shown in Figure 3, remove graphical photoresist layer 13, form graphical photoresist layer 15 at dielectric layer 12 and trench transistor contact openings 14, be formed with opening (not sign) in the graphical photoresist layer 15, this opening exposes the dielectric layer 12 of part Schottky barrier zone 1b, carry out the first etching take graphical photoresist layer 15 as mask, with at dielectric layer 12 interior formation openings 16, it is h that opening 16 exposes the thickness that is positioned at the residue dielectric layer 12 of opening 16 belows after remaining dielectric layer 12, the first etchings
2
In conjunction with Fig. 3 and shown in Figure 4, continuation is carried out the second etching take graphical photoresist layer 15 as mask, to form Schottky Barrier Contact opening 17, the bottom of Schottky Barrier Contact opening 17 extends to epitaxial loayer 2 surperficial S belows, thereby expose epitaxial loayer 2a and polysilicon layer 8, wherein, to enter the degree of depth of the part of epitaxial loayer 2 be h to Schottky Barrier Contact opening 17
3, in other words, the distance between Schottky Barrier Contact opening 17 bottoms and the epitaxial loayer 2 surperficial S is h
3
In conjunction with Fig. 4 and shown in Figure 5, remove graphical photoresist layer 15, form the first metal layer BL at dielectric layer 12, trench transistor contact openings 14 and Schottky Barrier Contact opening 17, then form the second metal level M at the first metal layer BL, the first metal layer BL and the second metal level M consist of metal level 18 jointly, and metal level 18 contacts with source area 10 and the well region 3 of trench transistor contact openings 14 belows; Metal level 18 contacts with the epitaxial loayer 2a of Schottky Barrier Contact opening 17 belows, thereby consists of Schottky barrier, and wherein, metal level 18 is as the anode of Schottky barrier, and the epitaxial loayer 2a of Schottky barrier zone 1b is as the negative electrode of Schottky barrier.
As shown in Figure 2, when forming dielectric layer 12, since the impact (such as the normal fluctuation of board deposition velocity, the normal difference of dielectric layer deposition rate in wafer) of many factors, the actual (real) thickness h of dielectric layer 12
1Usually be not to be accurate set point, but in certain deviation range, fluctuate.For example, the setting thickness h of dielectric layer 12
1For
The time, the actual (real) thickness of dielectric layer 12 can
Fluctuation in the scope, in other words, the actual (real) thickness h of dielectric layer 12
1For
Because the actual (real) thickness of dielectric layer 12 can fluctuate within the specific limits, as shown in Figure 3, therefore when utilizing identical etching condition to carry out the first etching with formation opening 16, the thickness h of the residue dielectric layer 12 of opening 16 belows
2Also can fluctuate in the certain limit; In addition, can there be deviation (for example normal fluctuation of board etch rate) in the process conditions that affect the first etching owing to many factors in the actual fabrication process, therefore the thickness h of the residue dielectric layer 12 of opening 16 belows
2Can fluctuate in the certain limit.Because the thickness h of residue dielectric layer 12
2Within the specific limits fluctuation, as shown in Figure 4, therefore when utilizing identical etching condition to carry out the second etching with formation Schottky Barrier Contact opening 17, Schottky Barrier Contact opening 17 enters the degree of depth h of the part of epitaxial loayer 2
3Also can fluctuate within the specific limits.
And Schottky Barrier Contact opening 17 enters the degree of depth h of the part of epitaxial loayer 2
3Directly affect groove-shaped Metal-oxide-semicondutor barrier schottky performance of devices: the degree of depth h that enters the part of epitaxial loayer 2 when Schottky Barrier Contact opening 17
3When less than normal, after the second etching is with formation Schottky Barrier Contact opening 17, the oxide layer 11 of polysilicon layer 8 and epitaxial loayer 2a top may have residual, cause being formed on the metal level 18(of Schottky Barrier Contact opening 17 tops with reference to shown in Figure 5) can not contact fully with epitaxial loayer 2a with polysilicon layer 8, can't form groove type MOS schottky barrier device structure; Enter the degree of depth h of the part of epitaxial loayer 2 when Schottky Barrier Contact opening 17
3When bigger than normal, device can't utilize metals-oxides-semiconductor structure to produce the complete pinch off conductive channel of depletion layer, can cause larger source-leakage leakage current.
For so that Schottky Barrier Contact opening 17 enters the degree of depth h of the part of epitaxial loayer 2
3Can obtain controlling more accurately, existing a kind of solution is: as shown in Figure 3, dielectric layer 12 being carried out the first etching with before forming opening 16, at first measure the actual (real) thickness h of dielectric layer 12
1If, the actual (real) thickness h of dielectric layer 12
1For
The time, utilize the first etch technological condition to carry out the first etching; If the actual (real) thickness h of dielectric layer 12
1For
The time, utilize the second etch technological condition to carry out the first etching; If the actual (real) thickness h of dielectric layer 12
1For
The time, utilize the 3rd etch technological condition to carry out the first etching, etch period is different in described the first etch technological condition, the second etch technological condition, the 3rd etch technological condition, so that remain the actual (real) thickness h of dielectric layer 12 after the first etching in three kinds of situations
2Can be controlled at less scope, and then make Schottky Barrier Contact opening 17 enter the degree of depth h of the part of epitaxial loayer 2
3Also can be controlled at more among a small circle.
But find in the actual fabrication process, the effect that said method is realized is very limited.For example, as the actual (real) thickness h of dielectric layer 12
1For
The setting thickness h of the residue dielectric layer 12 of opening 16 belows
2For
The time, utilize said method to form the actual (real) thickness h of residue dielectric layer 12
2Meeting exists
Fluctuation in the scope, in other words, the actual (real) thickness h of residue dielectric layer 12
2For
So that Schottky Barrier Contact opening 17 enters the thickness h of the part of epitaxial loayer 2
3Still fluctuation in a big way.
More about the formation method of groove-shaped Metal-oxide-semicondutor barrier schottky device can be open with reference on June 10th, 2009, publication number is the Chinese patent of CN101454882A.
Summary of the invention
The technical problem to be solved in the present invention is when forming groove-shaped Metal-oxide-semicondutor barrier schottky device, how accurately to control the degree of depth that the Schottky Barrier Contact opening enters the part of epitaxial loayer, and then improves performance of devices.
In order to address the above problem, the invention provides a kind of formation method of groove-shaped Metal-oxide-semicondutor barrier schottky device, it comprises:
Semiconductor substrate is provided, its top is provided with semiconductor region, described Semiconductor substrate comprises trench transistor zone and Schottky barrier zone, wherein, be formed with trench transistor in the semiconductor region in trench transistor zone, be formed with first groove of being filled by gate material layers in the semiconductor region in Schottky barrier zone;
Form the barrier layer and be positioned at dielectric layer above the described barrier layer at described semiconductor region;
Form graphical photoresist layer at described dielectric layer, the part dielectric layer in Schottky barrier zone is not covered by described graphical photoresist layer, take described graphical photoresist layer as mask described dielectric layer is carried out the first etching exposes described barrier layer with formation opening;
Carry out the second etching take described graphical photoresist layer as mask, expose the Schottky Barrier Contact opening of described gate material layers and semiconductor region with formation;
Remove after the described graphical photoresist layer, form metal level at described dielectric layer and Schottky Barrier Contact opening, the semiconductor region of described Schottky Barrier Contact opening below contacts with described metal level, to form Schottky barrier.
Alternatively, the material on described barrier layer is silicon nitride or silicon-oxygen nitride, and the material of described dielectric layer is silica or the boron-doping phosphorosilicate glass that utilizes TEOS to form.
Alternatively, described Schottky Barrier Contact opening enters the degree of depth of the part of described semiconductor region and is
Alternatively, the material of described gate material layers is polysilicon.
Alternatively, described metal level comprises the second metal level of the first metal layer and the side of being located thereon, and the material of described the first metal layer is titanium-tungsten and/or titanium-silicon compound, and the material of described the second metal level is aluminium or aluminium copper.
Alternatively, being formed with the formation method that is formed with first groove of being filled by gate material layers in the semiconductor region in trench transistor and Schottky barrier zone in the semiconductor region in trench transistor zone comprises:
Form described the first groove and the second groove in described semiconductor region, described the second groove is arranged in the semiconductor region in trench transistor zone;
In described the first groove and the second groove, form described gate material layers;
Semiconductor region surface in described trench transistor zone forms well region, and the bottom of described the second groove is arranged in the semiconductor region of described well region below, and the doping type of described semiconductor region is the first doping, and the doping type of described well region is the second doping;
Form the source area of the first doping type in the well region of described the second groove both sides, described source area is arranged on the surface of described well region.
Alternatively, before described dielectric layer forms graphical photoresist layer, described dielectric layer and barrier layer are carried out etching to form the trench transistor contact openings, described trench transistor contact openings exposes described source area and well region, and described metal level contacts with source area and the well region of described trench transistor contact openings below.
Alternatively, the doping type of described semiconductor region is N-type, and the doping type of described well region is the P type, and the doping type of described source area is N-type.
Alternatively, described semiconductor region is epitaxial loayer, and its material is silicon.
Compared with prior art, technical scheme of the present invention has the following advantages:
In a technical scheme of the present invention, the Schottky Barrier Contact opening is to utilize the first etching and two steps of the second etching to form, and the accurate control of the first etching etching terminal can be realized as the etching terminal barrier structure in the barrier layer therefore in the first etch step; In addition, do not need to measure the thickness of dielectric layer and utilize different etch periods to carry out the first etching according to the difference of detect thickness, so that the formation method of Schottky Barrier Contact opening is more simple.Because the first etching can stop on the barrier layer exactly, therefore only can determine that by controlling the second etching technics parameter the Schottky Barrier Contact opening enters the degree of depth of the part of semiconductor region in the second etch step after the first etch step, can control more accurately so that the Schottky Barrier Contact opening enters the degree of depth of the part of semiconductor region, and then improve the stability of performance of devices.
Description of drawings
Fig. 1 to Fig. 5 is the cutaway view of existing a kind of groove-shaped Metal-oxide-semicondutor barrier schottky device in each production phase;
Fig. 6 to Figure 12 be in one embodiment of the present of invention groove-shaped Metal-oxide-semicondutor barrier schottky device at the cutaway view of each production phase.
Embodiment
Below in conjunction with accompanying drawing, by specific embodiment, technical scheme of the present invention is carried out clear, complete description, obviously, described embodiment only is the part of embodiment of the present invention, rather than they are whole.According to these embodiment, those of ordinary skill in the art belongs to protection scope of the present invention need not obtainable all other execution modes under the prerequisite of creative work.
As shown in Figure 6, provide the Semiconductor substrate 100 of the first doping type, Semiconductor substrate 100 comprises trench transistor zone 101 and Schottky barrier zone 102.The material of Semiconductor substrate 100 can be monocrystalline silicon, also can be silicon, germanium, GaAs or silicon Germanium compound, can also be silicon-on-insulator (SOI, Silicon On Insulator) substrate, and in one embodiment, Semiconductor substrate 100 is N
+The type silicon substrate.Be formed with the semiconductor region 110 of the first doping type on the Semiconductor substrate 100, in one embodiment, semiconductor region 110 is N
-Type epitaxial loayer, its material are silicon.Epitaxial loayer 110 has identical lattice structure with Semiconductor substrate 100, and just purity is higher, and lattice defect still less.
As shown in Figure 8, be formed with trench transistor in the semiconductor region 110 in trench transistor zone 101, be formed with first groove of being filled by gate material layers in the semiconductor region 110 in Schottky barrier zone 102.In one embodiment, be formed with trench transistor in the semiconductor region 110 in trench transistor zone 101, the formation method that is formed with first groove of being filled by gate material layers in the semiconductor region 110 in Schottky barrier zone 102 comprises the steps:
As shown in Figure 7, at semiconductor region 110 interior formation the first groove 131 and the second grooves 132, wherein, the first groove 131 is arranged in the semiconductor region 110 in Schottky barrier zone 102, and the second groove 132 is arranged in the semiconductor region 110 in trench transistor zone 101.In one embodiment, the formation method of the first groove 131 and the second groove 132 comprises: form graphical photoresist layer (not shown) at semiconductor region 110, take described graphical photoresist layer as mask epitaxial loayer 110 is carried out etching.Those skilled in the art can determine concrete etching depth according to specific requirement, it should be noted that, the quantity of the first groove 131 and the second groove 132 should only not be confined to accompanying drawing in the groove-shaped Metal-oxide-semicondutor barrier schottky device.
As shown in Figure 8, in the first groove 131 interior formation insulating barrier 141 and gate material layers 151, insulating barrier 141 is between the first groove 131 and gate material layers 151, in the second groove 132 interior formation insulating barrier 142 and gate material layers 152, insulating barrier 142 is between the second groove 132 and gate material layers 152.In one embodiment, the material of insulating barrier 141 and insulating barrier 142 is silica, and the material of gate material layers 151 and gate material layers 152 is polysilicon.In one embodiment, the formation method that be filled in insulating barrier 141 and gate material layers 151 in the first groove 131, is filled in insulating barrier 142 and gate material layers 152 in the second groove 132 comprises: form insulating barrier (not shown) and be positioned at the gate material layers (not shown) of insulating barrier top at semiconductor region 110, the first groove 131 and the second groove 132, described insulating barrier covers on the sidewall and bottom of the first groove 131 and the second groove 132, and described gate material layers is filled up the first groove 131 and the second groove 132; Utilize cmp (CMP) technique to remove unnecessary gate material layers.Wherein, be filled in gate material layers 152 in the second groove 132 as the grid of trench transistor, be filled in insulating barrier 142 in the second groove 132 as the gate dielectric layer of trench transistor.
Continue with reference to shown in Figure 8, form the well region 111 of the second doping type on semiconductor region 110 surfaces in trench transistor zone 101, in one embodiment, the doping type of well region 111 is the P type, its formation method comprises: the semiconductor region 110 to trench transistor zone 101 carries out Implantation, thereby the semiconductor region 110 in trench transistor zone 101 forms well region 111, and the part except well region 111 of semiconductor region 110 is semiconductor region 112.Those skilled in the art can select the doping content of Semiconductor substrate 100, semiconductor region 110 and well region 111 as required.Wherein, the bottom of the second groove 132 is arranged in the semiconductor region 112 of well region 111 belows.In the present embodiment, because the first groove 131 and the second groove 132 are when forming simultaneously, therefore the bottom of the first groove 131 also is arranged in the semiconductor region 112 of well region 111 belows.
Continue with reference to shown in Figure 8, at the source area 113 of well region 111 interior formation first doping types of the first groove 131 both sides, source area 113 is arranged on the surface of well region 111.In one embodiment, the doping type of source area 113 is N
+Type, its formation method is Implantation.Source area 113 is as the source electrode of trench transistor, and Semiconductor substrate 100 is as the drain electrode of trench transistor, and the part except source area 113 of well region 111 is as the channel region of trench transistor.
It should be noted that, trench transistor and the formation method that is filled with the first groove 131 of gate material layers 151 are not limited to above-described embodiment, the first groove 131 that formation method that also can other existing groove-shaped Metal-oxide-semicondutor barrier schottky device forms above-mentioned trench transistor and is filled with gate material layers 151.
Alternatively, after forming source area 113, carry out annealing in process, with advance source area 113 ions distribute again and the reparation ion implantation process in damage that lattice structure is caused.After annealing in process, as shown in Figure 9, can form on semiconductor region 110 surfaces oxide layer 160.
Continue with reference to shown in Figure 9, form barrier layers 170 and be positioned at dielectric layer 180 above the barrier layer 170 in oxide layer 160.Then form graphical photoresist layer 190 at dielectric layer 180, the part dielectric layer 180 in trench transistor zone 101 is not covered by graphical photoresist layer 190, take graphical photoresist layer 190 as mask dielectric layer 180, barrier layer 170 and oxide layer 160 are carried out etching, expose the trench transistor contact openings 181 of source area 113 and well region 111 with formation.
As shown in figure 10, remove after the graphical photoresist layer 190 shown in Figure 9, form graphical photoresist layer 200 at dielectric layer 180, the part dielectric layer 180 in Schottky barrier zone 102 is not covered by graphical photoresist layer 200, and graphical photoresist layer 200 covers trench transistor contact openings 181.Take graphical photoresist layer 200 as mask dielectric layer 180 is carried out the first etching, expose the opening 182 on barrier layer 170 with formation, opening 182 is used for defining the position of Schottky Barrier Contact opening.In one embodiment, the material on barrier layer 170 is silicon nitride or silicon-oxygen nitride, the material of dielectric layer 180 is for utilizing the TEOS(tetraethoxysilane) silica or the boron-doping phosphorosilicate glass (BPSG) that form, can select a kind of lithographic method under this condition, the etching selection ratio of barrier layer 170 and dielectric layer 180 is much smaller than 1 in this lithographic method.Because the etching selection ratio of barrier layer 170 and dielectric layer 180 is less than 1, therefore can with barrier layer 170 as the etching terminal detection architecture, namely stop the first etching when exposing barrier layer 170 in the first etch step.Certainly, the material of barrier layer 170 and dielectric layer 180 is not limited to above-described embodiment, barrier layer 170 and dielectric layer 180 also can utilize other material to make, as long as the material of barrier layer 170 and dielectric layer 180 makes it possible to select a kind of like this lithographic method to form opening 182: the etching selection ratio of barrier layer 170 and dielectric layer 180 is less than 1 in this lithographic method.
As shown in figure 11, carry out the second etching take graphical photoresist layer 200 as mask, to form Schottky Barrier Contact opening 183, Schottky Barrier Contact opening 183 exposes gate material layers 151 and semiconductor region 112.In one embodiment, the second etching is dry etching, and the etching gas that adopts is equal to the etch rate of barrier layer 170, oxide layer 160, gate material layers 151 and semiconductor region 110, like this can be so that the bottom of the Schottky Barrier Contact opening 183 that forms is comparatively smooth.In one embodiment, Schottky Barrier Contact opening 183 enters the degree of depth h of the part of semiconductor region 110 and is
So that groove-shaped Metal-oxide-semicondutor barrier schottky device has better performance.
Contrast Fig. 3 is to shown in Figure 5, in the formation method of existing groove-shaped Metal-oxide-semicondutor barrier schottky device, Schottky Barrier Contact opening 17 is to utilize the first etching and two steps of the second etching to form, and the first etching stopping is (as shown in Figure 3) in dielectric layer 12, because the actual (real) thickness h of dielectric layer 12
1Can fluctuate in the larger context, before carrying out the first etching, can at first measure the actual (real) thickness h of dielectric layer 12
1, then according to the actual (real) thickness h of dielectric layer 12
1Select different technological parameters, so that the actual (real) thickness h of residue dielectric layer 12
2Can in less scope, fluctuate, and then so that Schottky Barrier Contact opening 17 enters the degree of depth h of the part of epitaxial loayer 2
3Can in more among a small circle, fluctuate.
And in the present invention, Schottky Barrier Contact opening 183 is to utilize the first etching and two steps of the second etching to form, and the accurate control of the first etching etching terminal can be realized as the etching terminal detection architecture in barrier layer 170 therefore in the first etch step; In addition, do not need to measure the thickness of dielectric layer 180 and utilize different etch periods to carry out the first etching according to the difference of detect thickness, so that the formation method of Schottky Barrier Contact opening 183 is more simple.Because the first etching can stop on the barrier layer 170 exactly, therefore only can determine that by controlling the second etching technics parameter Schottky Barrier Contact opening 183 enters the degree of depth h of the part of semiconductor region 110 in the second etch step after the first etch step, can accurately control so that Schottky Barrier Contact opening 183 enters the degree of depth h of the part of semiconductor region 110.
As shown in figure 12, remove after the graphical photoresist layer 200 shown in Figure 11, form metal level 210 at dielectric layer 180, Schottky Barrier Contact opening 183 and trench transistor contact openings 181, the semiconductor region 112 of Schottky Barrier Contact opening 183 belows contacts with metal level 210, to form Schottky barrier, wherein, metal level 210 is as the anode of Schottky barrier, and semiconductor region 112 is as the negative electrode of Schottky barrier.In addition, metal level 210 contacts with source area 113 and well region 111.In one embodiment, metal level 210 comprises the first metal layer 211 and is positioned at the second metal level 212 of the first metal layer 211 tops, wherein, the material of the first metal layer 211 is titanium-tungsten and/or titanium-silicon compound, and the material of the second metal level 212 is aluminium or albronze.
In other embodiments, can Semiconductor substrate 100, semiconductor region 110, well region 111 and source area 113 be adjusted into opposite doping type according to the needs of groove-shaped Metal-oxide-semicondutor barrier schottky device.
Above-mentioned explanation by embodiment should be able to make this area professional and technical personnel understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can be in the situation that do not break away from that the spirit and scope of the invention are done various changes to above-described embodiment and modification is apparent according to described principle herein.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (9)
1. the formation method of a groove-shaped Metal-oxide-semicondutor barrier schottky device is characterized in that, comprising:
Semiconductor substrate is provided, its top is provided with semiconductor region, described Semiconductor substrate comprises trench transistor zone and Schottky barrier zone, wherein, be formed with trench transistor in the semiconductor region in trench transistor zone, be formed with first groove of being filled by gate material layers in the semiconductor region in Schottky barrier zone;
Form the barrier layer and be positioned at dielectric layer above the described barrier layer at described semiconductor region;
Form graphical photoresist layer at described dielectric layer, the part dielectric layer in Schottky barrier zone is not covered by described graphical photoresist layer, take described graphical photoresist layer as mask described dielectric layer is carried out the first etching exposes described barrier layer with formation opening;
Carry out the second etching take described graphical photoresist layer as mask, expose the Schottky Barrier Contact opening of described gate material layers and semiconductor region with formation;
Remove after the described graphical photoresist layer, form metal level at described dielectric layer and Schottky Barrier Contact opening, the semiconductor region of described Schottky Barrier Contact opening below contacts with described metal level, to form Schottky barrier.
2. formation method according to claim 1 is characterized in that, the material on described barrier layer is silicon nitride or silicon-oxygen nitride, and the material of described dielectric layer is silica or the boron-doping phosphorosilicate glass that utilizes TEOS to form.
3. formation method according to claim 1 is characterized in that, the degree of depth that described Schottky Barrier Contact opening enters the part of described semiconductor region is
4. formation method according to claim 1 is characterized in that, the material of described gate material layers is polysilicon.
5. formation method according to claim 1, it is characterized in that, described metal level comprises the second metal level of the first metal layer and the side of being located thereon, and the material of described the first metal layer is titanium-tungsten and/or titanium-silicon compound, and the material of described the second metal level is aluminium or aluminium copper.
6. formation method according to claim 1 is characterized in that, is formed with the formation method that is formed with first groove of being filled by gate material layers in the semiconductor region in trench transistor and Schottky barrier zone in the semiconductor region in trench transistor zone and comprises:
Form described the first groove and the second groove in described semiconductor region, described the second groove is arranged in the semiconductor region in trench transistor zone;
In described the first groove and the second groove, form described gate material layers;
Semiconductor region surface in described trench transistor zone forms well region, and the bottom of described the second groove is arranged in the semiconductor region of described well region below, and the doping type of described semiconductor region is the first doping, and the doping type of described well region is the second doping;
Form the source area of the first doping type in the well region of described the second groove both sides, described source area is arranged on the surface of described well region.
7. formation method according to claim 6, it is characterized in that, before described dielectric layer forms graphical photoresist layer, described dielectric layer and barrier layer are carried out etching to form the trench transistor contact openings, described trench transistor contact openings exposes described source area and well region, and described metal level contacts with source area and the well region of described trench transistor contact openings below.
8. formation method according to claim 6 is characterized in that, the doping type of described semiconductor region is N-type, and the doping type of described well region is the P type, and the doping type of described source area is N-type.
9. formation method according to claim 1 is characterized in that, described semiconductor region is epitaxial loayer, and its material is silicon.
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| CN107026174A (en) * | 2015-09-25 | 2017-08-08 | 台湾积体电路制造股份有限公司 | Interdigitated capacitors in gate-division type flash memory technology and forming method thereof |
| US10297608B2 (en) | 2015-09-25 | 2019-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inter-digitated capacitor in split-gate flash technology |
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