CN105097517B - A kind of FinFET and its manufacturing method, electronic device - Google Patents
A kind of FinFET and its manufacturing method, electronic device Download PDFInfo
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Abstract
A kind of FinFET of present invention offer and its manufacturing method, electronic device, the method includes：Semiconductor substrate is provided, multiple fins is formed on a semiconductor substrate, hard mask layer is formed at the top of fin；The first spacer material layer is deposited, to be partially filled with the gap between fin, and covers the top of the hard mask layer；Depositing etch stop layer to be partially filled with the gap between fin, and covers the first spacer material layer；The second spacer material layer is deposited, to be filled up completely the gap between fin；Chemical mechanical grinding is executed, until exposing the top of the hard mask layer；Remove the hard mask layer；Etching removes remaining second spacer material layer；The etching stopping layer in the gap between fin is removed, to expose the part of fin.According to the present invention it is possible to form multiple fins that height is uniform and side wall profile is vertical.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of FinFET and its manufacturing method, electronics
Device.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to that nanotechnology process node, the preparation of semiconductor devices are limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) is arranged, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
The following processing step of prior art generally use forms the fin of FinFET：First, hard mask is formed on substrate
Layer；Then, pattern the hard mask layer, formed for etching substrate be formed on fin it is multiple be isolated from each other cover
Film；Then, etching substrate is to be formed on multiple fins；Then, deposition forms the isolation structure between multiple fins；Most
Afterwards, etching removes the hard mask layer.
In above-mentioned technical process, deposition is formed after the isolation structure, need to first carry out chemical mechanical grinding until
Expose the top of the hard mask layer, then etch the removal hard mask layer and portions of isolation structure, to expose the part of fin.
The deposition of above-mentioned implementation, grinding can all cause the loss of the height of fin, meanwhile, it is formed in the fin of the different zones of substrate
The extent of damage of height is also different, and eventually leads to the decline of device performance.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of FinFET, including：Semiconductor is provided
Substrate is formed with multiple fins on the semiconductor substrate, and hard mask layer is formed at the top of the fin；Deposition first
Spacer material layer with the gap being partially filled between the fin, and covers the top of the hard mask layer；Deposition etch stops
Layer, with the gap being partially filled between the fin, and covers first spacer material layer；The second spacer material layer is deposited,
With the gap being filled up completely between the fin；Chemical mechanical grinding is executed, until exposing the top of the hard mask layer；Removal
The hard mask layer；Etching removes remaining second spacer material layer；It removes in the gap between the fin
Etching stopping layer, to expose the part of the fin.
In one example, the width of the fin is all identical or the fin is divided into the more of different in width
A fins group.
In one example, the processing step for forming the fin includes：Hard mask is formed on the semiconductor substrate
Layer；Pattern the hard mask layer, formed for etch the semiconductor substrate be formed on the fin it is multiple that
The mask of this isolation；The semiconductor substrate is etched to be formed on the fin.
In one example, using patterning process described in self-aligned double patterning case process implementing.
In one example, the hard mask layer includes the oxide skin(coating) and silicon nitride layer being laminated from bottom to top.
In one example, stopped using the first spacer material layer described in gas cluster ion beam process implementing and the etching
The only deposition of layer implements the deposition of second spacer material layer using chemical vapor deposition method.
In one example, the material of first spacer material layer and second spacer material layer is oxide, institute
The material for stating etching stopping layer is silicon nitride.
In one example, the removal for implementing the hard mask layer includes：First use the removal of the first wet etching described hard
Silicon nitride layer in mask layer；The oxide skin(coating) in the hard mask layer is removed using the second wet etching again.
In one example, remaining second spacer material layer is removed using the second wet etching, it is wet using third
Etching stopping layer of the method etching removal in the gap between the fin.
In one example, the corrosive liquid of first wet etching is the mixture of diluted hydrofluoric acid and phosphoric acid, institute
The corrosive liquid for stating the second wet etching is diluted hydrofluoric acid, and the corrosive liquid of the third wet etching is phosphoric acid.
In one embodiment, the present invention also provides a kind of FinFETs manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic device, the electronic device includes the FinFET devices
Part.
According to the present invention it is possible to form multiple fins that height is uniform and side wall profile is vertical.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 H are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one
The schematic cross sectional view of part；
Fig. 2 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
FinFET and its manufacturing method, electronic device.Obviously, execution of the invention is not limited to the technology of semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment one]
The step of A- Fig. 1 H referring to Fig.1, the method for being shown according to an exemplary embodiment of the present one is implemented successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 1A, semiconductor substrate 100 is provided, the constituent material of semiconductor substrate 100, which may be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon etc. doped with impurity.As an example, in one embodiment, semiconductor substrate 100 selects monocrystalline
Silicon materials are constituted.
It is formed with multiple fins 100 ' on a semiconductor substrate 100, the width of fin 100 ' is all identical or fin
100 ' are divided into multiple fins groups with different in width.Formed fin 100 ' processing step include：On a semiconductor substrate 100
Hard mask layer is formed, the hard mask layer is formed and the various suitable techniques that those skilled in the art are familiar with, example may be used
Such as chemical vapor deposition method, the hard mask layer can be the oxide skin(coating) 101 being laminated from bottom to top and silicon nitride layer 102；
Pattern the hard mask layer, formed for etch semiconductor substrate 100 be formed on fin 100 ' it is multiple each other every
From mask, in one embodiment, using patterning process described in self-aligned double patterning case (SADP) process implementing；Etching is partly led
Body substrate 100 is to be formed on fin 100 '.
Then, as shown in Figure 1B, the first spacer material layer 103 is deposited, to be partially filled with the gap between fin 100 ', and
Cover the top of the hard mask layer.In one embodiment, it is described heavy to be implemented using gas cluster ion beam technique (GCIB)
Product, i.e., the described deposition process only occurs on surface in horizontal direction, the side wall in fin 100 ' and the hard mask layer
The first spacer material layer 103 is not formed on side wall.The material of first spacer material layer 103 is oxide, such as silica
(SiO2)。
Then, as shown in Figure 1 C, depositing etch stop layer 104 to be partially filled with the gap between fin 100 ', and cover
First spacer material layer 103.In one embodiment, the deposition is implemented using gas cluster ion beam technique (GCIB), i.e.,
The deposition process only occurs on surface in horizontal direction, the side wall of fin 100 ', the side wall of the hard mask layer and
Etching stopping layer 104 is not formed on the side wall of first spacer material layer 103.The material of etching stopping layer 104 is silicon nitride
(SiN)。
Then, as shown in figure iD, the second spacer material layer 105 is deposited, to be filled up completely the gap between fin 100 '.
In one embodiment, the deposition is implemented using chemical vapor deposition method (CVD).The material of second spacer material layer 105 is excellent
Select oxide, such as HARP.
Then, as referring to figure 1E, chemical mechanical grinding is executed, until exposing the top of the hard mask layer, that is, passes through institute
State the of grinding removal the second spacer material layer of part 105 and being laminated from bottom to top on the top of the hard mask layer
One spacer material layer 103 and etching stopping layer 104.
Then, as shown in fig. 1F, the silicon nitride layer 102 in the hard mask layer is removed.In one embodiment, using
One wet etching removes silicon nitride layer 102, and the corrosive liquid of first wet etching is the mixing of diluted hydrofluoric acid and phosphoric acid
Object.
Then, as shown in Figure 1 G, the oxide skin(coating) 101 in the hard mask layer and remaining second spacer material layer are removed
105, to expose the part of fin 100 '.In one embodiment, the removal is implemented using the second wet etching, described second
The corrosive liquid of wet etching is diluted hydrofluoric acid.
Then, as shown in fig. 1H, the etching stopping layer 104 in gap of the removal between fin 100 ', to form tool
There is the fin 100 ' of certain height.In one embodiment, the removal, the third wet method are implemented using third wet etching
The corrosive liquid of etching is phosphoric acid.
So far, the processing step that the method for completing according to an exemplary embodiment of the present one is implemented.It, can according to the present invention
To form multiple fins 100 ' that height is uniform and side wall profile is vertical.
The flow of the step of reference Fig. 2, the method for being shown according to an exemplary embodiment of the present one is implemented successively
Figure, the flow for schematically illustrating manufacturing process.
In step 201, semiconductor substrate is provided, is formed with multiple fins on a semiconductor substrate, at the top of fin
It is formed with hard mask layer；
In step 202, the first spacer material layer is deposited, to be partially filled with the gap between fin, and is covered described hard
The top of mask layer；
In step 203, depositing etch stop layer to be partially filled with the gap between fin, and covers the first isolation material
The bed of material；
In step 204, the second spacer material layer is deposited, to be filled up completely the gap between fin；
In step 205, chemical mechanical grinding is executed, until exposing the top of the hard mask layer；
In step 206, the hard mask layer is removed；
In step 207, etching removes remaining second spacer material layer；
In a step 208, the etching stopping layer in gap of the removal between fin, to expose the part of fin.
[exemplary embodiment two]
Next, the making of entire FinFET can be completed by subsequent technique, it is possible to implement conventional FinFET
Device front end fabrication process：
In an exemplary embodiment, first, gate structure is formed at the both sides of fin 100 ' and top, as showing
Example, gate structure includes the gate dielectric stacked gradually from bottom to top, gate material layers and grid hard masking layer.
Specifically, the constituent material of gate dielectric includes oxide, such as silica (SiO2).Select SiO2As
When the constituent material of gate dielectric, gate dielectric, thickness 8-50 are formed by rapid thermal oxidation process (RTO)
Angstrom, however, it is not limited to this thickness.
The constituent material of gate material layers includes polysilicon, metal, conductive metal nitride, conductive metal oxide
With it is one or more in metal silicide, wherein metal can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride
Object includes titanium nitride (TiN)；Conductive metal oxide includes yttrium oxide (IrO2)；Metal silicide includes titanium silicide
(TiSi).When selecting constituent material of the polysilicon as gate material layers, optional low-pressure chemical vapor phase deposition (LPCVD) technique
Gate material layers are formed, process conditions include：Reaction gas is silane (SiH4), flow is 100~200sccm, preferably
150sccm；Temperature in reaction chamber is 700~750 DEG C；Pressure in reaction chamber is 250~350mTorr, preferably
300mTorr；The reaction gas can also include buffer gas, and the buffer gas is helium (He) or nitrogen (N2), stream
Amount is 5~20 liters/min (slm), preferably 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer include one kind in oxide, nitride, nitrogen oxides and amorphous carbon or
It is a variety of, wherein oxide includes boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), ethyl orthosilicate (TEOS), undoped silicon
Glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride includes silicon nitride
(SiN)；Nitrogen oxides includes silicon oxynitride (SiON).Those skilled in the art may be used in the forming method of grid hard masking layer
Any prior art being familiar with, preferably chemical vapour deposition technique (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure
Learn vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
Then, ion implanting is executed, to form source/drain in not by the fin 100 ' of gate structure covering.Then, exist
Gate structure both sides form the offset side wall against gate structure, constituent material SiO2, one kind in SiN, SiON or
Combination thereof.During gate structure both sides form offset side wall, the both sides of fin 100 ' can also form offset side wall,
Therefore, next, removal is located at the offset side wall of 100 ' both sides of fin.Then, using the offset side wall as mask, using extension
Growth technique expands the area for the fin 100 ' being located at except gate structure region, to reduce the electricity of the source/drain formed before
Resistance.
Then, sequentially form on a semiconductor substrate 100 with can generate stress characteristics contact etch stop layer and
Interlayer dielectric layer executes chemical mechanical grinding to expose the top of gate structure.Then, gate structure is removed, in the ditch left
High k- metal gate structures are formed in slot, as an example, this structure includes the high k dielectric layer being laminated from bottom to top, coating, work(
Function metal, barrier layer and metal material layer.Next, another interlayer dielectric layer is formed, then, in above-mentioned interlayer dielectric layer
The middle contact hole for forming the top and the source/drain region pole that are connected to the metal gate structure is being revealed by the contact hole
The top and the source/drain region of the metal gate structure gone out extremely on form self-aligned silicide, filling metal (is usually
Tungsten) interconnecting metal layer and the self-aligned silicide for connecting and implementing back end fabrication and being formed are formed in the contact hole
Contact plug.
Next, it is possible to implement conventional FinFET back end fabrication, including：The shape of multiple interconnecting metal layers
It is completed at, generally use dual damascene process；The formation of metal pad, for implementing wire bonding when device encapsulation.
[exemplary embodiment three]
The present invention also provides a kind of electronic devices comprising two method manufactures according to an exemplary embodiment of the present
FinFET.The electronic device can be mobile phone, tablet computer, laptop, net book, game machine, television set,
Any electronic product such as VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products for including the semiconductor devices.The electronic device due to the use of the semiconductor devices, thus has
There is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacturing method of FinFET, including：
Semiconductor substrate is provided, is formed with multiple fins on the semiconductor substrate, is formed at the top of the fin hard
Mask layer；
The first spacer material layer is deposited, with the gap being partially filled between the fin, and covers the top of the hard mask layer；
Depositing etch stop layer with the gap being partially filled between the fin, and covers first spacer material layer；
The second spacer material layer is deposited, with the gap being filled up completely between the fin；
Chemical mechanical grinding is executed, until exposing the top of the hard mask layer；
Remove the hard mask layer；
Etching removes remaining second spacer material layer；
The etching stopping layer in the gap between the fin is removed, to expose the part of the fin.
2. according to the method described in claim 1, it is characterized in that, the width of the fin is all identical or the fin
It is divided into multiple fins groups with different in width.
3. according to the method described in claim 2, it is characterized in that, the processing step for forming the fin includes：Described half
Hard mask layer is formed on conductor substrate；The hard mask layer is patterned, is formed for etching the semiconductor substrate on it
Form multiple masks being isolated from each other of the fin；The semiconductor substrate is etched to be formed on the fin.
4. according to the method described in claim 3, it is characterized in that, being patterned using described in self-aligned double patterning case process implementing
Journey.
5. according to the method described in claim 1, it is characterized in that, the hard mask layer includes the oxide being laminated from bottom to top
Layer and silicon nitride layer.
6. according to the method described in claim 1, it is characterized in that, using described in gas cluster ion beam process implementing first every
Deposition from material layer and the etching stopping layer implements the heavy of second spacer material layer using chemical vapor deposition method
Product.
7. according to the method described in claim 6, it is characterized in that, first spacer material layer and second isolated material
The material of layer is oxide, and the material of the etching stopping layer is silicon nitride.
8. according to the method described in claim 5, it is characterized in that, the removal for implementing the hard mask layer includes：First use the
One wet etching removes the silicon nitride layer in the hard mask layer；It is removed in the hard mask layer using the second wet etching again
Oxide skin(coating).
9. according to the method described in claim 8, it is characterized in that, using the second wet etching removal remaining described second every
From material layer, using etching stopping layer of the third wet etching removal in the gap between the fin.
10. according to the method described in claim 9, it is characterized in that, the corrosive liquid of first wet etching is diluted hydrogen
The corrosive liquid of the mixture of fluoric acid and phosphoric acid, second wet etching is diluted hydrofluoric acid, the third wet etching
Corrosive liquid is phosphoric acid.
11. a kind of FinFET using the method manufacture described in one of claim 1-10.
12. a kind of electronic device, the electronic device includes the FinFET described in claim 11.
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| TW201946112A (en) * | 2018-04-24 | 2019-12-01 | 美商應用材料股份有限公司 | Method to remove III-V materials in high aspect ratio structures |
| EP3621118A1 (en) * | 2018-09-07 | 2020-03-11 | IMEC vzw | A method for producing a gate cut structure on an array of semiconductor fins |
| CN111668369A (en) * | 2020-06-15 | 2020-09-15 | 浙江驰拓科技有限公司 | Preparation method of bottom electrode in magnetic memory device |
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