CN105845573A - FinFET device and manufacturing method thereof, and electronic apparatus - Google Patents
FinFET device and manufacturing method thereof, and electronic apparatus Download PDFInfo
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- CN105845573A CN105845573A CN201510019288.1A CN201510019288A CN105845573A CN 105845573 A CN105845573 A CN 105845573A CN 201510019288 A CN201510019288 A CN 201510019288A CN 105845573 A CN105845573 A CN 105845573A
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- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
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- 239000007788 liquid Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a FinFET device and a manufacturing method thereof, and an electronic apparatus. The method comprises the following steps: providing a semiconductor substrate, wherein multiple fins are formed on the semiconductor substrate, and a hard mask layer is formed on the top of each fin; forming a liner oxide layer to cover the surface of the semiconductor substrate, the sidewalls of the fins and the sidewalls and tops of the hard mark layers; depositing an isolation material layer to fully fill the gaps between the fins; exposing part of the fins, and forming fins of specific height; and sequentially implementing well injection and channel stop injection to adjust the threshold voltage and control source/drain punch-through. According to the invention, by implementing channel stop injection through use of carbon ions, nitrogen ions or the combination thereof, the source/drain punch-through inhibiting ability of the FinFET is enhanced effectively.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of FinFET and
Its manufacture method, electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly by not
The disconnected size reducing IC-components realizes with the speed improving it.At present, due to
Pursue semi-conductor industry in high device density, high-performance and low cost and have advanced to nanotechnology
Process node, the preparation of semiconductor device is limited by various physics limits.
Along with constantly reducing of cmos device size, from manufacturing and the challenge of design aspect
Promote the development of three dimensional design such as FinFET (FinFET).Relative to existing
Planar transistor, FinFET is the sophisticated semiconductor device for 20nm and following process node
Part, it can effectively control scaled the caused short channel effect being difficult to overcome of device
Should, it is also possible to be effectively improved on substrate the density of transistor array formed, meanwhile,
Grid in FinFET is arranged around fin (fin-shaped channel), therefore can control from three faces
Electrostatic processed, the performance in terms of Electrostatic Control is the most prominent.
Prior art generally uses following processing step to form the fin of FinFET: first,
Hard mask layer is formed on substrate；Then, pattern described hard mask layer, formed and be used for etching lining
The end, is to be formed on multiple masks being isolated from each other of fin；Then, etching substrate is with at it
The multiple fin of upper formation；Then, the isolation structure between the multiple fin of formation of deposits；Finally,
Described hard mask layer is removed in etching.
After forming the fin of FinFET, need to implement channel stop and inject to control by part
Exhaust the source/drain break-through being positioned at bottom fin caused.If implementing what channel stop injected
Injecting ion is boron ion or fluorine boron ion, boron ion or fluorine boron during subsequent implementation heat treatment
Ion has the advantages that to be prone to isolation structure diffusion, the boron ion that causes being positioned at channel region or
The dose losses of fluorine boron ion, does not has the effect controlling source/drain break-through.
It is, therefore, desirable to provide a kind of method, to solve the problems referred to above.
Summary of the invention
For the deficiencies in the prior art, the present invention provides the manufacture method of a kind of FinFET,
Including: Semiconductor substrate is provided, is formed with multiple fin on the semiconductor substrate, in institute
The top stating fin is formed with hard mask layer；Form pad oxide layer, described partly lead to cover
The surface of body substrate, the sidewall of described fin and the sidewall of described hard mask layer and top；Heavy
Long-pending spacer material layer, to be filled up completely with the gap between described fin；Expose the portion of described fin
Point, and then form the fin with certain height；Implement well region successively to inject and channel stop note
Enter, with adjusting threshold voltage and control source/drain break-through.
In one example, for N-type channel, the injection ion that described well region injects
For boron ion or fluorine boron ion.
In one example, the injection ion that described channel stop injects is carbon ion, Nitrogen ion
Or combination, described injection ion is relative to the direction being perpendicular to described Semiconductor substrate
Incident angle be 10 °-20 °.
In one example, the width of described fin is the most identical, or described fin is divided into tool
There are multiple fins group of different in width.
In one example, the processing step forming described fin includes: serve as a contrast at described quasiconductor
Hard mask layer is formed at the end；Pattern described hard mask layer, formed and be used for etching described quasiconductor
Substrate is to be formed on multiple masks being isolated from each other of described fin；Etch described quasiconductor
Substrate is to be formed on described fin.
In one example, described hard mask layer includes oxide skin(coating) and the nitrogen of stacking from bottom to top
SiClx layer.
In one example, before depositing described spacer material layer, also include forming covering described
The step of the protective layer of pad oxide layer；Before implementing the injection of described well region, it is additionally included in institute
The surface stating the fin exposed forms the step of oxide thin layer thing.
In one example, the enforcement step of the part exposing described fin includes: implement high temperature
Annealing, so that described spacer material layer densification；Perform cmp, until exposing institute
State the top of hard mask layer；Remove described hard mask layer and the described spacer material layer of part.
In one embodiment, the present invention also provides for a kind of using said method to manufacture
FinFET.
In one embodiment, the present invention also provides for a kind of electronic installation, described electronic installation bag
Include described FinFET.
According to the present invention, by implement described injection ion be carbon ion, Nitrogen ion or the two
Combination channel stop inject, can effectively strengthen the source/drain break-through rejection ability of FinFET.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 H is the step that the method according to exemplary embodiment of the present one is implemented successively
The schematic cross sectional view of the rapid device obtained respectively；
Fig. 2 is the stream of the step that the method according to exemplary embodiment of the present one is implemented successively
Cheng Tu.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to
The FinFET of explaination present invention proposition and manufacture method, electronic installation.Obviously, originally
The execution of invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.This
The preferred embodiment of invention is described in detail as follows, but in addition to these describe in detail, the present invention
Can also have other embodiments.
It should be appreciated that term ought be used in this manual " to comprise " and/or " including "
Time, it indicates and there is described feature, entirety, step, operation, element and/or assembly, but
Do not preclude the presence or addition of other features one or more, entirety, step, operation, element,
Assembly and/or combinations thereof.
[exemplary embodiment one]
With reference to Figure 1A-Fig. 1 H, illustrated therein is the side of according to an exemplary embodiment of the present
The schematic cross sectional view of the device that the step that method is implemented successively obtains respectively.
First, as shown in Figure 1A, it is provided that Semiconductor substrate 100, Semiconductor substrate 100
Constituent material can use unadulterated monocrystal silicon, monocrystal silicon etc. doped with impurity.As showing
Example, in one embodiment, Semiconductor substrate 100 selects single crystal silicon material to constitute.
Being formed with multiple fin 100 ' on a semiconductor substrate 100, the width of fin 100 ' is complete
Portion is identical, or fin 100 ' is divided into multiple fins group with different in width.Form fin
The processing step of 100 ' including: forms hard mask layer on a semiconductor substrate 100, is formed described
Hard mask layer can use the various suitable technique that those skilled in the art are familiar with, such as, change
Learning gas-phase deposition, described hard mask layer can be the oxide skin(coating) 101 of stacking from bottom to top
With silicon nitride layer 102；Pattern described hard mask layer, formed and be used for etching Semiconductor substrate 100
To be formed on multiple masks being isolated from each other of fin 100 ', in one embodiment, adopt
With patterning process described in self-aligned double patterning case (SADP) process implementing；Etching quasiconductor lining
The end 100, is to be formed on fin 100 '.
Then, as shown in Figure 1B, pad oxide layer 103 is formed, to cover quasiconductor lining
The surface at the end 100, the sidewall of fin 100 ' and the sidewall of described hard mask layer and top.?
In one embodiment, use on-site steam to generate technique (ISSG) and form pad oxide layer
103。
Then, as shown in Figure 1 C, formed and cover pad oxide layer 103 protective layer 104,
With the technique of subsequent implementation, height and the characteristic size of fin 100 ' are caused damage.A reality
Execute in example, use the chemical vapor deposition method (FCVD) with flowable to form protection
Layer 104, the material of protective layer 104 can be silicon nitride.
Then, as shown in figure ip, depositing isolation material layer 105, to be filled up completely with fin 100 '
Between gap.In one embodiment, the chemical gaseous phase with flowable is used to deposit work
Skill implements described deposition.The material of spacer material layer 105 can be with selective oxidation thing, such as
HARP。
Then, as referring to figure 1e, expose the part of fin 100 ', and then formation has specific
The fin 100 ' of height.As example, implement high annealing, so that spacer material layer 105
Densification, the temperature of described high annealing can be 700 DEG C-1000 DEG C；Execution chemical machinery grinds
Mill, until exposing the top of described hard mask layer；Remove the silicon nitride layer in described hard mask layer
102, in one embodiment, use wet etching to remove silicon nitride layer 102, described wet method
The corrosive liquid of etching is the Fluohydric acid. of dilution；Remove the oxide skin(coating) 101 in described hard mask layer
With part spacer material layer 105, to expose the part of fin 100 ', and then formation has specific
The fin 100 ' of height, in one embodiment, uses SiCoNi etching to implement this removal,
The etching gas of described SiCoNi etching mainly has NH3And NF3。
Then, as shown in fig. 1f, oxide thin layer thing is formed on the surface of the fin 100 ' exposed,
It is beneficial to subsequent implementation well region inject and channel stop injection.In one embodiment, use now
Field steam generates technique and forms this oxide thin layer thing.
Then, as shown in Figure 1 G, implement well region to inject, with adjusting threshold voltage.For N
For type raceway groove, the injection ion that well region injects is boron ion or fluorine boron ion.
Then, as shown in fig. 1h, implement channel stop and inject, to control to be positioned at fin 100 '
The source/drain break-through of bottom.The injection ion that described channel stop injects is carbon ion, Nitrogen ion
Or combination, injects ion relative to the entering of direction being perpendicular to Semiconductor substrate 100
Firing angle degree is 10 °-20 °.
So far, the technique step that the method for according to an exemplary embodiment of the present is implemented is completed
Suddenly.According to the present invention, it is carbon ion, Nitrogen ion or the group of the two by implementing injection ion
The channel stop closed injects, and can effectively strengthen the source/drain break-through rejection ability of FinFET.
With reference to Fig. 2, illustrated therein is the method reality successively of according to an exemplary embodiment of the present
The flow chart of the step executed, for schematically illustrating the flow process of manufacturing process.
In step 201, it is provided that Semiconductor substrate, multiple fin it is formed with on a semiconductor substrate
Sheet, is formed with hard mask layer at the top of fin；
In step 202., formed pad oxide layer, with cover Semiconductor substrate surface,
The sidewall of fin and the sidewall of described hard mask layer and top；
In step 203, depositing isolation material layer, with the gap being filled up completely with between fin；
In step 204, expose the part of fin, and then form the fin with certain height；
In step 205, implement well region successively to inject and channel stop injection, to regulate threshold value
Voltage and control source/drain break-through.
[exemplary embodiment two]
It follows that the making of whole FinFET can be completed by subsequent technique, permissible
The FinFET front end fabrication process that enforcement is conventional:
In an exemplary embodiment, first, grid are formed in the both sides of fin 100 ' and top
Electrode structure, as example, gate dielectric that grid structure includes stacking gradually from bottom to top,
Gate material layers and grid hard masking layer.
Specifically, the constituent material of gate dielectric includes oxide, such as silicon dioxide
(SiO2).Select SiO2During as the constituent material of gate dielectric, pass through rapid thermal oxidation
Technique (RTO) forms gate dielectric, and its thickness is 8-50 angstrom, but is not limited to
This thickness.
The constituent material of gate material layers include polysilicon, metal, conductive metal nitride,
One or more in conductive metal oxide and metal silicide, wherein, metal can be
Tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride includes titanium nitride (TiN)；
Conductive metal oxide includes yttrium oxide (IrO2)；Metal silicide includes titanium silicide (TiSi).
When selecting polysilicon as the constituent material of gate material layers, can be selected for low-pressure chemical vapor phase deposition
(LPCVD) technique forms gate material layers, and its process conditions include: reacting gas is silane
(SiH4), its flow is 100～200sccm, preferably 150sccm；Temperature in reaction chamber is
700～750 DEG C；Pressure in reaction chamber is 250～350mTorr, preferably 300mTorr；
Described reacting gas can also include that buffer gas, described buffer gas are helium (He) or nitrogen
(N2), its flow is 5～20 liters/min of (slm), preferably 8slm, 10slm or 15slm.
The constituent material of grid hard masking layer includes that oxide, nitride, nitrogen oxides and nothing are fixed
One or more in shape carbon, wherein, oxide includes boron-phosphorosilicate glass (BPSG), phosphorus silicon
Glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin coating glass
Glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD)；Nitride
Including silicon nitride (SiN)；Nitrogen oxides includes silicon oxynitride (SiON).Grid hard masking layer
Forming method can use any prior art that those skilled in the art are familiar with, preferably change
Learn vapour deposition process (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical phase
Deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), PECVD
Deposition (PECVD).
Then, ion implanting is performed, to be formed in the fin 100 ' not covered by grid structure
Source/drain.Then, form the offset side wall against grid structure in grid structure both sides, its
Constituent material is SiO2, one in SiN, SiON or combinations thereof.Tie at grid
During structure both sides form offset side wall, the both sides of fin 100 ' also can form offset side wall,
Therefore, it follows that remove the offset side wall being positioned at fin 100 ' both sides.Then, with described partially
Shifting side wall is mask, the fin outside using epitaxial growth technology expansion to be positioned at grid structure region
The area of 100 ', the resistance of the source/drain formed before reducing.
Then, sequentially form on a semiconductor substrate 100 there is the contact that can produce stress characteristics
Hole etching stopping layer and interlayer dielectric layer, perform cmp to expose the top of grid structure
Portion.Then, remove grid structure, the groove stayed formed high k-metal gate structure,
As example, this structure includes the high k dielectric layer of stacking from bottom to top, cover layer, work function
Metal level, barrier layer and metal material layer.It follows that form another interlayer dielectric layer, then,
Above-mentioned interlayer dielectric layer is formed connect the top of described metal gate structure and described source/
The contact hole of pole, drain region, by described contact hole, on the top of the described metal gate structure exposed
Portion and described source/drain region extremely on form self-aligned silicide, filler metal (usually tungsten)
Formed in described contact hole connect implement back end fabrication and the interconnecting metal layer that formed with
The contact plug of described self-aligned silicide.
Next, it is possible to implement conventional FinFET back end fabrication, including: many
The formation of individual interconnecting metal layer, generally uses dual damascene process to complete；Metal pad
Formed, wire bonding during for implementing device encapsulation.
[exemplary embodiment three]
The present invention also provides for a kind of electronic installation, and it includes according to an exemplary embodiment of the present two
Method manufacture FinFET.Described electronic installation can be mobile phone, panel computer,
Notebook computer, net book, game machine, television set, VCD, DVD, navigator, photograph
Camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment,
Can also be any intermediate products including described semiconductor device.Described electronic installation, due to
Employ described semiconductor device, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for FinFET, including:
Semiconductor substrate is provided, is formed with multiple fin on the semiconductor substrate, described
The top of fin is formed with hard mask layer；
Form pad oxide layer, to cover the surface of described Semiconductor substrate, described fin
Sidewall and the sidewall of described hard mask layer and top；
Depositing isolation material layer, to be filled up completely with the gap between described fin；
Expose the part of described fin, and then form the fin with certain height；
Successively implement well region inject and channel stop inject, with adjusting threshold voltage and control source/
Leakage break-through.
Method the most according to claim 1, it is characterised in that for N-type channel
Speech, the injection ion that described well region injects is boron ion or fluorine boron ion.
Method the most according to claim 1, it is characterised in that described channel stop is noted
The injection ion entered is carbon ion, Nitrogen ion or combination, and described injection ion is relative
Incident angle in the direction being perpendicular to described Semiconductor substrate is 10 °-20 °.
Method the most according to claim 1, it is characterised in that the width of described fin
The most identical, or described fin is divided into multiple fins group with different in width.
Method the most according to claim 1, it is characterised in that form described fin
Processing step includes: form hard mask layer on the semiconductor substrate；Pattern and described firmly cover
Film layer, formed for etch described Semiconductor substrate be formed on described fin multiple that
The mask of this isolation；Etch described Semiconductor substrate to be formed on described fin.
Method the most according to claim 1, it is characterised in that described hard mask layer bag
Include oxide skin(coating) and the silicon nitride layer of stacking from bottom to top.
Method the most according to claim 1, it is characterised in that deposit described isolation material
Before the bed of material, also include the step forming the protective layer covering described pad oxide layer；Implement
Before described well region injects, be additionally included in described in the surface of fin exposed form oxide thin layer thing
Step.
Method the most according to claim 1, it is characterised in that expose described fin
The enforcement step of part includes: implement high annealing, so that described spacer material layer densification；
Perform cmp, until exposing the top of described hard mask layer；Remove described hard mask
Layer and the described spacer material layer of part.
9. the FinFET that the method using one of claim 1-8 described manufactures.
10. an electronic installation, described electronic installation includes the FinFET described in claim 9
Device.
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| CN108630610A (en) * | 2017-03-21 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN109686779A (en) * | 2017-10-19 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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