CN106601685B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
- Publication number
- CN106601685B CN106601685B CN201510672973.4A CN201510672973A CN106601685B CN 106601685 B CN106601685 B CN 106601685B CN 201510672973 A CN201510672973 A CN 201510672973A CN 106601685 B CN106601685 B CN 106601685B
- Authority
- CN
- China
- Prior art keywords
- work
- pmos
- coating
- function layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000011248 coating agent Substances 0.000 claims abstract description 82
- 238000000576 coating method Methods 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 176
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 33
- 238000009792 diffusion process Methods 0.000 claims description 25
- 239000003292 glue Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 11
- 230000006870 function Effects 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910010038 TiAl Inorganic materials 0.000 claims 2
- 238000003860 storage Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 22
- 150000002500 ions Chemical class 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000012212 insulator Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000026267 regulation of growth Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- -1 LDD ion Chemical class 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
Abstract
The present invention relates to a kind of semiconductor devices and preparation method thereof, electronic device.The method includes the steps S1: providing semiconductor substrate, is formed with PMOS and memory NMOS on the semiconductor substrate, the groove for removing and being formed after the dummy gate around fin is formed in the PMOS and the memory NMOS；Step S2: high k dielectric layer and the first coating are formed on the fin of the PMOS and the memory NMOS that expose in stating groove；Step S3: the second coating and the first work-function layer are formed on first coating of the PMOS；Step S4: the second work-function layer is formed in first work-function layer of the PMOS and first coating of the memory NMOS；Step S5: to being diffused stopping ion implanting in second work-function layer of the PMOS and the boundary the memory NMOS.The method can prevent the Al in the memory NMOS from diffusing to the PMOS grid, to improve the performance and yield of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
The raising of performance of integrated circuits mainly improves its speed by constantly reducing the size of integrated circuit device
Come what is realized.Currently, especially working as dimensions of semiconductor devices since semi-conductor industry has advanced to nanotechnology process node
When dropping to 22nm or following, the challenge from manufacture and design aspect has resulted in three dimensional design such as FinFET
(FinFET) development.
Relative to existing planar transistor, the FinFET is in the side such as channel control and reduction shallow ridges channel effect
Face has more superior performance；Planar gate is set to above the channel, and the grid described in FinFET is surround
The fin setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
It is usually injected with lower channel ion in FinFET to enhance the mobility of device and mix at random
Clutter moves (RDF) performance, and work-function layer is extremely important for the adjusting of device, grid work after usually selecting in device fabrication process
Skill forms work-function layer, in order to meet the needs of device, needs to remove coating TiN/TAN for NMOS and depositing Ti AL makees
For work-function layer, but for SRAM device, due to the diffusion of Al, for SRAM PMOS area device mismatch performance into one
Step is degenerated, and device performance and yield are reduced.
Therefore the method needs to improve the method there are above-mentioned many drawbacks at present, described to eliminate
Problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention is in order to overcome the problems, such as that presently, there are provide a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, PMOS and memory NMOS are formed on the semiconductor substrate, described
The groove that removal is formed after the dummy gate of fin is formed in the PMOS and memory NMOS；
Step S2: high K is formed on the fin of the PMOS and the memory NMOS that expose in stating groove
Dielectric layer and the first coating；
Step S3: the second coating and the first work-function layer are formed on first coating of the PMOS；
Step S4: in first work-function layer of the PMOS and first coating of the memory NMOS
Form the second work-function layer；
Step S5: to being diffused stopping in second work-function layer of the PMOS and the boundary the memory NMOS
Ion implanting, to prevent the diffusion of the boundary ion.
Optionally, the method may further include the diffusion and stop before or after ion implanting described second
In work-function layer formed glue line the step of, and the diffusion stopping ion implanting after on the glue line shape
The step of at conductive material, to form metal gates.
Optionally, in the step S5, in second work function of the PMOS and the boundary the memory NMOS
Carbon ion implantation is executed in layer, to form carbon containing diffusion stop layer on the boundary.
Optionally, the step S3 includes:
Step S31: second covering is formed on first coating of the PMOS and memory NMOS
Layer and first work-function layer；
Step S32: forming protective layer in first work-function layer of the PMOS, to cover the institute in the PMOS
State the first work-function layer；
Step S33: the described first supratectal first work-function layer of the memory NMOS and described is removed
Second coating, to expose first coating；
Step S34: removing the protective layer, to expose first work-function layer of the PMOS.
Optionally, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
The present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the semiconductor substrate, wherein the grid packet of the memory NMOS
Include the high k dielectric layer, the first coating and the second work-function layer stacked gradually；The grid of the PMOS includes the institute stacked gradually
State high k dielectric layer, first coating, the second coating, the first work-function layer and second work-function layer；
Diffusion stop layer, positioned at second work-function layer of the grid boundary of the PMOS and the memory NMOS
In.
Optionally, the grid of the PMOS and the memory NMOS are still further comprised positioned at second work-function layer
On glue line and conductive material.
Optionally, the semiconductor devices still further comprises NMOS and transmission transistor, wherein the NMOS and described
The grid of transmission transistor includes the high k dielectric layer being sequentially depositing and the second work-function layer.
Optionally, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
Optionally, the diffusion stop layer selects TiCAl.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor devices.
In order to solve the problems in the existing technology the present invention, provides a kind of semiconductor devices and preparation method thereof,
The device in the logic area and the active area is adjusted by adjusting the composition of the gate stack in the method
Threshold voltage, wherein the memory NMOS gate lamination include include the high k dielectric layer stacked gradually, the first coating
(TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W)；；The grid of the PMOS includes stacking gradually
The high k dielectric layer, the first coating (TiN), the second coating (TaN), the first work-function layer (TiN), the second work function
Layer (TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W).Wherein, in the memory NMOS and institute
The boundary for stating PMOS grid is formed with diffusion stop layer, to prevent the Al in the memory NMOS from diffusing to the PMOS grid
Pole, to improve the performance and yield of semiconductor devices.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 a-1h is the preparation process schematic diagram of semiconductor devices described in the present invention one is specifically implemented；
Fig. 2 is the process flow chart of the preparation of semiconductor devices described in the present invention one is specifically implemented.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
Embodiment one
In order to solve the problems in the existing technology the present invention, provides a kind of preparation side of new semiconductor devices
Method is with reference to the accompanying drawing further described the method for the invention.
Wherein, Fig. 1 a-1h is the preparation process schematic diagram of semiconductor devices described in the present invention one is specifically implemented；Fig. 2
The process flow chart of the preparation of semiconductor devices described in specifically implementing for the present invention one.
Firstly, executing step 101, semiconductor substrate 101 is provided and executes ion implanting, to form trap.
Specifically, as shown in Figure 1a, the semiconductor substrate can be in the following material being previously mentioned in this step
At least one: silicon (SSOI) is laminated on insulator, SiGe (S- is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Semiconductor substrate 101 selects silicon in this embodiment.
Wherein the semiconductor substrate includes logic area and active area, wherein in the active area again include NMOS area and
PMOS area includes PMOS area in the logic area to form NMOS device and active area PMOS in subsequent steps.
Wherein, the active area can form various memory devices, such as can form SRAM, described in this embodiment
SRAM NMOS and SRAM PMOS is formed in active area, using as pull up transistor, pull-down transistor and transmission
Transistor.
Then pad oxide skin(coating) (Pad oxide) is formed on the semiconductor substrate, wherein the pad oxide skin(coating)
The forming method of (Pad oxide) can be formed by the method for deposition, such as the side such as chemical vapor deposition, atomic layer deposition
Method can also be formed by the surface of semiconductor substrate described in thermal oxide, and details are not described herein.
Further, the step of executing ion implanting can also be further included, in this step to serve as a contrast in the semiconductor
Trap is formed in bottom, wherein the ionic species and method for implanting that inject can be method commonly used in the art, herein not one by one
It repeats.
The method can further include following steps:
Step 1011:
Multiple fins are formed on a semiconductor substrate, and the width of fin is all identical or fin is divided into different width
Multiple fins groups of degree.
Specifically, the forming method of the fin is not limited to a certain kind, and a kind of illustrative formation side is given below
Method: hard mask layer (not shown) is formed on a semiconductor substrate, art technology can be used by forming the hard mask layer
The various suitable techniques that personnel are familiar with, such as chemical vapor deposition process, the hard mask layer can be layer from bottom to top
Folded oxide skin(coating) and silicon nitride layer；The hard mask layer is patterned, is formed for etching semiconductor substrate to be formed on
Multiple exposure masks being isolated from each other of fin are schemed using described in self-aligned double patterning case (SADP) process implementing in one embodiment
Case process；Semiconductor substrate is etched to be formed on fin structure.
Step 1012:
Depositing isolation material layer, to cover the fin structure.
Specifically, depositing isolation material layer, to be filled up completely the gap between fin structure.In one embodiment, it adopts
Implement the deposition with the chemical vapor deposition process with flowability.The material of spacer material layer can choose oxide,
Such as HARP.
Then spacer material layer described in etch-back, until the object height of the fin.Specifically, material is isolated described in etch-back
The bed of material with fin described in exposed portion, and then forms the fin with certain height.
Step 1013:
Dummy gate oxide skin(coating) and dummy gate are formed, on the spacer material layer to cover the fin.
Specifically, as shown in Figure 1a, dummy gate oxide skin(coating) and dummy gate material layer are deposited in this step.
Wherein, the dummy gate oxide skin(coating) can select common oxide, such as SiO2, the dummy gate material
The bed of material can select semiconductor material commonly used in the art, such as polysilicon can be selected etc., it is not limited to it is a certain, herein
Will not enumerate,
The deposition method of the gate material layers can select the methods of chemical vapor deposition or atomic layer deposition.
Then the dummy gate oxide skin(coating) and gate material layers are patterned, to form the virtual grid around the fin
Pole.Specifically, photoresist layer is formed in the dummy gate material layer, then exposure development, to form opening, then with institute
Stating photoresist layer is dummy gate material layer described in mask etch, to be formed in the logic area NMOS and memory NMOS
NMOS dummy gate forms PMOS dummy gate in the active area PMOS.
Step 1014:
Offset side wall and clearance wall are formed on the side wall of the dummy gate structure.
Specifically, the method may further include the two sides shape of the NMOS dummy gate and PMOS dummy gate
At offset side wall (offset spacer).The material of the offset side wall is, for example, silicon nitride, silica or silicon oxynitride etc.
Insulating materials.With further becoming smaller for device size, the channel length of device is smaller and smaller, and the particle of source-drain electrode injects depth
Also smaller and smaller, the effect of offset side wall be with improve formed transistor channel length, reduce short-channel effect and by
The hot carrier's effect caused by short-channel effect.The technique that offset side wall is formed in gate structure two sides can be chemical gaseous phase
It deposits, in the present embodiment, the thickness of the offset side wall may diminish to 80 angstroms.
Optionally, LDD ion implanting step and work are executed in the NMOS dummy gate and PMOS dummy gate two sides
Change.
Optionally, it is formed on the clearance wall of the NMOS dummy gate and on the offset side wall of the PMOS dummy gate
Clearance wall.
Specifically, on being formed by offset side wall formed clearance wall (Spacer), the clearance wall can for silica,
A kind of or their combinations are constituted in silicon nitride, silicon oxynitride.As embodiment in the one of the present embodiment, the clearance wall is
Silica, silicon nitride collectively constitute, specifically comprises the processes of: the first silicon oxide layer, the first silicon nitride layer are formed on a semiconductor substrate
And second silicon oxide layer, clearance wall is then formed using engraving method.
Step 1015:
Source and drain LDD injection is executed, and in the two sides epitaxial growth of semiconductor material layer of the dummy gate, to form lifting
Source and drain.
Specifically, the common method of ability can be used in this step and execute source and drain LDD injection, details are not described herein.
Optionally, the first groove is formed in the semiconductor substrate of PMOS dummy gate two sides, optionally, institute
Stating the first groove is " ∑ " connected in star, can select PMOS source drain region described in dry etching in this step, is lost in the dry method
CF can be selected in quarter4、CHF3, in addition add N2、CO2、O2One of as etching atmosphere, wherein gas flow be CF410-
200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, the etching pressure is 30-150mTorr, when etching
Between be 5-120s.
Then, one stressor layers of extension growth regulation in first groove, to form PMOS source leakage.
Further, first stressor layers select SiGe in the present invention, and the extension can be selected and subtract in the present invention
Press one of extension, low-temperature epitaxy, selective epitaxy, liquid phase epitaxy, hetero-epitaxy, molecular beam epitaxy.
Further, the second groove is formed in the semiconductor substrate of NMOS dummy gate two sides, and described
Two stressor layers of extension growth regulation in second groove, to form NMOS source and drain.
Second stressor layers can select SiC layer, can select reduced pressure epitaxy, low-temperature epitaxy, selective epitaxy, outside liquid phase
Prolong, one of hetero-epitaxy, molecular beam epitaxy form second stressor layers.
In addition, the method still further comprises the step of forming contact etch stop layer, the forming method can be with
Various methods commonly used in the art are selected, details are not described herein.
Optionally, ion implanting step can also be executed again after the step 106 and carry out rapid thermal annealing.
It can inhibit the depth and horizontal proliferation of impurity in the present invention in order to demonstrate,prove activator impurity again, execute the ion note
Rapid thermal annealing is carried out after entering, optionally, the rapid thermal annealing temperature is 1000-1050 DEG C.
Step 1016:
It deposits the interlayer dielectric layer 102 and planarizes, to fill the gap between the dummy gate.
Specifically, it interlevel dielectric deposition 102 and planarizes, planarizes described to interlayer dielectric layer to the dummy gate
Top.
Wherein, the interlayer dielectric layer can select dielectric material commonly used in the art, such as various oxides etc.,
Interlayer dielectric layer 102 can select SiO in the embodiment2, thickness is not limited to a certain numerical value.
The non-limiting example of the planarization process includes mechanical planarization method and chemically mechanical polishing planarization side
Method.
Step 102 is executed, removes the dummy gate oxide skin(coating) and the dummy gate, and in the PMOS and described
High k dielectric layer and the first coating are formed on the fin of memory NMOS.
Specifically, as shown in Figure 1a, the dummy gate oxide skin(coating) and the dummy gate are removed, respectively described
The groove is formed in logic area PMOS, the memory NMOS.
The dummy gate and the dummy gate oxide skin(coating) can be removed simultaneously in this step, can also first be removed
The dummy gate, then the dummy gate oxide skin(coating) again.
In this embodiment, the dummy gate is removed first.
The dummy gate is removed, groove is formed.The method of the removal can be photoetching and etching.In etching process
Gas used includes HBr, is used as main etch gas；It further include the O as etching make-up gas2Or Ar, it can mention
The quality of high etching.
Then the method for selecting SiCoNi removes the dummy gate oxide skin(coating), to expose the fin.In the step
In in order to reduce remove the dummy gate oxide skin(coating) during damage to other materials layer, no longer selection HF lost
It carves, but selects the higher SiCoNi processing procedure of selectivity, the dummy gate oxide skin(coating) is removed by the method, it will not be right
Device damages.
Optionally, SiCoNi processing procedure is selected to remove the dummy gate oxide skin(coating) 102, wherein the SiCoNi processing procedure
Various parameters can select conventional parameter.
Then boundary layer and high k dielectric layer 103 are formed.
It is formed by the method for chemical oxidation on the surface of the fin.
Specifically, the method for the chemical oxidation can be to be heated, with oxygen in oxygen containing atmosphere in this step
Change the semiconductor substrate exposed, form oxide skin(coating) on the semiconductor substrate, using as boundary layer.
Optionally, the oxygen-containing atmosphere can be pure oxygen, air, oxygen-enriched air or ozone, it is not limited to a certain.
In this embodiment, it selects ozone to carry out chemical oxidation to the semiconductor substrate 101, forms boundary layer.
Further, the temperature and time of the chemical oxide is not limited to a certain range, can select conventional parameter.
High k dielectric layer 103 is formed in the boundary layer.Specifically, as illustrated in figure 1 c, it sinks first in the virtual opening
Product high k dielectric layer 103, wherein the high k dielectric layer can select dielectric material commonly used in the art, such as in Hf02Middle introducing
The elements such as Si, Al, N, La, Ta simultaneously optimize the ratio of each element obtained hafnium etc..Form the side of the high k dielectric layer
Method can be physical gas-phase deposition or atom layer deposition process.
Hf0 is formed in an embodiment of the present invention2Dielectric layer, with a thickness of 15 to 60 angstroms.
Then the first coating 104 is formed on the high k dielectric layer.
Optionally, first coating selects TiN.
Step 103 is executed, forms the second coating 104 and the first work function on first coating of the PMOS
Layer 105.
Specifically, as shown in Figure 1 b, only second is formed on first coating of the PMOS in this step to cover
Cap rock 104 and the first work-function layer 105, and the second coating 104 is formed on the first coating of the no longer described memory NMOS
With the first work-function layer 105.
Wherein, second coating selects TaN；First work-function layer selects TiN；
The second coating 104 and the first work-function layer 105 are wherein formed on first coating of the PMOS
Method may comprise steps of:
Firstly, forming the second coating 104 and the first function on the fin of the PMOS and the memory NMOS
Function layer 105, as shown in Figure 1 b.
Then, protective layer is formed in first work-function layer of the PMOS, to cover fin described in the PMOS
Second coating of on piece and first work-function layer, as illustrated in figure 1 c.
Then, second coating on the fin of the memory NMOS and first work function are removed
Layer, as shown in Figure 1 d；
The protective layer is finally removed, as shown in fig. le.
Step 104 is executed, forms second in first work-function layer 105 of the PMOS and memory NMOS
Work-function layer 106 and glue line 107.
Specifically, as shown in Figure 1 f, wherein second work-function layer 106 selects TiAl, and the glue line 107 selects
Use TiN.
Step 105 is executed, diffusion is executed on the boundary of the PMOS and the memory NMOS and stops ion implanting, to prevent
The only diffusion of the boundary ion.
Specifically, as shown in Figure 1 g, the region other than the PMOS and the boundary the memory NMOS in this step
Protective layer is formed, the borderline region of the PMOS and the memory NMOS are only exposed.
It executes diffusion and stops ion implanting, to prevent the diffusion of the boundary ion.
Specifically, carbon ion implantation is executed on the boundary of the PMOS and the memory NMOS, in the boundary shape
At carbon containing diffusion stop layer.
The position of the carbon ion implantation is located at the boundary of the PMOS and the memory NMOS gate in this step
Region, in this step, the ion implantation energy needs are sufficiently large, and the carbon atom enable reaches the position of predetermined depth,
Optionally, the energy of the ion implanting is 20~30KeV in this step.
Wherein, second work-function layer selects TiAl, then is TiCAl in the diffusion stop layer that the boundary is formed.
Step 106 is executed, conductive material is deposited on the glue line, to cover the glue line while fill institute
State groove.
Specifically, as shown in figure 1h, the glue line selects TiN in this step, and the conductive material selects metal,
Such as W.
So far, the introduction of the correlation step of the semiconductor devices preparation of the embodiment of the present invention is completed.Above-mentioned steps it
It afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the problems in the existing technology the present invention, provides a kind of semiconductor devices and preparation method thereof,
The device in the logic area and the active area is adjusted by adjusting the composition of the gate stack in the method
Threshold voltage, wherein the memory NMOS gate lamination include include the high k dielectric layer stacked gradually, the first coating
(TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W)；；The grid of the PMOS includes stacking gradually
The high k dielectric layer, the first coating (TiN), the second coating (TaN), the first work-function layer (TiN), the second work function
Layer (TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W).Wherein, in the memory NMOS and institute
The boundary for stating PMOS grid is formed with diffusion stop layer, to prevent the Al in the memory NMOS from diffusing to the PMOS grid
Pole, to improve the performance and yield of semiconductor devices.
Referring to Fig. 2, the process flow chart that the present invention prepares the semiconductor devices is shown, it is whole for schematically illustrating
The process of a manufacturing process, comprising the following steps:
Step S1: semiconductor substrate is provided, PMOS and memory NMOS are formed on the semiconductor substrate, described
The groove that removal is formed after the dummy gate of fin is formed in the PMOS and memory NMOS；
Step S2: high K is formed on the fin of the PMOS and the memory NMOS that expose in stating groove
Dielectric layer and the first coating；
Step S3: the second coating and the first work-function layer are formed on first coating of the PMOS；
Step S4: in first work-function layer of the PMOS and first coating of the memory NMOS
Form the second work-function layer；
Step S5: to being diffused stopping in second work-function layer of the PMOS and the boundary the memory NMOS
Ion implanting, to prevent the diffusion of the boundary ion.
Embodiment two
The present invention also provides a kind of semiconductor devices, the semiconductor devices selects method system described in embodiment one
It is standby.
Semiconductor substrate；
Semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the semiconductor substrate, wherein the grid packet of the memory NMOS
Include the high k dielectric layer, the first coating and the second work-function layer stacked gradually；The grid of the PMOS includes the institute stacked gradually
State high k dielectric layer, the first coating, the second coating, the first work-function layer and the second work-function layer；
Diffusion stop layer, positioned at the boundary of the grid of the PMOS and the memory NMOS.
Optionally, the grid of the PMOS and the memory NMOS are still further comprised positioned at second work-function layer
On glue line and conductive material.
Optionally, the semiconductor devices still further comprises NMOS and transmission transistor, wherein the NMOS and described
The grid of transmission transistor includes the high k dielectric layer being sequentially depositing and the second work-function layer.
Optionally, first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
Optionally, the diffusion stop layer selects TiCAl.
Wherein, the semiconductor devices includes semiconductor substrate 101, and the semiconductor substrate can be following be previously mentioned
At least one of material: silicon (SSOI) is laminated on insulator, SiGe is laminated on insulator for silicon, silicon-on-insulator (SOI)
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Semiconductor serves as a contrast in this embodiment
Silicon is selected at bottom 101.
Specifically, it is formed with multiple fins on a semiconductor substrate, the width of fin is all identical or fin is divided into tool
There are multiple fins groups of different in width.
The semiconductor devices still further comprises the metal gate structure around fin setting, the metal gate knot
It is formed on the side wall of structure and offsets side wall and clearance wall.
The material of the offset side wall is, for example, silicon nitride, the insulating materials such as silica or silicon oxynitride.With device
Size further becomes smaller, and the channel length of device is smaller and smaller, and the particle injection depth of source-drain electrode is also smaller and smaller, deviates side
The effect of wall is to reduce short-channel effect and due to caused by short-channel effect to improve the channel length of the transistor formed
Hot carrier's effect.
It is formed on being formed by offset side wall clearance wall (Spacer), the clearance wall can be silica, nitridation
A kind of or their combinations are constituted in silicon, silicon oxynitride.
Lifting source and drain is formed in the two sides of the gate structure.Wherein, PMOS source leakage selection SiGe, the NMOS source and drain
Select SiC layer.
The gate structure includes boundary layer, selects ozone to carry out chemistry to the semiconductor substrate 101 in the present invention
Oxidation forms boundary layer.
Wherein, the memory NMOS gate lamination include include the high k dielectric layer stacked gradually, the first coating
(TiN), the second work-function layer (TiAl), glue line (TiN) and conductive layer (W)；
The grid of the PMOS includes the high k dielectric layer stacked gradually, the first coating (TiN), the second coating
(TaN), the first work-function layer (TiN), the second work-function layer (TiN), the second work-function layer (TiAl), glue line (TiN) and
Conductive layer (W).
Wherein, it is formed with diffusion stop layer in the boundary of the memory NMOS and the PMOS grid, to prevent
It states the Al in memory NMOS and diffuses to the PMOS grid, to improve the performance and yield of semiconductor devices.
Embodiment three
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment two.Wherein, semiconductor device
Part is semiconductor devices described in embodiment two, or the semiconductor devices that the preparation method according to embodiment one obtains.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, PMOS and memory NMOS are formed on the semiconductor substrate, in the PMOS
With the groove for being formed with removal formation after the dummy gate of fin in the memory NMOS；
Step S2: high k dielectric is formed on the fin of the PMOS and the memory NMOS that expose in stating groove
Layer and the first coating；
Step S3: the second coating and the first work-function layer are formed on first coating of the PMOS；
Step S4: it is formed in first work-function layer of the PMOS and first coating of the memory NMOS
Second work-function layer；
Step S5: to being diffused stopping ion in second work-function layer of the PMOS and the boundary the memory NMOS
Injection, to prevent the diffusion of the boundary ion.
2. the method according to claim 1, wherein the method may further include the diffusion stop from
Before or after son injection the step of forming glue line in second work-function layer, and in diffusion stopping ion
After injection the step of forming conductive material on the glue line, to form metal gates.
3. the method according to claim 1, wherein in the step S5, in the PMOS and the storage
Carbon ion implantation is executed in second work-function layer on the boundary device NMOS, is stopped with being formed on the boundary containing Carbon diffusion
Layer.
4. the method according to claim 1, wherein the step S3 includes:
Step S31: formed on first coating of the PMOS and memory NMOS second coating and
First work-function layer；
Step S32: forming protective layer in first work-function layer of the PMOS, to cover described in the PMOS
One work-function layer；
Step S33: the described first supratectal first work-function layer and described second of the memory NMOS is removed
Coating, to expose first coating；
Step S34: removing the protective layer, to expose first work-function layer of the PMOS.
5. the method according to claim 1, wherein first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
6. a kind of semiconductor devices, comprising:
Semiconductor substrate is formed with multiple fins in the semiconductor substrate；
PMOS and memory NMOS, positioned at the top of the semiconductor substrate, wherein the grid of the memory NMOS includes ring
Around the high k dielectric layer stacked gradually, the first coating and the second work-function layer of fin setting；The grid packet of the PMOS
Include the high k dielectric layer stacked gradually around fin setting, first coating, the second coating, the first function
Function layer and second work-function layer；
Diffusion stop layer, in second work-function layer of the grid boundary of the PMOS and the memory NMOS.
7. semiconductor devices according to claim 6, which is characterized in that the grid of the PMOS and the memory NMOS
Still further comprise the glue line and conductive material being located in second work-function layer.
8. semiconductor devices according to claim 6, which is characterized in that the semiconductor devices still further comprises NMOS
And transmission transistor, wherein the grid of the NMOS and the transmission transistor includes the high k dielectric layer and second being sequentially depositing
Work-function layer.
9. semiconductor devices according to claim 6, which is characterized in that first coating selects TiN；
Second coating selects TaN；
First work-function layer selects TiN；
Second work-function layer selects TiAl.
10. semiconductor devices according to claim 6 or 9, which is characterized in that the diffusion stop layer selects TiCAl.
11. a kind of electronic device, including semiconductor devices described in one of claim 6 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510672973.4A CN106601685B (en) | 2015-10-16 | 2015-10-16 | A kind of semiconductor devices and preparation method thereof, electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510672973.4A CN106601685B (en) | 2015-10-16 | 2015-10-16 | A kind of semiconductor devices and preparation method thereof, electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106601685A CN106601685A (en) | 2017-04-26 |
| CN106601685B true CN106601685B (en) | 2019-09-27 |
Family
ID=58553945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510672973.4A Active CN106601685B (en) | 2015-10-16 | 2015-10-16 | A kind of semiconductor devices and preparation method thereof, electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106601685B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545734B (en) * | 2017-09-22 | 2021-12-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109545749A (en) * | 2017-09-22 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111293118B (en) * | 2018-12-10 | 2023-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104810368A (en) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos transistor and forming method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7682891B2 (en) * | 2006-12-28 | 2010-03-23 | Intel Corporation | Tunable gate electrode work function material for transistor applications |
-
2015
- 2015-10-16 CN CN201510672973.4A patent/CN106601685B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752447A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN104810368A (en) * | 2014-01-28 | 2015-07-29 | 中芯国际集成电路制造(上海)有限公司 | Cmos transistor and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106601685A (en) | 2017-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102350007B1 (en) | Method for fabricating semiconductor device | |
| CN105428238B (en) | A kind of FinFET and preparation method thereof and electronic device | |
| CN104347630A (en) | Semiconductor device and fabricating the same | |
| US9331079B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN106601619B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106601678B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106601685B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106601741B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN105244318B (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| CN108122840A (en) | A kind of semiconductor devices and preparation method, electronic device | |
| CN106558610B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106601675B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN106558546B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN104979289B (en) | A kind of semiconductor devices and preparation method thereof | |
| CN106910685A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN106601684B (en) | Semiconductor device, preparation method thereof and electronic device | |
| CN105990119B (en) | Manufacturing method of semiconductor device, semiconductor devices and electronic device | |
| CN106158640A (en) | A kind of semiconductor device and preparation method thereof, electronic installation | |
| CN105990240B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN105789131A (en) | Semiconductor device and preparation method thereof and electronic device | |
| CN106601620B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN109087890A (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN107527814A (en) | A kind of semiconductor devices and preparation method, electronic installation | |
| CN108206160A (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| CN108735670A (en) | A kind of semiconductor devices and its manufacturing method and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |