CN108206160A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108206160A CN108206160A CN201611187661.5A CN201611187661A CN108206160A CN 108206160 A CN108206160 A CN 108206160A CN 201611187661 A CN201611187661 A CN 201611187661A CN 108206160 A CN108206160 A CN 108206160A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic devices.The method includes：Semiconductor substrate is provided, be formed with gate structure on the semiconductor substrate and covers the offset side wall material layer of the gate structure and the Semiconductor substrate；The offset side wall material layer is etched, to form offset side wall on the side wall of the gate structure and expose the Semiconductor substrate；The offset side wall and the Semiconductor substrate exposed are ashed, to form offset oxide skin(coating) in the semiconductor substrate surface；Perform cleaning step；Oxidation step is performed, to increase the thickness of the offset oxide skin(coating) of semiconductor substrate surface.The technique can be very good compatible with current technique, it is simple for process, easy to implement, and the influence that device deviates when can avoid waiting for the time less than 50 minutes, the defects of being caused in gate etch processes can be repaired by increasing the oxidation step, further improves the performance and yield of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.At present, the semiconductor of high device density, high-performance and low cost is pursued
Industry has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to lower Nano grade, partly leads
The preparation of body device receives the limitation of various physics limits.
When the size of semiconductor devices drops to lower Nano grade, gate critical dimension (gate CD) is corresponding in device
Be reduced into 24nm.With the reduction of technology node, traditional gate dielectric layer is constantly thinning, and transistor leakage amount increases therewith,
The problems such as causing semiconductor devices power wastage.To solve the above problems, avoiding high-temperature process simultaneously, the prior art provides
A kind of solution that high-K metal gate is substituted to polysilicon gate.
In high-K metal gate preparation process, there is similar trend, such as each ginseng for the parameter in NFET device
Number shows as growth trend or downward trend, and only typical NFET device is affected, other devices are then unaffected.Its
In, clearance wall residual oxide thickness and technique stand-by period in NFET device in substrate (such as spacer etch ashing
To the stand-by period between cleaning step) there is very big association.The clearance wall residual oxide thickness is by significant impact
The performance of device, when the clearance wall residual oxide thickness be less than 25 angstroms when device will suffer from offset risk in addition make device
Part fails.
Therefore, to solve the above-mentioned problems, it is necessary to propose a kind of manufacturing method of new semiconductor devices.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, a kind of manufacturing method of semiconductor devices, institute are provided in the embodiment of the present invention one
The method of stating includes：
Semiconductor substrate is provided, be formed on the semiconductor substrate gate structure and the covering gate structure and
The offset side wall material layer of the Semiconductor substrate；
The offset side wall material layer is etched, to form offset side wall on the side wall of the gate structure and reveal
Go out the Semiconductor substrate；
The offset side wall and the Semiconductor substrate exposed are ashed, in the semiconductor substrate surface shape
Into offset oxide skin(coating)；
Perform cleaning step；
Oxidation step is performed, to increase the thickness of the offset oxide skin(coating) of the semiconductor substrate surface.
Optionally, the oxidation step uses stove internal oxidation process.
Optionally, the temperature of the oxidation step is 650-750 DEG C.
Optionally, the time of the oxidation step is 1.5-2.5 minutes.
Optionally, the increased thickness of oxide skin(coating) is deviated described in the oxidation step at 5 angstroms or more.
Optionally, after the oxidation step it is described offset oxide skin(coating) overall thickness at 25 angstroms or more.
Optionally, the method still further comprises the step of being measured to the thickness of the offset oxide skin(coating).
Optionally, the gate structure includes the boundary layer, high k dielectric layer and the dummy gate that sequentially form, the method
The step of still further comprising the removal dummy gate, then forming metal gates.
Optionally, the Semiconductor substrate includes NMOS area and PMOS area, is formed in the NMOS area
NMOS gate is formed with PMOS grids in the PMOS area.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes：
Semiconductor substrate；
Gate structure, in the Semiconductor substrate；
Offset side wall, on the side wall of the gate structure；
Deviate oxide skin(coating), in the Semiconductor substrate on the outside of the offset side wall, the offset oxide skin(coating)
Thickness at 25 angstroms or more.
Optionally, the Semiconductor substrate includes NMOS area and PMOS area, is formed in the NMOS area
NMOS gate is formed with PMOS grids in the PMOS area.
The present invention also provides a kind of electronic device, including above-mentioned semiconductor devices.
, the offset oxide skin(coating) too short to the cleaning process stand-by period is ashed in order to solve offset side wall in current technique
Thickness it is small, the problems such as device performance is made to be affected, the present invention provides a kind of semiconductor devices and its manufacturing method, in institute
State in the preparation process of semiconductor devices increases by a re-oxidation step after the offset side wall ashing, cleaning, so that described
The thickness of the offset oxide skin(coating) in Semiconductor substrate increases, and the oxidation step can not only be situated between to avoid to high-K gate
The influence of electric layer, and the technique can be very good with current technique it is compatible, it is simple for process, easy to implement, and can be to avoid
The influence of device offset, can be repaired in gate etch processes by increasing the oxidation step and made when stand-by period is less than 50 minutes
Into the defects of, further improve the performance and yield of the semiconductor devices.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows a kind of schematic flow chart of the manufacturing method of semiconductor devices of one embodiment of the invention；
Fig. 2A-Fig. 2 C show a kind of correlation step shape of the manufacturing method of semiconductor devices in one embodiment of the invention
Into structure sectional view；
Fig. 3 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree rather than the binary from injection region to non-injection regions change.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
The preparation process of semiconductor devices mainly includes the following steps that at present：First, Semiconductor substrate is provided, described half
Gate structure is formed on conductor substrate and covers the offset side wall material layer of the gate structure and the Semiconductor substrate；It is right
The offset side wall material layer is etched, and described is partly led with forming offset side wall on the side wall of the gate structure and exposing
Body substrate；The offset side wall and the Semiconductor substrate exposed are ashed, in the semiconductor substrate surface shape
Into offset oxide skin(coating)；Perform cleaning step.Wherein, the stand-by period between the cineration step and the cleaning step and institute
Stating has very big association between the performance of device, is less than when the stand-by period between the cineration step and the cleaning step
At 50 minutes, the device reliability risk dramatically increases.
In order to solve this problem, the present inventor is through a large number of experiments and analysis finds the semiconductor devices
Described in offset the thickness of oxide skin(coating) and the cineration step and the cleaning step between stand-by period have it is very big
Relevance, when being more than 50 minutes the stand-by period between the cineration step and the cleaning step, the offset of the device
The thickness of oxide skin(coating) can be normally reached 25 angstroms or more, therefore device performance will not be impacted, and when the ashing walks
When stand-by period between rapid and described cleaning step is less than 50 minutes, the thickness of the offset oxide skin(coating) of the device is caused to exist
Less than 25 angstroms of possibility greatly increases, when the device offset oxide skin(coating) thickness below 25 angstroms when can cause device
The problems such as threshold voltage shift, the reliability and yield for making device reduce.
For this purpose, the present invention provides a kind of manufacturing method of semiconductor devices, the method includes：
Semiconductor substrate is provided, be formed on the semiconductor substrate gate structure and the covering gate structure and
The offset side wall material layer of the Semiconductor substrate；
The offset side wall material layer is etched, to form offset side wall on the side wall of the gate structure and reveal
Go out the Semiconductor substrate；
The offset side wall and the Semiconductor substrate exposed are ashed, in the semiconductor substrate surface shape
Into offset oxide skin(coating)；
Perform cleaning step；
Oxidation step is carried out to the offset side wall and the Semiconductor substrate exposed, to increase the Semiconductor substrate
The thickness of the offset oxide skin(coating) on surface.
The defects of being caused in gate etch processes can be repaired by increasing the oxidation step in the present invention, is further carried
The performance and yield of the high semiconductor devices.
Embodiment one
Below with reference to the accompanying drawings the preparation method of the semiconductor devices of the present invention is described in detail, Fig. 1 shows the present invention
The preparation technology flow chart of the semiconductor devices；Fig. 2A -2C show the system of semiconductor devices described in one embodiment of the invention
Preparation Method is implemented to obtain the diagrammatic cross-section of structure.
The present invention provides a kind of preparation method of semiconductor devices, as shown in Figure 1, the key step packet of the preparation method
It includes：
Step S1：Semiconductor substrate is provided, is formed with gate structure and the covering grid on the semiconductor substrate
The offset side wall material layer of pole structure and the Semiconductor substrate；
Step S2：The offset side wall material layer is etched, is deviated with being formed on the side wall of the gate structure
Side wall simultaneously exposes the Semiconductor substrate；
Step S3：The offset side wall and the Semiconductor substrate exposed are ashed, to be served as a contrast in the semiconductor
Bottom surface forms offset oxide skin(coating)；
Step S4：Perform cleaning step；
Step S5：Oxidation step is performed, to increase the thickness of the offset oxide skin(coating) of the semiconductor substrate surface.
The method of the invention is further described below in conjunction with the accompanying drawings.
First, step 1 is performed, Semiconductor substrate 201 is provided, is formed with gate structure 202 on the semiconductor substrate
And cover the offset side wall material layer 203 of the gate structure and the Semiconductor substrate.
Specifically, as shown in Figure 2 A, Semiconductor substrate 201 is provided, active area is formed in the Semiconductor substrate 201,
Including NMOS area and PMOS area, be respectively formed in the NMOS area and PMOS area NMOS gate structure and
PMOS gate structures.
Wherein, the Semiconductor substrate 201 can be at least one of following material being previously mentioned：On silicon, insulator
Silicon (SSOI) etc. is laminated on silicon (SOI), insulator.
In addition, active area can be defined in Semiconductor substrate 201.Others can also be included on the active region to be had
Source device, for convenience, there is no indicate in shown figure.
Then shallow trench isolation is formed over the substrate, and the Semiconductor substrate is divided into active area and isolation
Area.
Wherein, the forming method of the shallow trench isolation can select method commonly used in the prior art, for example, first,
The first oxide skin(coating) and the first nitride layer are sequentially formed in Semiconductor substrate 201.Then, dry etch process is performed, according to
It is secondary that first nitride layer, the first oxide skin(coating) and Semiconductor substrate are performed etching to form groove.It specifically, can be first
It is formed on nitride layer and has figuratum photoresist layer, using the photoresist layer as mask is carried out to the first nitride layer dry method quarter
Erosion to transfer a pattern to the first nitride layer, and is mask to the first oxide skin(coating) using photoresist layer and the first nitride layer
It is performed etching with Semiconductor substrate, to form groove.Certainly groove can also be formed using other methods, due to the technique with
To be known in the art, therefore no longer it is described further.
Then, shallow trench isolation material is filled in the trench, to form fleet plough groove isolation structure.It specifically, can be
Shallow trench isolation material is formed on mononitride layer and in groove, the shallow trench isolation material can be silica, nitrogen oxidation
Silicon and/or other existing advanced low-k materials；It performs chemical mechanical milling tech and stops on the first nitride layer, with
Being formed has fleet plough groove isolation structure.
The Semiconductor substrate can be divided into NMOS area and PMOS area by the shallow trench isolation in the present invention.
Then, NMOS gate is formed in the NMOS area, PMOS grids is formed in the PMOS area.
Specifically, it is sequentially depositing oxide skin(coating), high k dielectric layer and gate material layers on the semiconductor substrate.
Wherein, the oxide skin(coating) is chosen as silica, forming method can be deposition silicon dioxide material layer or
Semiconductor substrate described in person's high-temperature oxydation is formed.
The gate material layers may include polysilicon layer, metal layer, conductive metal nitride layer, conductive metal oxidation
It is one or more in nitride layer and metal silicide layer.
Optionally, the gate material layers select polysilicon in this embodiment.
The polysilicon selects epitaxy method to be formed, and specifically, is described further by taking silicon as an example in a particular embodiment,
Reaction gas can include hydrogen (H2) carry silicon tetrachloride (SiCl4) or trichlorosilane (SiHCl3), silane (SiH4) and two
Chlorine hydrogen silicon (SiH2Cl2) etc. at least one of enter and be placed with the reative cell of silicon substrate, it is anti-to carry out high temeperature chemistry in reative cell
Should, siliceous reaction gas is made to restore or thermally decompose, generated silicon atom is grown epitaxially.
Wherein, the k values (dielectric constant) of the high k dielectric layer are usually more than 3.9, constituent material include hafnium oxide,
Hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium,
Strontium oxide strontia titanium, aluminium oxide etc., preferably hafnium oxide, zirconium oxide or aluminium oxide.
Chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) or physics gas may be used in the high k dielectric layer
The suitable technique such as phase sedimentation (PVD) is formed.
Then the oxide skin(coating), high k dielectric layer and gate material layers are performed etching to obtain gate structure 202.
The method may further include the NMOS gate and PMOS grids both sides form offset side wall material layer
203。
The offset side wall material layer 203 e.g. silicon nitride, the insulating materials such as silica or silicon oxynitride.With device
Part size further becomes smaller, and the channel length of device is less and less, and the particle injection depth of source-drain electrode is also less and less, offset
The effect of side wall is the channel length to improve the transistor formed, reduces short-channel effect and since short-channel effect causes
Hot carrier's effect.
The offset side wall material layer 203 uses silicon nitride in this embodiment.
Step 2 is performed, the offset side wall material layer is etched, to be formed on the side wall of the gate structure
Offset side wall simultaneously exposes the Semiconductor substrate.
Specifically, as shown in Figure 2 B, the institute removed in the active area and the shallow trench isolation is etched in this step
Offset side wall material layer is stated, retains the offset side wall material layer on the gate structure sidewall, to form offset side wall
2031。
Optionally, in this step, dry etching, reactive ion etching (RIE), ion beam milling, plasma are selected
Etching removes the offset side wall material layer in the active area and the shallow trench isolation.
Step 3 is performed, the offset side wall and the Semiconductor substrate exposed are ashed, partly to be led described
Body substrate surface forms offset oxide skin(coating).
Specifically, as shown in Figure 2 B, the offset side wall and the Semiconductor substrate exposed are carried out in this step
Ashing, wherein the temperature of the ashing can be 800-1200 DEG C, the time of the ashing is 1-300s.
Offset oxide skin(coating) 204 can be formed on the surface of the Semiconductor substrate by the cineration step.
Step 4 is performed, performs cleaning step.
Optionally, in this step with diluted hydrofluoric acid DHF (wherein comprising HF, H2O2And H2O) to the device
Surface carries out prerinse.
Deviated described in the semiconductor devices oxide skin(coating) thickness and the cineration step and the cleaning step it
Between stand-by period have very big relevance, when the stand-by period between the cineration step and the cleaning step be more than 50
During minute, the thickness of the offset oxide skin(coating) of the device can be normally reached 25 angstroms or more, therefore device performance will not be made
Into influence, and when being less than 50 minutes the stand-by period between the cineration step and the cleaning step, cause the device
Possibility of the thickness below 25 angstroms of offset oxide skin(coating) greatly increase, when the thickness of the offset oxide skin(coating) of the device
The problems such as device threshold voltage being caused to deviate when below 25 angstroms, the reliability and yield for making device reduce.
Although offset can be made when the stand-by period between the cineration step and the cleaning step was more than 50 minutes
Oxide layer thicknesses increase, but can substantially reduce the yield of the semiconductor devices.
In order to solve this problem, step 5 is performed, oxygen is carried out to the offset side wall and the Semiconductor substrate exposed
Change step, to increase the thickness of the offset oxide skin(coating) of the semiconductor substrate surface.
Specifically, as shown in Figure 2 C, the oxidation step uses stove internal oxidation process.
Optionally, the temperature of the oxidation step is 650-750 DEG C, such as the temperature of the oxidation step is 700 DEG C.
Optionally, the time of the oxidation step is 1.5-2.5 minutes, such as the time of the oxidation step is 2 minutes.
Optionally, the increased thickness of oxide skin(coating) is deviated described in the oxidation step at 5 angstroms or more.
Optionally, after the oxidation step it is described offset oxide skin(coating) overall thickness at 25 angstroms or more.
Increase by a re-oxidation step after the offset side wall ashing, cleaning in the method for the invention, so that institute
Stating the thickness of the offset oxide skin(coating) in Semiconductor substrate increases, and device is inclined when can avoid waiting for the time less than 50 minutes
The influence of shifting, and the defects of being caused in gate etch processes can be repaired by increasing the oxidation step, further improve institute
State the performance and yield of semiconductor devices.
Step 6 is performed, the thickness of the offset oxide skin(coating) is measured.
Specifically, the method, which still further comprises, measures the thickness of the offset oxide skin(coating), to determine institute
State the requirement that offset oxide skin(coating) meets target thickness.
After this step, the method can further include but be not limited to following steps：
LDD ion implantings step is performed in the NMOS gate and PMOS grids both sides and is activated.
Specifically, it is formed and source/drain (LDD) is lightly doped in the substrate of NMOS gate and PMOS grids both sides.Institute
It can be ion implantation technology or diffusion technique to state the method to form LDD.The ionic type of LDD injection will be according to will form
Semiconductor devices electrical decision, that is, the device formed is NMOS device, then the foreign ion mixed in LDD injection technologies is
One kind or combination in phosphorus, arsenic, antimony, bismuth；If the device formed is PMOS device, the foreign ion injected is boron.According to institute
The concentration of the foreign ion needed, ion implantation technology can be completed with one or multi-step.
Optionally, after having performed the LDD, the step of further comprising thermal annealing, to activate the LDD ions,
The annealing steps are usually to be placed in the substrate under the protection of high vacuum or high-purity gas, are heated to certain temperature and carry out
Heat treatment is chosen as nitrogen or inert gas in high-purity gas of the present invention, and the temperature of the thermal anneal step is 800-
1200 DEG C, 1050 DEG C are chosen as, the thermal anneal step time is 1-300s.
Clearance wall is formed on the offset side wall of the NMOS gate structure and the PMOS gate structures.
Specifically, on the offset side wall formed formed clearance wall (Spacer), the clearance wall can be silica,
A kind of or their combinations are formed in silicon nitride, silicon oxynitride.As an optimal enforcement mode of the present embodiment, the gap
Wall is silica, silicon nitride collectively constitutes, and concrete technology is：The first silicon oxide layer, the first nitridation are formed on a semiconductor substrate
Then silicon layer and the second silicon oxide layer form clearance wall using engraving method.
Clearance wall is formed on each side wall of grid, is by heavy including nitride, oxynitride or combination thereof
What product and etching were formed.Clearance wall structure can have different thickness, but be measured since bottom surface, the thickness of clearance wall structure
Degree is usually 10 to 30nm.It should be noted that clearance wall is optional rather than required, it is mainly used for being lost subsequently
The side wall of protection gate structure is injury-free when quarter or ion implanting.
The gate structure is removed, to form opening, and then forms metal gate structure, specifically：It goes in this step
After the NMOS gate structure and PMOS gate structures, opening is formed in NMOS and PMOS area respectively.
The NMOS gate structure and PMOS gate structures are removed by dry etching or wet etching in this step,
Such as N can be selected in the present invention2In conduct etching atmosphere, other a small amount of gas such as CF can also be added in simultaneously4、
CO2、O2, the etching pressure can be 50-200mTorr, power 200-600W, and the etching period is 5- in the present invention
80s。
Expose the high k dielectric layer, and work(is formed in the high K Semiconductor substrates after the gate structure is removed
Function material layer
Workfunction material be p-type or N-type workfunction material, material can with selected as but be not limited to TixN1-x,
TaC, MoN, TaN either combination thereof or other suitable film layers.
In the present embodiment, workfunction material can select TiN.The suitable technique such as CVD, ALD or PVD may be used
Form workfunction material.
The step of forming diffusion impervious layer (not shown) is being deposited in the N work-function layers, the diffusion impervious layer includes
TaN, TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above.The nonrestrictive reality of deposit diffusion barriers method
Example include chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD),
Fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).
Then, metal gate electrode layer is formed on the semiconductor substrate.
In one example, the method for forming the metal gate electrode layer includes：First, it sinks on the semiconductor substrate
Product forms metal gate electrode layer；Then, the metal gate electrode layer is planarized to ultimately form metal gate structure.
The material of metal gate electrode layer with selected as but can be not limited to Al, W or other suitable film layers.It may be used
CVD, ALD or PVD etc. suitable technique forms metal gate electrode layer.
In one example, metal W is formed as metal gate electrode layer using chemical vapor deposition method.Wherein, CVD works
Skill uses WF6As reaction gas, WF is decomposed6Deposition forms metal W.
So far the introduction of the key step of the manufacturing method of the semiconductor devices to the present invention is completed, for complete device
The making of part also needs other previous steps, intermediate steps or subsequent step, and this is no longer going to repeat them.
, the offset oxide skin(coating) too short to the cleaning process stand-by period is ashed in order to solve offset side wall in current technique
Thickness it is small, the problems such as device performance is made to be affected, the present invention provides a kind of semiconductor devices and its manufacturing method, in institute
State in the preparation process of semiconductor devices increases by a re-oxidation step after the offset side wall ashing, cleaning, so that described
The thickness of the offset oxide skin(coating) in Semiconductor substrate increases, and the oxidation step can not only be situated between to avoid to high-K gate
The influence of electric layer.
The technique can be very good with current technique it is compatible, it is simple for process, easy to implement, and when can avoid waiting for
Between when being less than 50 minutes device offset influence, lacked caused by being repaired in gate etch processes by increasing the oxidation step
It falls into, further improves the performance and yield of the semiconductor devices.
Embodiment two
The present invention also provides a kind of semiconductor devices obtained using preceding method manufacture, which includes：
Semiconductor substrate；
Gate structure, in the Semiconductor substrate；
Offset side wall, on the side wall of the gate structure；
Deviate oxide skin(coating), in the Semiconductor substrate on the outside of the offset side wall, the offset oxide skin(coating)
Thickness at 25 angstroms or more.
The Semiconductor substrate 201 can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) etc. is laminated on insulator.
In addition, active area can be defined in Semiconductor substrate 201.Others can also be included on the active region to be had
Source device, for convenience, there is no indicate in shown figure.
Then shallow trench isolation is formed over the substrate, and the Semiconductor substrate is divided into active area and isolation
Area.
The Semiconductor substrate can be divided into NMOS area and PMOS area by the shallow trench isolation in the present invention.
NMOS gate is formed in the NMOS area, PMOS grids are formed in the PMOS area.
Specifically, it has been sequentially depositing oxide skin(coating), high k dielectric layer and gate material layers on the semiconductor substrate.
Wherein, the oxide skin(coating) is chosen as silica, forming method can be deposition silicon dioxide material layer or
Semiconductor substrate described in person's high-temperature oxydation is formed.
The gate material layers may include polysilicon layer, metal layer, conductive metal nitride layer, conductive metal oxidation
It is one or more in nitride layer and metal silicide layer.
Optionally, the gate material layers select polysilicon in this embodiment.
Wherein, the k values (dielectric constant) of the high k dielectric layer are usually more than 3.9, constituent material include hafnium oxide,
Hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium,
Strontium oxide strontia titanium, aluminium oxide etc., preferably hafnium oxide, zirconium oxide or aluminium oxide.
Chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) or physics gas may be used in the high k dielectric layer
The suitable technique such as phase sedimentation (PVD) is formed.
Offset side wall 2031 is formed in the NMOS gate and PMOS grids both sides.
The offset side wall 2031 e.g. silicon nitride, the insulating materials such as silica or silicon oxynitride.With device ruler
Very little further becomes smaller, and the channel length of device is less and less, and the particle injection depth of source-drain electrode is also less and less, offset side wall
Effect be channel length to improve the transistor formed, reduce short-channel effect and caused by short-channel effect it is hot
Carrier effect.
Increase in the preparation process of the semiconductor devices to the offset side wall and the Semiconductor substrate exposed
Oxidation step is carried out, to increase the thickness of the offset oxide skin(coating) of the semiconductor substrate surface.
Optionally, the temperature of the oxidation step is 650-750 DEG C, such as the temperature of the oxidation step is 700 DEG C.
Optionally, the time of the oxidation step is 1.5-2.5 minutes, such as the time of the oxidation step is 2 minutes.
Optionally, the increased thickness of oxide skin(coating) is deviated described in the oxidation step at 5 angstroms or more.
Optionally, after the oxidation step it is described offset oxide skin(coating) overall thickness at 25 angstroms or more.
Clearance wall is formed on the offset side wall of the NMOS gate structure and the PMOS gate structures.
The clearance wall can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.As this reality
An optimal enforcement mode of example is applied, the clearance wall is silica, silicon nitride collectively constitutes, and concrete technology is：In semiconductor
The first silicon oxide layer, the first silicon nitride layer and the second silicon oxide layer are formed on substrate, gap is then formed using engraving method
Wall.
The semiconductor devices forms workfunction material after dummy gate is removed in the high K Semiconductor substrates
Workfunction material be p-type or N-type workfunction material, material can with selected as but be not limited to TixN1-x,
TaC, MoN, TaN either combination thereof or other suitable film layers.
In the present embodiment, workfunction material can select TiN.The suitable technique such as CVD, ALD or PVD may be used
Form workfunction material.
Deposition is formed with diffusion impervious layer (not shown) in the N work-function layers, the diffusion impervious layer include TaN,
TiN, TaC, TaSiN, WN, TiAl, TiAlN or combinations of the above.The deposit diffusion barriers method non-limiting examples packet
Chemical vapour deposition technique (CVD) is included, such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast heat
Chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD).
Metal gate electrode layer is formed on the diffusion impervious layer.
The material of metal gate electrode layer with selected as but can be not limited to Al, W or other suitable film layers.It may be used
CVD, ALD or PVD etc. suitable technique forms metal gate electrode layer.
In one example, metal W is formed as metal gate electrode layer using chemical vapor deposition method.Wherein, CVD works
Skill uses WF6As reaction gas, WF is decomposed6Deposition forms metal W.
Since the semiconductor devices of the present invention is formed using aforementioned manufacturing method, also have the advantages that identical.
Embodiment three
The present invention also provides a kind of electronic devices, including the semiconductor devices described in embodiment two, the semiconductor device
Part is prepared according to one the method for embodiment.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus with better performance.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
Semiconductor substrate；Gate structure, in the Semiconductor substrate；Offset side wall, on the side wall of the gate structure；Partially
Oxide skin(coating) is moved, in the Semiconductor substrate on the outside of the offset side wall, the thickness of the offset oxide skin(coating) is 25
Angstrom or more.
The electronic device of the present invention includes aforementioned semiconductor devices, therefore also has identical with the semiconductor devices
Advantage.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, is formed with gate structure and the covering gate structure and described on the semiconductor substrate
The offset side wall material layer of Semiconductor substrate；
The offset side wall material layer is etched, to form offset side wall on the side wall of the gate structure and expose institute
State Semiconductor substrate；
The offset side wall and the Semiconductor substrate exposed are ashed, to be formed partially in the semiconductor substrate surface
Move oxide skin(coating)；
Perform cleaning step；
Oxidation step is performed, to increase the thickness of the offset oxide skin(coating) of the semiconductor substrate surface.
2. manufacturing method according to claim 1, which is characterized in that the oxidation step uses stove internal oxidation process.
3. manufacturing method according to claim 1, which is characterized in that the temperature of the oxidation step is 650-750 DEG C.
4. manufacturing method according to claim 1, which is characterized in that the time of the oxidation step is 1.5-2.5 minutes.
5. manufacturing method according to claim 1, which is characterized in that deviate oxide skin(coating) described in the oxidation step
Increased thickness is at 5 angstroms or more.
6. manufacturing method according to claim 1, which is characterized in that the offset oxide after the oxidation step
The overall thickness of layer is at 25 angstroms or more.
7. manufacturing method according to claim 1, which is characterized in that the method is still further comprised to the offset oxygen
The step of thickness of compound layer measures.
8. manufacturing method according to claim 1, which is characterized in that the gate structure includes the interface sequentially formed
Layer, high k dielectric layer and dummy gate, the method still further comprise the removal dummy gate, then form metal gates
The step of.
9. manufacturing method according to claim 1, which is characterized in that the Semiconductor substrate includes NMOS area and PMOS
Region is formed with NMOS gate in the NMOS area, and PMOS grids are formed in the PMOS area.
10. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes：
Semiconductor substrate；
Gate structure, in the Semiconductor substrate；
Offset side wall, on the side wall of the gate structure；
Oxide skin(coating) is deviated, in the Semiconductor substrate on the outside of the offset side wall, the thickness of the offset oxide skin(coating)
Degree is at 25 angstroms or more.
11. semiconductor devices according to claim 10, which is characterized in that the Semiconductor substrate include NMOS area and
PMOS area is formed with NMOS gate in the NMOS area, and PMOS grids are formed in the PMOS area.
12. a kind of electronic device, which is characterized in that including claim 10 to 11 any one of them semiconductor devices.
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