CN104752316B - A kind of method for making semiconductor devices - Google Patents
A kind of method for making semiconductor devices Download PDFInfo
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- CN104752316B CN104752316B CN201310728082.7A CN201310728082A CN104752316B CN 104752316 B CN104752316 B CN 104752316B CN 201310728082 A CN201310728082 A CN 201310728082A CN 104752316 B CN104752316 B CN 104752316B
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- 238000000034 method Methods 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 239000010410 layer Substances 0.000 claims description 304
- 238000000576 coating method Methods 0.000 claims description 77
- 239000011248 coating agent Substances 0.000 claims description 76
- 239000000758 substrate Substances 0.000 claims description 45
- 230000004888 barrier function Effects 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 17
- 238000012545 processing Methods 0.000 claims description 16
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910020781 SixOy Inorganic materials 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- 230000035484 reaction time Effects 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 239000011247 coating layer Substances 0.000 claims 1
- 239000008246 gaseous mixture Substances 0.000 claims 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 239000004411 aluminium Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000011049 filling Methods 0.000 abstract description 4
- 239000012528 membrane Substances 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 description 17
- 239000010408 film Substances 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000000059 patterning Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 239000006117 anti-reflective coating Substances 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910017121 AlSiO Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- -1 LaSiO Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 229910010252 TiO3 Inorganic materials 0.000 description 2
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000003851 corona treatment Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of method for making semiconductor devices, the method according to the invention proposes a kind of manufacture craft of new metal gate electrode thin membrane stack, to prevent the diffusion of the aluminium in PMOS area, the diffusion of aluminium is utilized in NMOS area, it is final to make the semiconductor device structure to be formed that there is good gap filling edge and relatively low metal gates resistance compared with the semiconductor device structure that traditional handicraft is formed, to improve the overall performance of semiconductor devices, the yields of semiconductor is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to one kind metal gates (high-K＆gate after rear high K/
Last the method that new metal gate electrode thin film stacked structure) is formed in technique.
Background technology
Main devices in integrated circuit (IC) especially super large-scale integration are metal oxide semiconductcor field effects
Transistor (MOS) is answered, with the maturation of semiconductor integrated circuit industrial technology increasingly, the rapid hair of ultra-large integrated circuit
Exhibition, has a higher performance and the bigger component density of more powerful integrated circuit requirement, and between all parts, element or
Size, size and the space of each element itself are also required to further reduce.For the CMOS with more advanced technology node
For, rear high K/ metal gates (high-k and metal gate last) technology has been widely used for cmos device
In, to avoid damage of the high-temperature processing technology to device.Simultaneously, it is necessary to reduce the equivalent oxide of cmos device gate dielectric
Thickness (EOT), such as it is contracted to about 1.1nm.In rear high K (high-k last, HK last process) technology, in order to
Up to less EOT thickness, hot gate oxide layers are replaced using chemical oxide boundary layer (chemical oxide IL)
(thermal gate oxide)。
After current rear high K/ in metal gates (high-K＆gate last) technology, including remove virtual polysilicon gate
To form gate trench, deposition forms interface oxide layer and high k dielectric layer in gate trench, then exists for pole and grid oxic horizon
Deposition forms workfunction layers and metal electrode layer on high k dielectric layer in gate trench, then using cmp
(CMP) unnecessary workfunction layers and metal electrode layer are removed, to form metal gates.
As shown in figs. 1A-1 c, it is to be shown according to the cross section of the semiconductor devices of MG structures after HK/ after existing fabrication techniques
It is intended to, shown in 1A, the dummy gate in NMOS area and PMOS area in Semiconductor substrate 100 is removed using etching technics
Retain the clearance wall positioned at dummy gate structure both sides with gate dielectric, to form metal gates groove, in metal gates ditch
It is sequentially depositing to form boundary layer 101, high k dielectric layer 102, coating 103, barrier layer 104 and PMOS workfunction layers in groove
105。
As shown in Figure 1B, the bottom antireflective coating and photoresist layer 106 of patterning are formed on a semiconductor substrate, with dew
Go out NMOS area covering PMOS area；Removed according to the bottom antireflective coating of patterning and photoresist layer 106 in NMOS area
PMOS workfunction layers to expose barrier layer 104, then remove and pattern the bottom antireflective coating and photoresist
Layer 106.
As shown in Figure 1 C, deposition forms NMOS workfunction layers 108 and metal electrode layer on a semiconductor substrate 100
107.Then, use chemical mechanical milling tech to get rid of unnecessary metal level to expose interlayer dielectric layer, eventually form metal
Grid.
However, current rear high k dielectric layer/rear metal gates are being formed compared with preceding high k dielectric layer/rear metal gates
Metal gates groove in deposit high k dielectric layer and coating, this will make what gate stack filling became to be not easily accomplished, especially right
For relatively advanced technology node.On the other hand, served as a contrast in double work function metal gate process in order to realize in semiconductor
PMOS workfunction layers and NMOS workfunction layers are formed in bottom respectively so that form film stack lamination and fill process becomes
Unusual complexity.Meanwhile in existing rear high k dielectric layer/rear metal gate process, the material of NMOS workfunction layers
Usually TiAl or aluminium, so it is easy to cause generation aluminium atom diffusion phenomena, the diffusion of more aluminium atom will influence device
Voltage (increase PMOS device voltage and reduce the voltage of nmos device) and influence device performance and reliability.
Therefore, it is necessary to a kind of preparation method of new semiconductor devices, to solve the problems of the prior art.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of method for making semiconductor devices, wraps
Include：The Semiconductor substrate with first area and second area is provided, the first area includes dummy gate, secondth area
Domain includes dummy gate；The dummy gate in the dummy gate and the second area in the first area is removed, with institute
State and first groove is formed in first area, second groove is formed in the second area；In the first groove and described
It is sequentially depositing to form high k dielectric layer, the first coating and p-type workfunction layers on the bottom of two grooves and side wall；Using light
The p-type workfunction layers and first coating in the carving technology removal second groove expose the high k dielectric
Layer, to form the 3rd groove；Second is sequentially formed on the bottom and side wall of the first groove and the 3rd groove to cover
Cap rock, barrier layer, N-type workfunction layers and metal gate layers.
The present invention proposes another method for making semiconductor devices, including：Offer has first area and the secondth area
The Semiconductor substrate in domain, the first area include dummy gate, and the second area includes dummy gate；Remove described first
The dummy gate in dummy gate and the second area in region, to form first groove in the first area,
Second groove is formed in the second area；It is sequentially depositing on the bottom and side wall of the first groove and the second groove
Form high k dielectric layer, the first coating, barrier layer and p-type workfunction layers；The second groove is removed using photoetching process
In the p-type workfunction layers, the barrier layer and first coating expose the high k dielectric layer, to form
Three grooves；The second coating is formed on the bottom and side wall of the first groove and the 3rd groove；To described second
Coating carries out a processing step, to prevent the metal ion in the N-type workfunction layers and metal gate layers formed afterwards
It is diffused into the Rotating fields under it；N-type workfunction layers and metal are sequentially formed on second coating after treatment
Grid layer.
Preferably, p-type workfunction layers in second area and described are removed using wet etching or dry etching
First coating, the etching technics have the p-type workfunction layers and first coating to the high k dielectric layer
High etching selectivity.
Preferably, using the p-type workfunction layers in wet etching or dry etching removal second area, the resistance
Barrier and first coating, the etching technics have the p-type workfunction layers, the barrier layer and described first
High etching selectivity of the coating to the high k dielectric layer.
Preferably, the material of second coating is titanium nitride, titanium silicon nitride, and the material on the barrier layer is nitridation
Tantalum, tantalum or calorize tantalum, the thickness on the barrier layer is 5 angstroms to 20 angstroms.
Preferably, the processing step is performed using annealing process, the annealing process be peak value annealing, Millisecond annealing or
Person's short annealing, the temperature for performing the annealing process is 400 DEG C to 600 DEG C, and the time for performing the annealing process is 10 seconds
To 60 seconds, the annealing process is performed under conditions of the mixed gas of oxygen, nitrogen, ammonia or oxygen and nitrogen is passed through.
Preferably, Semiconductor substrate exposure is performed into the processing step in atmosphere.
Preferably, the using plasma technique execution processing step, the reaction time of the plasma process are
10 seconds to 60 seconds, the plasma is performed under conditions of the mixed gas of oxygen, nitrogen, argon gas or argon gas and nitrogen is passed through
Body technology, the power for performing the plasma process are 100W to 500W.
Preferably, the processing step is that titanium layer or silicon layer are formed on second coating, then performs annealing
Technique, to form Ti on second coatingxOyLayer or SixOyThe thickness of layer, the titanium layer or the silicon layer is 5
Angstrom to 15 angstroms.
Preferably, boundary layer, the material of the boundary layer are also formed between the Semiconductor substrate and the high k dielectric layer
Expect for thermal oxide layer, nitrogen oxide layer or chemical oxide layer, the thickness range of the boundary layer is 5 angstroms to 10 angstroms.
Preferably, the first area is PMOS area, and the second area is NMOS area.
Preferably, the high k dielectric layer, first coating, described are formed using CVD, ALD or PVD
Two coatings, the barrier layer, the p-type workfunction layers, the N-type workfunction layers, the metal electrode layer.
Preferably, the thickness range of first coating and second coating is 5 angstroms to 20 angstroms, the p-type work(
The thickness range of function metal is 10 angstroms to 580 angstroms, the thickness range of the N-type workfunction layers is 10 angstroms to 80 angstroms.
To sum up shown, the method according to the invention proposes a kind of manufacture craft of new metal gate electrode thin membrane stack, with resistance
The only diffusion of the aluminium in PMOS area, in NMOS area utilize aluminium diffusion, finally make the semiconductor device structure to be formed with
The semiconductor device structure that traditional handicraft is formed is compared with good gap filling edge and relatively low metal gates resistance, to carry
The overall performance of high semiconductor devices, improve the yields of semiconductor.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Figure 1A -1C are to make the cross-section structure with the semiconductor devices of MG structures after rear HK/ according to prior art to illustrate
Figure；
Fig. 2A -2C are to make the semiconductor devices correlation with MG structures after rear HK/ according to one embodiment of the present invention
The cross-sectional view for the device that step is obtained；
Fig. 3 is to make the technique stream with the semiconductor devices of MG structures after rear HK/ according to one embodiment of the present invention
Cheng Tu；
Fig. 4 A-4D are to make the semiconductor devices phase with MG structures after rear HK/ according to another embodiment of the invention
Close the cross-sectional view for the device that step is obtained；
Fig. 5 is to make the technique with the semiconductor devices of MG structures after rear HK/ according to another embodiment of the invention
Flow chart.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it will be apparent to one skilled in the art that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, in the method for the explanation present invention.
Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.The preferable reality of the present invention
Example is applied to be described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
The preparation method of semiconductor devices of the present invention is described in detail below in conjunction with Fig. 2A -2C.Such as Fig. 2A
It is shown, there is provided Semiconductor substrate 200, semiconductor Semiconductor substrate 200 may include any semi-conducting material, and this semi-conducting material can
Including but not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or II-VI race
Compound semiconductor.And alternatively, Semiconductor substrate 300 can include epitaxial layer.Semiconductor substrate 300 can also include organic
Semiconductor or the layered semiconductor such as SiGe (SGOI) on Si/SiGe, silicon-on-insulator (SOI) or insulator.
Semiconductor substrate 200 includes various isolation structures, and these isolated parts can include different structure, and by difference
Treatment technology formed.Such as isolated part can include shallow trench isolated part (STI).Semiconductor substrate 200 also includes
Trap.
Semiconductor substrate 200 includes NMOS area and PMOS area, and NMOS area has the raceway groove formed in Uniform Doped
Dummy gate structure in area, the dummy gate structure include grid oxic horizon and dummy gate, and gate oxide level
The grid gap wall formed with dummy gate both sides, PMOS area have the dummy gate formed on the channel region of Uniform Doped
Structure, the dummy gate structure include grid oxic horizon and dummy gate, and gate oxide level and dummy gate both sides
The grid gap wall of formation, the material of dummy gate can be that polysilicon is either silicon nitride or agraphitic carbon, wherein, virtually
The material of grid preferably undoped with polysilicon, grid gap wall can be silica, silicon nitride, it is a kind of in silicon oxynitride or
They combine composition.As an optimal enforcement mode of the present embodiment, the clearance wall is silica, common group of silicon nitride
Into.Semiconductor substrate 200 also includes the source-drain area positioned at NMOS dummy gates and PMOS dummy gates both sides.
Interlayer dielectric layer is formed above Semiconductor substrate 200 and dummy gate.Implement cmp (CMP) technique
Remove unnecessary interlayer dielectric layer so that expose the dummy gate layer of dummy gate.Other mode forming layers can also be used
Between dielectric layer to expose the dummy gate layer of dummy gate.
Implement etching technics to remove dummy gate in NMOS area and PMOS area and grid oxic horizon retains and is located at
Dummy gate and the grid gap wall of grid oxic horizon both sides, to form metal gates ditch in NMOS area and PMOS area
Groove.Etching technics can include the combination of dry etching, wet etching or dry etching and wet etching.Removing virtual grid
After pole is to expose the surface of Semiconductor substrate, can also use such as dilution hydrofluoric acid or other be adapted to techniques to remove grid
Pole oxide layer, metal gates groove is formed to be completely exposed the surface of Semiconductor substrate.
On interlayer dielectric layer, in grid gap wall, in the bottom of metal gates groove and aspect deposition form boundary layer
(IL) 201 and high K (HK) dielectric layer 202.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or its
The film layer that he is adapted to.The suitable technique such as CVD, ALD or PVD can be used to form boundary layer.The thickness range of boundary layer
For 5 angstroms to 10 angstroms.The material of high-k dielectrics can select be but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON,
HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(BST)、Al2O3、Si3N4, nitrogen oxidation
Thing or other suitable materials.The suitable technique such as CVD, ALD or PVD can be used to form high k dielectric layer.High k dielectric
The thickness range of layer is 10 angstroms to 30 angstroms.
Coating 203 is formed on high k dielectric layer 202, the material of coating 203 can be La2O3、AL2O3、Ga2O3、
In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable film layers.CVD, ALD can be used
Or the technique formation coating that PVD etc. is suitable.The thickness range of coating is 5 angstroms to 20 angstroms.P is formed on coating 203
Type workfunction layers 204, to form groove 205A and groove 205B, p-type workfunction layers are that PMOS workfunction metals can
Adjust layer, the material of p-type workfunction layers (PWF) can select to be but be not limited to TixN1-x, TaC, MoN, TaN or other are suitable
The film layer of conjunction.The suitable technique such as CVD, ALD or PVD can be used to form p-type workfunction layers.P-type work function gold
The thickness range for belonging to layer is 10 angstroms to 580 angstroms.
As shown in Figure 2 B, formed in the bottom of the groove 205A in PMOS area and side wall bottom antireflective coating and
The photoresist layer 206 of patterning, the photoresist layer 206 of patterning expose NMOS area covering PMOS area.By bottom anti-reflective
Reduce the reflection of bottom light in bottom of the coating coated in photoresist 206.
PMOS workfunction layers 204 and the covering removed in NMOS area is etched according to the photoresist layer 206 of patterning
Layer 203, to expose high k dielectric layer 202.The PMOS workfunction layers 204 in NMOS area and coating 203 are removed to expose
The etching technics of high k dielectric layer 202 can use wet etching or dry etching, and the etching technics has p-type work function
Metal level 204 and coating 203 are to the high etching selection ratio less than high k dielectric layer 202.
In the specific embodiment of the present invention, using the photoresist layer being patterned immediately as mask, using dry etching
Technique, in the case where being passed through the etching condition of boron chloride and chlorine, p-type workfunction layers 204 and coating 203 are performed etching,
It can be 5~20 millitorrs (mTorr) to react room pressure；Power：300-800W；Time：5-15s；The boron chloride and chlorine
Range of flow can be 0~150 cc/min (sccm) and 50~200 cc/mins (sccm).Need what is illustrated
Above-mentioned engraving method is merely exemplary that limitation and this method, those skilled in the art can also not select other normal
Method.
Then, the photoresist layer 206 of bottom antireflective coating and patterning is removed, to form groove in NMOS area
207, expose the high k dielectric layer 202 in NMOS area, expose the p-type workfunction layers 205 in PMOS area.
As shown in Figure 2 C, the bottom of the groove 207 in the groove 205A and NMOS area in PMOS area and side wall
Coating 208 is formed, the material of coating 208 can be La2O3、AL2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、
TaC、MoN、WN、TixN1-xOr other suitable film layers.The technique that CVD, ALD or PVD etc. can be used suitable is formed
Coating.The thickness range of coating is 5 angstroms to 20 angstroms.Deposition forms barrier layer 209, the material on barrier layer on coating 208
Material can select to be but be not limited to TiN, TiSiN or other suitable film layers.CVD, ALD or PVD etc. can be used suitable
The technique of conjunction forms barrier layer.The thickness range on barrier layer is 5 angstroms to 20 angstroms.
It is sequentially depositing to form N-type workfunction layers 210 and gold on barrier layer 209 in NMOS area and PMOS area
Belong to electrode layer 211, NMOS workfunction layers 210 and metal electrode layer 211 cover Semiconductor substrate.N-type workfunction layers
(NWF) be NMOS workfunction metal tunable layers, the material of N-type workfunction layers can select be but be not limited to TaC, Ti, Al,
TixAl1-xOr other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form N-type work function gold
Belong to layer.The thickness range of N-type workfunction layers is 10 angstroms to 80 angstroms.The material of metal electrode layer can select to be but be not limited to
Al, W or other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form metal electrode layer.
There is no the formation in cavity during forming metal electrode layer using above-mentioned technique.In Semiconductor substrate 200 NMOS area and
Metal gate structure lamination is formed in PMOS area.
Then, cmp (CMP) technique is performed to planarize nmos device and PMOS device, with NMOS area
Middle formation metal gates, metal gates are formed in PMOS area.CMP can have metal electrode layer 211 to be situated between interlayer
The high etching selection ratio of electric layer, unnecessary metal electrode layer, workfunction layers, barrier layer, coating are removed using CMP
With high k dielectric layer to expose interlayer dielectric layer, and make the gold in the top of the metal gate layers in NMOS area, PMOS area
Belong to and being flushed at the top of top, grid gap wall and the interlayer dielectric layer of grid layer.CMP is metal gate stack and interlayer
Dielectric layer provides the surface of substantially flat.
Reference picture 3, it illustrated therein is and the semiconductor with MG structures after rear HK/ is made according to one embodiment of the present invention
The process chart of device, for schematically illustrating the flow of whole manufacturing process.
In step 301, there is provided semi-conductive substrate, on a semiconductor substrate formed with interlayer dielectric layer (ILD0),
Dummy gate structure in dummy gate structure and PMOS area in NMOS area.Remove the dummy gate structure in NMOS area
With the dummy gate structure in PMOS area, to form metal gates groove；
In step 302, be sequentially depositing in the metal gates groove in NMOS area and PMOS area to be formed boundary layer,
High k dielectric layer, the first coating and p-type workfunction layers；
In step 303, the p-type workfunction layers and the first coating in NMOS area are removed using photoetching process；
In step 304, sequentially form on a semiconductor substrate the second coating, barrier layer, N-type workfunction layers and
Metal gate layer, perform CMP.
Fig. 4 A-4D are to make the semiconductor devices phase with MG structures after rear HK/ according to another embodiment of the invention
Close the cross-sectional view for the device that step is obtained；Below in conjunction with Fig. 4 A-4D to semiconductor devices of the present invention
Preparation method is described in detail.As shown in Figure 4 A, there is provided Semiconductor substrate 400, Semiconductor substrate 400 may include any partly to lead
Body material, this semi-conducting material may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and
Other III-V or group Ⅱ-Ⅵ compound semiconductor.And alternatively, Semiconductor substrate 400 can include epitaxial layer.Semiconductor
Substrate 400 can also include organic semiconductor or such as SiGe on Si/SiGe, silicon-on-insulator (SOI) or insulator
(SGOI) layered semiconductor.
Semiconductor substrate 400 includes various isolation structures, and these isolated parts can include different structure, and by difference
Treatment technology formed.Such as isolated part can include shallow trench isolated part (STI).Semiconductor substrate 400 also includes
Trap.
Semiconductor substrate 400 includes NMOS area and PMOS area, and NMOS area has the raceway groove formed in Uniform Doped
Dummy gate structure in area, the dummy gate structure include grid oxic horizon and dummy gate, and gate oxide level
The grid gap wall formed with dummy gate both sides, PMOS area have the dummy gate formed on the channel region of Uniform Doped
Structure, the dummy gate structure include grid oxic horizon and dummy gate, and gate oxide level and dummy gate both sides
The grid gap wall of formation, the material of dummy gate can be that polysilicon is either silicon nitride or agraphitic carbon, wherein, virtually
The material of grid preferably undoped with polysilicon, grid gap wall can be silica, silicon nitride, it is a kind of in silicon oxynitride or
They combine composition.As an optimal enforcement mode of the present embodiment, the clearance wall is silica, common group of silicon nitride
Into.Semiconductor substrate 400 also includes the source-drain area positioned at NMOS dummy gates and PMOS dummy gates both sides.
Interlayer dielectric layer is formed above Semiconductor substrate 400 and dummy gate.Implement cmp (CMP) technique
Remove unnecessary interlayer dielectric layer so that expose the dummy gate layer of dummy gate.Other mode forming layers can also be used
Between dielectric layer to expose the dummy gate layer of dummy gate.
Implement etching technics to remove dummy gate in NMOS area and PMOS area and grid oxic horizon retains and is located at
Dummy gate and the grid gap wall of grid oxic horizon both sides, to form metal gates ditch in NMOS area and PMOS area
Groove.Etching technics can include the combination of dry etching, wet etching or dry etching and wet etching.Removing virtual grid
After pole is to expose the surface of Semiconductor substrate, can also use such as dilution hydrofluoric acid or other be adapted to techniques to remove grid
Pole oxide layer, metal gates groove is formed to be completely exposed the surface of Semiconductor substrate.
On interlayer dielectric layer, in grid gap wall, in the bottom of metal gates groove and aspect deposition form boundary layer
(IL) 401 and high K (HK) dielectric layer 402.IL layers can be thermal oxide layer, nitrogen oxide layer, chemical oxide layer or its
The film layer that he is adapted to.The suitable technique such as CVD, ALD or PVD can be used to form boundary layer.The thickness range of boundary layer
For 5 angstroms to 10 angstroms.The material of high-k dielectrics can select be but be not limited to LaO, BaZrO, AlO, HfZrO, HfZrON,
HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(BST)、Al2O3、Si3N4, nitrogen oxidation
Thing or other suitable materials.The suitable technique such as CVD, ALD or PVD can be used to form high k dielectric layer.High k dielectric
The thickness range of layer is 10 angstroms to 30 angstroms.
Deposition forms coating 403 on high k dielectric layer 402, and the material of coating 403 can be La2O3、AL2O3、
Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-xOr other suitable film layers.It can use
CVD, ALD or PVD etc. suitable technique forms coating.The thickness range of coating is 5 angstroms to 20 angstroms.In coating 403
Upper formation barrier layer 404, the material on barrier layer can select to be but be not limited to TiN, TiSiN or other suitable film layers.
The suitable technique such as CVD, ALD or PVD can be used to form barrier layer.The thickness range on barrier layer is 5 angstroms to 20 angstroms.Hindering
P-type workfunction layers 405 are formed in barrier 404, to form groove 406A and groove 406B, p-type workfunction layers are
PMOS workfunction metal tunable layers, the material of p-type workfunction layers (PWF) can select to be but be not limited to TixN1-x,TaC,
MoN, TaN or other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form p-type work function gold
Belong to layer.The thickness range of p-type workfunction layers is 10 angstroms to 580 angstroms.
As shown in Figure 4 B, formed in the bottom of the groove 406A in PMOS area and side wall bottom antireflective coating and
The photoresist layer 407 of patterning, the photoresist layer 407 of patterning expose NMOS area covering PMOS area.By bottom anti-reflective
Reduce the reflection of bottom light in bottom of the coating coated in photoresist 407.
The PMOS workfunction layers 405 removed in NMOS area, barrier layer are etched according to the photoresist layer 407 of patterning
404 and coating 403, to expose high k dielectric layer 402.PMOS workfunction layers 405, barrier layer in removal NMOS area
404 and coating 403 can use wet etching or dry etching, the quarter to expose the etching technics of high k dielectric layer 402
Etching technique has p-type workfunction layers 405, barrier layer 404 and coating 403 to the high etching choosing less than high k dielectric layer 402
Select ratio.
In the specific embodiment of the present invention, using the photoresist layer being patterned immediately as mask, using dry etching
Technique, in the case where being passed through the etching condition of boron chloride and chlorine, to p-type workfunction layers 405, barrier layer 404 and coating 403
Perform etching, reaction room pressure can be 5~20 millitorrs (mTorr)；Power：300-800W；Time：5-15s；The boron chloride
Range of flow with chlorine can be 0~150 cc/min (sccm) and 50~200 cc/mins (sccm).Need
To illustrate that what above-mentioned engraving method was merely exemplary, limitation and this method, those skilled in the art can also not select
With other conventional methods.
Then, the photoresist layer 407 of bottom antireflective coating and patterning is removed, to form groove in NMOS area
408, expose the high k dielectric layer 402 in NMOS area, expose the p-type workfunction layers 405 in PMOS area.
As shown in Figure 4 C, the bottom of the groove 408 in the groove 406A and NMOS area in PMOS area and side wall
Coating 409 is formed, the material of coating 409 can be La2O3、AL2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、
TaC、MoN、WN、TixN1-xOr other suitable film layers.The technique that CVD, ALD or PVD etc. can be used suitable is formed
Coating.The thickness range of coating is 5 angstroms to 20 angstroms.
In order to prevent the diffusion of the aluminium atom in PMOS area, to Semiconductor substrate after the coating 409 is formed
400 are handled.Specifically, a processing step is carried out to the coating 409, to prevent the N-type work function gold formed afterwards
Metal ion in category layer and metal gate layers is diffused into the Rotating fields under it.
Exemplarily, the Semiconductor substrate can be exposed in atmosphere, to perform the processing step.
Exemplarily, the processing step is performed using annealing process, the annealing process can be peak value annealing, millisecond
The suitable annealing process such as annealing or short annealing.In the mixed gas with oxygen, nitrogen, ammonia or oxygen and nitrogen
Environment in perform the annealing process, perform the annealing process temperature range be 400 DEG C to 600 DEG C, the lehr attendant
The annealing time of skill is 10 seconds to 60 seconds.
Exemplarily, using plasma processing performs the processing step, and nitrogen, oxygen, argon are passed through in reative cell
The mixed gas of gas or nitrogen and argon gas performs the plasma treatment, and the reaction time of the corona treatment is 10 seconds
To 60 seconds, the power of the corona treatment was 100W to 500W.Wherein, in the plasma treatment process, in order to keep away
Exempting from the damage to device needs to implement the plasma treatment under conditions of low-power.
Exemplarily, deposition forms in titanium layer or silicon layer, then reative cell and is passed through oxygen on the coating 409, instead
The temperature for answering interior will deposit the titanium layer or silicon layer formed to form Ti to aoxidize under conditions of being 400 DEG C to 600 DEG CxOy
Layer or SixOyLayer, to prevent the diffusion of aluminium atom.Wherein, the thickness of titanium layer or silicon layer is 5 angstroms to 15 angstroms, can be used
Either suitable PVD etc. technique forms titanium layer or silicon layer by CVD, ALD, the thickness of the titanium layer or silicon layer it is thin as far as possible with
Reduce the influence to device voltage.
Exemplarily, the processing step can be performed as one group of handling process with reference to above-mentioned all techniques.
As shown in Figure 4 D, it is sequentially depositing to form N-type work function gold on the coating 409 in NMOS area and PMOS area
Belong to layer 410 and metal electrode layer 411, NMOS workfunction layers 410 and metal electrode layer 411 cover Semiconductor substrate.N-type work(
Function metal (NWF) is NMOS workfunction metal tunable layers, and the material of N-type workfunction layers can select to be but be not limited to
TaC、Ti、Al、TixAl1-xOr other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form N
Type workfunction layers.The thickness range of N-type workfunction layers is 10 angstroms to 80 angstroms.The material of metal electrode layer can select
For but be not limited to Al, W or other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form metal
Electrode layer.There is no the formation in cavity during metal electrode layer is formed using above-mentioned technique.In Semiconductor substrate 400
Metal gate structure lamination is formed in NMOS area and PMOS area.
Then, cmp (CMP) technique is performed to planarize nmos device and PMOS device, with NMOS area
Middle formation metal gates, metal gates are formed in PMOS area.CMP can have metal electrode layer 411 to be situated between interlayer
The high etching selection ratio of electric layer, unnecessary metal electrode layer, workfunction layers, barrier layer, coating are removed using CMP
With high k dielectric layer to expose interlayer dielectric layer, and make the gold in the top of the metal gate layers in NMOS area, PMOS area
Belong to and being flushed at the top of top, grid gap wall and the interlayer dielectric layer of grid layer.CMP is metal gate stack and interlayer
Dielectric layer provides the surface of substantially flat.
Reference picture 5, it illustrated therein is to be made according to another of the invention embodiment and partly led with MG structures after rear HK/
The process chart of body device, for schematically illustrating the flow of whole manufacturing process.
In step 501, there is provided semi-conductive substrate, on a semiconductor substrate formed with interlayer dielectric layer (ILD0),
Dummy gate structure in dummy gate structure and PMOS area in NMOS area.Remove the dummy gate structure in NMOS area
With the dummy gate structure in PMOS area, to form metal gates groove；
In step 502, be sequentially depositing in the metal gates groove in NMOS area and PMOS area to be formed boundary layer,
High k dielectric layer, the first coating, barrier layer and p-type workfunction layers；
In step 503, using the p-type workfunction layers in photoetching process removal NMOS area, barrier layer and first
Coating；
In step 504, the second coating is formed on a semiconductor substrate, reprocesses the cover surface；
In step 505, N-type workfunction layers and metal gate layer are sequentially formed on the coating, are performed
CMP。
The method of the present invention proposes a kind of new metal gate electrode thin membrane stack, to prevent the diffusion of the aluminium in PMOS area,
The diffusion of aluminium, the semiconductor devices for finally making the semiconductor device structure to be formed be formed with traditional handicraft are utilized in NMOS area
Structure has good gap filling edge and relatively low metal gates resistance, to improve the overall performance of semiconductor devices, improves
The yields of semiconductor.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member it is understood that the invention is not limited in above-described embodiment, according to the present invention can also make more kinds of modifications and
Modification, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is by attached
Claims and its equivalent scope are defined.
Claims (12)
1. a kind of method for making semiconductor devices, including：
Semiconductor substrate with first area and second area is provided, the first area includes dummy gate, and described second
Region includes dummy gate, wherein the first area is PMOS area, the second area is NMOS area；
The dummy gate in the dummy gate and the second area in the first area is removed, with the first area
First groove is formed, second groove is formed in the second area；
It is sequentially depositing to form high k dielectric layer, the first covering on the bottom and side wall of the first groove and the second groove
Layer and p-type workfunction layers；
Expose institute using the p-type workfunction layers in the photoetching process removal second groove and first coating
High k dielectric layer is stated, to form the 3rd groove；
The second coating, barrier layer, N-type are sequentially formed on the bottom and side wall of the first groove and the 3rd groove
Workfunction layers and metal gate layers.
2. a kind of method for making semiconductor devices, including：
Semiconductor substrate with first area and second area is provided, the first area includes dummy gate, and described second
Region includes dummy gate, wherein the first area is PMOS area, the second area is NMOS area；
The dummy gate in the dummy gate and the second area in the first area is removed, with the first area
First groove is formed, second groove is formed in the second area；
It is sequentially depositing to form high k dielectric layer, the first covering on the bottom and side wall of the first groove and the second groove
Layer, barrier layer and p-type workfunction layers；
Using the p-type workfunction layers in the photoetching process removal second groove, the barrier layer and described first
Coating exposes the high k dielectric layer, to form the 3rd groove；
The second coating is formed on the bottom and side wall of the first groove and the 3rd groove；
One processing step is carried out to second coating, to prevent the N-type workfunction layers and the metal gates that are formed afterwards
Metal ion in layer is diffused into the Rotating fields under it；
N-type workfunction layers and metal gate layers are sequentially formed on second coating after treatment.
3. the method as described in claim 1, it is characterised in that removed using wet etching or dry etching in second area
P-type workfunction layers and first coating, the etching technics there are the p-type workfunction layers and described
High etching selectivity of one coating to the high k dielectric layer.
4. method as claimed in claim 2, it is characterised in that removed using wet etching or dry etching in second area
P-type workfunction layers, the barrier layer and first coating, the etching technics has p-type work function gold
Belong to the high etching selectivity of layer, the barrier layer and first coating to the high k dielectric layer.
5. method as claimed in claim 1 or 2, it is characterised in that the material of second coating is titanium nitride, silicon nitride
Titanium, the material on the barrier layer is tantalum nitride, tantalum or calorize tantalum, and the thickness on the barrier layer is 5 angstroms to 20 angstroms.
6. method as claimed in claim 2, it is characterised in that the processing step, the annealing are performed using annealing process
Technique is peak value annealing, Millisecond annealing or short annealing, and the temperature for performing the annealing process is 400 DEG C to 600 DEG C, is performed
The time of the annealing process is 10 seconds to 60 seconds, is being passed through the mixed gas of oxygen, nitrogen, ammonia or oxygen and nitrogen
Under the conditions of perform the annealing process.
7. method as claimed in claim 2, it is characterised in that Semiconductor substrate exposure is performed into the place in atmosphere
Manage step.
8. method as claimed in claim 2, it is characterised in that using plasma technique performs the processing step, described
The reaction time of plasma process is 10 seconds to 60 seconds, is being passed through the gaseous mixture of oxygen, nitrogen, argon gas or argon gas and nitrogen
The plasma process is performed under conditions of body, the power for performing the plasma process is 100W to 500W.
9. method as claimed in claim 2, it is characterised in that the processing step is to form titanium on second coating
Layer or silicon layer, then perform annealing process, to form Ti on second coatingxOyLayer or SixOyLayer, the titanium
The thickness of layer or the silicon layer is 5 angstroms to 15 angstroms.
10. method as claimed in claim 1 or 2, it is characterised in that between the Semiconductor substrate and the high k dielectric layer
It is also formed with boundary layer, the material of the boundary layer is thermal oxide layer, nitrogen oxide layer or chemical oxide layer, the boundary layer
Thickness range be 5 angstroms to 10 angstroms.
11. method as claimed in claim 1 or 2, it is characterised in that the high K is formed using CVD, ALD or PVD
Dielectric layer, first coating, second coating, the barrier layer, the p-type workfunction layers, the N-type work(
Function metal, the metal gate layers.
12. method as claimed in claim 1 or 2, it is characterised in that the thickness of first coating and second coating
It is 5 angstroms to 20 angstroms to spend scope, and the thickness ranges of the p-type workfunction layers is 10 angstroms to 580 angstroms, N-type work function gold
The thickness range for belonging to layer is 10 angstroms to 80 angstroms.
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| CN107346783B (en) * | 2016-05-06 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN107978564B (en) * | 2016-10-21 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
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