CN105304568B - A method of reducing the fluctuation of high-K metal gate device threshold voltage - Google Patents
A method of reducing the fluctuation of high-K metal gate device threshold voltage Download PDFInfo
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- CN105304568B CN105304568B CN201510608986.5A CN201510608986A CN105304568B CN 105304568 B CN105304568 B CN 105304568B CN 201510608986 A CN201510608986 A CN 201510608986A CN 105304568 B CN105304568 B CN 105304568B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
Abstract
The present invention relates to semiconductor applications more particularly to a kind of methods reducing the fluctuation of high-K metal gate device threshold voltage.A method of the fluctuation of high-K metal gate device threshold voltage being reduced, method includes：A substrate is provided, in forming PMOS area and NMOS area on substrate, wherein PMOS area includes high k dielectric layer with NMOS area；In the disposed thereon titanium nitride (TiN) of the high k dielectric layer of PMOS area and NMOS area；A silicon fiml is deposited as barrier layer in PMOS area and NMOS area, and P-type workfunction layer is deposited on barrier layer；P-type workfunction layer, the silicon fiml of NMOS area are removed successively；Annealing process is carried out to PMOS area.
Description
Technical field
The present invention relates to semiconductor applications more particularly to a kind of methods reducing the fluctuation of high-K metal gate device threshold voltage.
Background technology
Integrated higher and higher with semiconductor devices, the requirement to the size of semiconductor devices is also just smaller and smaller,
When sub-micro grade, such as 45 nanometers and when following technology node, the reduction of the channel length in MOSFET and
The thinned of gate oxide thickness can bring high electric leakage, can cause the drift of threshold voltage.
In high-k/metal gate semiconductor technology, usually tantalum nitride (TaN) is selected to be used as NMOS area P-type workfunction layer TiN
The barrier layer of removal, and TiN etching processing procedures itself have certain fluctuation, this fluctuation can cause the TaN as barrier layer surplus
The fluctuation of remaining thickness, finally also just reflection has been arrived in the threshold voltage fluctuation of NMOS metal gate devices.
Invention content
For the problems of above-mentioned semiconductor device, (High-K, high dielectric are normal by a kind of high K of reduction of present invention offer
Number media) fluctuation of metal gate device threshold voltage method so that the fluctuation of the threshold voltage of metal gate device reduces.
The present invention adopts the following technical scheme that：
A method of the fluctuation of high-K metal gate device threshold voltage is reduced, the method includes：
One substrate is provided, in forming PMOS area and NMOS area on the substrate, wherein the PMOS area with it is described
NMOS area includes high k dielectric layer；
In the disposed thereon titanium nitride (TiN) of the PMOS area and the high k dielectric layer of the NMOS area；
A silicon fiml is deposited as barrier layer in the PMOS area and the NMOS area, is deposited on the barrier layer
P-type workfunction layer；
The P-type workfunction layer of the NMOS area, the silicon fiml are removed successively；
Annealing process is carried out to the PMOS area.
Preferably, the method further includes：
After carrying out annealing process, to the PMOS area and NMOS area deposit N-type workfunction layer and metal gate work
Skill.
Preferably, the silicon fiml is deposited using atomic layer deposition apparatus.
Preferably, use the atomic layer deposition apparatus deposit the thickness of the silicon fiml for
Preferably, the P-type workfunction layer is TiN.
Preferably, the P-type workfunction layer of the NMOS area is removed using photoetching and etching technics.
Preferably, the silicon fiml is removed using tetramethylammonium hydroxide.
Preferably, the annealing temperature in the annealing process is 50-1250 degrees Celsius.
Preferably, the time of the annealing process is 0.1-1000 seconds.
Preferably, deposited silicon nitride layer on the substrate, the PMOS area are formed in the nitrogen with the NMOS area
In SiClx layer.
Preferably, the PMOS area and the NMOS area further include middle layer.
The beneficial effects of the invention are as follows：
The present invention substitutes TaN as barrier layer, in NMOS area p-type work content in HKMG semiconductor technologies, using silicon fiml
After several layers of TiN are removed, excess silicon barrier layer is removed therewith, the NMOS threshold values come with this barrier layer residual thickness wave zone of forgoing
Voltage fluctuation.And and then so that the silicon of PMOS area is fully spread using annealing process, it is formed with the TiN of its levels
TiSiN middle layers.Because of its amorphism, there is this nitrogen silicon compound smaller work function to fluctuate for itself, can stop follow-up
The downward diffusion of upper layer metallic atom also reduces the threshold voltage fluctuation of PMOS metal gate devices.
Description of the drawings
Fig. 1 is a kind of method schematic diagram for reducing high-K metal gate device threshold voltage and fluctuating embodiment one of the present invention；
Fig. 2 a-2f are a kind of work for the barrier layer embodiment two reducing the fluctuation of high-K metal gate device threshold voltage of the present invention
Skill flow chart.
Specific implementation mode
It should be noted that in the absence of conflict, following technical proposals can be combined with each other between technical characteristic.
The specific implementation mode of the present invention is further described below in conjunction with the accompanying drawings：
Embodiment one
Fig. 1 is a kind of method schematic diagram reducing the fluctuation of high-K metal gate device threshold voltage of the present invention, as shown in Figure 1, this
The method of embodiment includes：A substrate is provided, in formation PMOS area and NMOS area, wherein PMOS area and NMOS on substrate
Region includes high k dielectric layer；In the disposed thereon titanium nitride (TiN) of the high k dielectric layer of PMOS area and NMOS area；In
PMOS area deposits a silicon fiml as barrier layer with NMOS area, and P-type workfunction layer is deposited on barrier layer；It removes successively
P-type workfunction layer, the silicon fiml of NMOS area；Annealing process is carried out to PMOS area.
Embodiment two
Fig. 2 a-2f are a kind of work for the barrier layer embodiment two reducing the fluctuation of high-K metal gate device threshold voltage of the present invention
Skill flow chart provides a silicon substrate 100 as shown in Figure 2 a, in depositing a silicon nitride (SiN) layer on substrate 100, in silicon nitride layer
102 inside form PMOS area and NMOS area, and PMOS area is followed successively by middle layer 101 from outside to inside with NMOS area, high K is situated between
Electric layer 103, titanium nitride layer 104.
As shown in Figure 2 b, using atomic layer deposition apparatus in one silicon fiml 105 of disposed thereon of titanium nitride layer 104, this silicon fiml
105 are used as barrier layer, wherein silicon fiml 105 to be deposited on two regions PMOS and NMOS.The thickness of the silicon fiml 105 of above-mentioned deposition
For
As shown in Figure 2 c, a P-type workfunction layer 106 is deposited in the top of silicon fiml 105, this work-function layer is titanium nitride
(TiN), wherein p-type power layer is deposited in PMOS area with NMOS area.
As shown in Figure 2 d, using the TiN work-function layers in photoetching process and etching technics removal NMOS area, etching stopping
In the upper surface of silicon fiml 105.
As shown in Figure 2 e, the silicon fiml 105 that NMOS area is removed using wet method, wherein tetramethyl hydroxide nitrogen can be utilized
(TMAH) above-mentioned silicon fiml 105 is removed.
As shown in figure 2f, annealing process is carried out to PMOS area, so that the silicon of PMOS area is fully spread using annealing process,
TiSiN middle layers 107 are formed with the TiN of its levels.For this nitrogen silicon compound because of its amorphism, itself has smaller work(
Function fluctuates, and can stop the downward diffusion of follow-up upper layer metallic atom, also reduce the threshold voltage of PMOS metal gate devices
Fluctuation.Annealing temperature is 50~1250 degrees Celsius (DEG C), and the time of annealing is 0.1~1000 second (s), can carry out N later
The deposit of type work-function layer and follow-up normal metal grid technique.
In conclusion the present invention is in high-k/metal gate semiconductor technology, according in normal process flow to high k dielectric layer
After the completion of titanium nitride (TiN) deposit of side, deposit silicon fiml is as barrier layer, then deposits P-type workfunction layer TiN.Then, pass through light
It carves and etching removes NMOS area P-type workfunction layer, rest on the silicon as barrier layer.Followed by TMAH (four
Methyl aqua ammonia) silicon fiml of NMOS area is removed, then make the TiN of the silicon fiml and its levels of PMOS area by annealing process
TiSiN middle layers are formed, because of its amorphism, there is this nitrogen silicon compound smaller work function to fluctuate for itself, and can hinder
The downward diffusion for keeping off follow-up upper layer metallic atom reduces the threshold voltage fluctuation of PMOS metal gate devices.And in NMOS area
Domain, because barrier layer is completely removed by wet method, NMOS would not be etched the barrier layer residual thickness fluctuation of wave zone by TiN
Influence, finally also reduce the threshold voltage fluctuation of NMOS metal gate devices.
By description and accompanying drawings, the exemplary embodiments of the specific structure of specific implementation mode are given, based on present invention essence
God can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering the true intention and range of the present invention as.It is weighing
The range and content of any and all equivalences within the scope of sharp claim, are all considered as still belonging to the intent and scope of the invention.
Claims (10)
1. a kind of method reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that the method includes：
A substrate is provided, in forming PMOS area and NMOS area on the substrate, wherein the PMOS area and the NMOS
Region includes high k dielectric layer；
In the disposed thereon titanium nitride (TiN) of the PMOS area and the high k dielectric layer of the NMOS area；
A silicon fiml is deposited as barrier layer in the PMOS area and the NMOS area, and p-type is deposited on the barrier layer
Work-function layer；
The P-type workfunction layer of the NMOS area, the silicon fiml are removed successively；
Annealing process is carried out to the PMOS area；
Wherein, the P-type workfunction layer is TiN.
2. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that described
Method further includes：
After carrying out annealing process, go forward side by side row metal grid work to the PMOS area and NMOS area deposit N-type workfunction layer
Skill.
3. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that use
Atomic layer deposition apparatus deposits the silicon fiml.
4. the method according to claim 3 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that use
The thickness that the atomic layer deposition apparatus deposits the silicon fiml is
5. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that use
Photoetching removes the P-type workfunction layer of the NMOS area with etching technics.
6. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that use
Tetramethylammonium hydroxide removes the silicon fiml.
7. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that described
Annealing temperature in annealing process is 50-1250 degrees Celsius.
8. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that described
The time of annealing process is 0.1-1000 seconds.
9. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that described
Deposited silicon nitride layer on substrate, the PMOS area are formed in the NMOS area in the silicon nitride layer.
10. the method according to claim 1 for reducing the fluctuation of high-K metal gate device threshold voltage, which is characterized in that described
PMOS area and the NMOS area further include middle layer.
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| CN107437562B (en) * | 2016-05-27 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN108807158B (en) * | 2017-04-26 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436825B1 (en) * | 2000-04-03 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of copper barrier layer formation |
| CN103579319A (en) * | 2012-07-17 | 2014-02-12 | 国际商业机器公司 | Laminated structure, semiconductor device and manufacturing method thereof |
| CN104752316A (en) * | 2013-12-25 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436825B1 (en) * | 2000-04-03 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of copper barrier layer formation |
| CN103579319A (en) * | 2012-07-17 | 2014-02-12 | 国际商业机器公司 | Laminated structure, semiconductor device and manufacturing method thereof |
| CN104752316A (en) * | 2013-12-25 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
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