CN106328539B - Multigate device and its manufacturing method - Google Patents

Multigate device and its manufacturing method Download PDF

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Publication number
CN106328539B
CN106328539B CN201610124431.8A CN201610124431A CN106328539B CN 106328539 B CN106328539 B CN 106328539B CN 201610124431 A CN201610124431 A CN 201610124431A CN 106328539 B CN106328539 B CN 106328539B
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layer
epitaxial layer
fin
epitaxial
semiconductor
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CN106328539A (en
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江国诚
蔡庆威
卡洛斯·H·迪亚兹
王志豪
连万益
梁英強
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract

The present invention describes a kind of method of semiconductor devices manufacture, and this method includes forming the fin extended from substrate and with source/drain regions and channel region.Fin includes the first epitaxial layer with the first component and the second epitaxial layer on the first epitaxial layer, and the second epitaxial layer has the second component.The second epitaxial layer is removed from the source/drain regions of fin to form gap.Gap is filled with dielectric material.Another epitaxial material is formed at least two surfaces of the first epitaxial layer to form source/drain component.The present invention also provides a kind of multiple gate semiconductor devices.

Description

Multigate device and its manufacturing method
Technical field
This patent disclosure relates generally to semiconductor fields, more particularly, to multigate device and its manufacturing method.
Background technique
Electronics industry has gone through for smaller and faster electronic device the demand constantly increased, these are smaller and more Fast electronic device can support more, increasingly complex and advanced function simultaneously.Therefore, semi-conductor industry exist manufacture it is low at Originally, the lasting trend of high-performance and the integrated circuit (IC) of low-power consumption.So far, these targets have largely passed through and have pressed Scale smaller semiconducter IC size (for example, minimize characteristic size) and therefore improve manufacture efficiency and reduce relevant cost and It realizes.However, such scaled complexity for making semiconductor fabrication process increases.Therefore, in semiconducter IC and device In the realization of lasting progress require the progress similar in technology in semiconductor fabrication process.
Recently, multigate device is had been incorporated into improve grid control by increasing gate-channel connection, reduce and cut Only state current and reduction short-channel effect (SCE).Such multigate device having been incorporated into is loopful gate transistor (GAA).The title of GAA device is derived from the gate structure that can extend around channel region, to provide on two sides or four sides To the entrance of channel.GAA device is compatible and GAA device with traditional complementary metal oxide semiconductor (CMOS) technique The structure of part allows them significantly scaled while keeping grid control and reducing SCE.In traditional technique, GAA device provides the channel in silicon nanowires.However, the integrated of manufacture of the GAA device around nano wire can be Challenge.For example, although existing method has been satisfied by many aspects, about formation enhanced strain, source/drain shape At and other component challenge so that existing method is not to be all satisfactory in all respects.
Summary of the invention
According to an aspect of the invention, there is provided a kind of method of semiconductor devices manufacture, comprising: formation is prolonged from substrate The fin stretched, the fin have source/drain regions and channel region, wherein the fin includes the first epitaxial layer with the first component With the second epitaxial layer being located on first epitaxial layer, second epitaxial layer has the second component；Described in the fin Source/drain regions remove second epitaxial layer to form gap；The gap is filled with dielectric material；And in the dielectric While material fills the gap, another epitaxial material is grown at least two surfaces of first epitaxial layer to be formed Source/drain component.
Preferably, this method further include: third epitaxial layer is formed below first epitaxial layer；It aoxidizes outside the third Prolong layer to form the third epitaxial layer of oxidation；Wherein, under the grid of the third epitaxial layer of the oxidation on the channel region The lower section of the square and described source/drain component.
Preferably, this method further include: it is another to be formed to remove second epitaxial layer from the channel region of the fin Gap；And gate structure is formed on first epitaxial layer being located in the channel region, wherein in another gap It is middle to form the gate structure at least partly.
Preferably, this method further include: before forming the fin, implement the anti-break-through for reaching the substrate interior (APT) ion implanting；And after implementing the APT ion implanting and before forming the fin, over the substrate Side deposits first epitaxial layer and the second epitaxial layer described in the first epitaxial layer disposed thereon.
Preferably, this method further include: first epitaxial layer is formed by growth silicon layer；And by directly in institute It states and grows germanium-silicon layer on silicon layer to form second epitaxial layer.
Preferably, first epitaxial layer has the first oxidation rate, and second epitaxial layer, which has, is greater than described first Second oxidation rate of oxidation rate.
Preferably, this method further include: formed and extended from the substrate and another with source/drain regions and channel region One fin, wherein another fin includes first epitaxial layer and second epitaxial layer；Aoxidize described the of another fin Two epitaxial layers, while hard mask layer protects the fin；And source/drain is grown on first epitaxial layer of another fin Pole epitaxial layer, wherein second epitaxial layer of the source/drain extensions layer adjacent to the oxidation.
Preferably, the thickness of the second epitaxial layer of the oxidation is greater than the thickness of second epitaxial layer, thus described the One epitaxial layer the top surface in the channel region of another fin lower than first epitaxial layer described in another fin Top surface in source/drain regions.
Preferably, this method further include: form gate structure on the fin, wherein the gate structure is arranged in institute State the top of first epitaxial layer in channel region, the top of bottom and opposite sides.
Preferably, this method comprises: top, bottom and the opposite sides of first epitaxial layer in the channel region Top form the high k gate dielectric of the gate structure.
According to another aspect of the present invention, a kind of method for manufacturing multigate device is provided, which comprises growth Epitaxial layers stack overlapping piece including the first epitaxial layer, the second epitaxial layer and third epitaxial layer；Pattern the epitaxial layers stack overlapping piece with Form fin element；Dummy gate structure is formed above the fin element；By the institute in the firstth area and the secondth area that are located at the fin State the second epitaxial layer and be transformed into dielectric layer, wherein the third area of the fin between firstth area and secondth area, In, the third area is located at below the dummy gate structure；After changing second epitaxial layer, the dummy grid knot is removed Structure, to form groove；And metal gate structure is formed in the trench, wherein the metal gates are arranged described In the multi-panel of each of first epitaxial layer and the third epitaxial layer.
Preferably, the transformation includes second epitaxial layer aoxidized in firstth area.
Preferably, the transformation includes: that removal is located at second epitaxial layer in firstth area to form gap；With And the gap is filled with dielectric material.
Preferably, this method further include: after removing the dummy gate structure, removed from the third area of the fin Second epitaxial layer is to form gap in the third area.
Preferably, the high k dielectric layer of the metal gate structure is arranged in the gap in the third area.
Preferably, this method further include: under first epitaxial layer, second epitaxial layer and the third epitaxial layer Face forms fourth epitaxial layer；And the oxidation fourth epitaxial layer is to form oxide skin(coating), wherein the thickness of the oxide skin(coating) Greater than the thickness of the dielectric layer.
According to another aspect of the present invention, a kind of multiple gate semiconductor device is provided, comprising: fin element prolongs from substrate It stretches；Gate structure extends above the channel region of the fin element, wherein the channel region of the fin element includes quilt Multiple channel semiconductors that the part of the gate structure surrounds；And the source/drain regions of the fin element, it is neighbouring described Gate structure, wherein the source/drain regions include: the first semiconductor layer, the dielectric above first semiconductor layer Layer and positioned at the dielectric layer the second semiconductor layer.
Preferably, semiconductor devices further include: third semiconductor layer, third semiconductor layer covering described the first half Conductor layer and second semiconductor layer and have a common boundary with the side wall of the dielectric layer.
Preferably, first semiconductor layer includes Si, and the dielectric layer includes the SiGe of oxidation, second semiconductor Layer includes Si.
Preferably, the high-K gate dielectric of the gate structure be arranged in each of the multiple channel semiconductor it Between.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts Size can be arbitrarily increased or decreased.
Fig. 1 is manufacture various aspects offer according to the present invention and the multiple-grid including being located at the isolated area below grid The flow chart of pole device and its partial method.
Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 A, Figure 13, Figure 14, Figure 15 and Figure 16 It is the isometric view according to the embodiment of the device 200 of the various aspects of the method for Fig. 1；
Figure 12 B and Figure 17 to Figure 19 be according to the embodiment of the device 200 of the various aspects of the method for Fig. 1 correspond to On the sectional view of respective isometric view listed；
Figure 20 is the another method of manufacture multigate device of one or more aspects according to the present invention or part thereof Flow chart；
Figure 21 is the implementation of the device 200 of the various aspects of 0 method according to fig. 2 to Figure 29, Figure 30 A and Figure 31 to Figure 34 The isometric view of example；
Figure 30 B, Figure 35, Figure 36 and Figure 37 are that the embodiment of the device of the various aspects of 0 method corresponds to according to fig. 2 The sectional view of respective isometric view listed above；
Figure 38 is each N-shaped of manufacture and p-type multigate device and its part of one or more aspects according to the present invention Method flow chart；
Figure 39 A, Figure 40 A, Figure 41 A, Figure 42 A, Figure 43 A, Figure 44 A, Figure 45 A, Figure 46 A, Figure 47 A are the methods according to Figure 38 Various aspects the first kind device embodiment isometric view；Figure 39 B, Figure 40 B, Figure 41 B, Figure 42 B, Figure 43 B, figure 44B, Figure 45 B, Figure 46 B, Figure 47 B are according to the equidistant of the embodiment of the device of the Second Type of the various aspects of the method for Figure 38 View；
Figure 48 A, Figure 49 A, Figure 50 A are the embodiments according to the device of the first kind of the various aspects of the method for Figure 38 Sectional view corresponding to respective isometric view listed above；Figure 48 B, Figure 49 B, Figure 50 B are each according to the method for Figure 38 The sectional view corresponding to respective isometric view listed above of the embodiment of the device of the Second Type of aspect；
Figure 51 is each N-shaped of manufacture and p-type multigate device and its part of one or more aspects according to the present invention Method flow chart；
Figure 52 A, Figure 53 A, Figure 54 A, Figure 55 A, Figure 56 A, Figure 57 A, Figure 58 A, Figure 59 A, Figure 60 A are the methods according to Figure 51 Various aspects the first kind device embodiment isometric view；Figure 52 B, Figure 53 B, Figure 54 B, Figure 55 B, Figure 56 B, figure 57B, Figure 58 B, Figure 59 B, Figure 60 B are according to the equidistant of the embodiment of the device of the Second Type of the various aspects of the method for Figure 51 View；
Figure 61 A, Figure 62 A, Figure 63 A are the embodiments according to the device of the first kind of the various aspects of the method for Figure 51 Sectional view corresponding to respective isometric view listed above；Figure 61 B, Figure 62 B, Figure 63 B are each according to the method for Figure 51 The sectional view corresponding to respective isometric view listed above of the embodiment of the device of the Second Type of aspect；
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", "lower", " ... it On ", the spatially relative terms such as "upper" with describe an element or component and another (or other) element as shown in the figure or The relationship of component.Other than orientation shown in figure, spatially relative term is intended to include the difference of device in use or operation Orientation.Device can otherwise orient (be rotated by 90 ° or in other directions), and space as used herein is opposite retouches Corresponding explanation can similarly be made by stating symbol.
It should also be noted that the present invention is in current embodiment in the form of multi-gated transistor.Multi-gated transistor includes these Transistor, the gate structure of these transistors are formed in at least two sides of channel region.Multigate device may include p-type metal oxygen Compound semiconductor devices or N metal-oxide semiconductor (MOS) multigate device.Herein, specific example can be rendered as and refer to Be FINFET (due to their fin structure).The multi-gated transistor of referred to as loopful grid (GAA) device is also presented herein The embodiment of type.GAA device include the part of its gate structure or gate structure be formed on the four sides of channel region (for example, Surround channel region part) any device.Device presented herein also includes that channel region is arranged in nanowire channel, strip groove Embodiment in road and/or other suitable channel structures.It is presented herein with to single, continuous gate structure is relevant The embodiment of the device of one or more channel regions (for example, nano wire).However, those skilled in the art will expect Introduction applied to single channel (for example, single nano wire) or any number of channel.Those skilled in the art It can be appreciated that other examples for the semiconductor devices that can benefit from various aspects of the invention.
It is shown in FIG. 1 be include manufacture multigate device semiconductors manufacture method 100.As used herein, Term " multigate device " is used to describe at least some grid materials on more sides at least one channel that device is arranged in Material.In some instances, multigate device can be referred to as on at least four sides at least one channel that device is arranged in Grid material GAA device.Channel region can be referred to as " nano wire ", as it is used herein, channel region includes having respectively The channel region of a geometry (for example, cylindrical, bar shaped) and each size.
Fig. 2 to Figure 11, Figure 12 A and Figure 13 to Figure 16 be method 100 according to the embodiment of semiconductor devices 200 in Fig. 1 Each stage isometric view.Figure 12 B, Figure 17 and Figure 18 are being schemed with listed above, semiconductor devices 200 embodiment The isometric view in each stage of 1 method distinguishes corresponding sectional view.With the other methods embodiment and reality being discussed herein Example device is the same, it should be understood that can by CMOS technology process flow come each section of manufacturing semiconductor devices 200, therefore this Some techniques are only briefly described in text.In addition, example semiconductor device may include other each devices and component, such as its The device of his type is (such as additional transistor, bipolar junction transistor, resistor, capacitor, inductor, diode, molten Silk, static random access memory (SRAM) and/or other logic circuits etc.), but hair for a better understanding of the present invention Bright concept, is simplified.In some embodiments, exemplary means include multiple semiconductor devices (for example, transistor), multiple Semiconductor devices includes PFET that can be interconnected and NFET etc..In addition, such as other methods provided by the invention and exemplary drawings Equally, it shall be noted that the processing step of method 100 together with any description provided in conjunction with Fig. 2 to Figure 19 be only exemplary but It is to be not intended to for protection scope of the present invention to be limited within the scope of following following claims specifically states.
Method 100 starts from frame 102, provides substrate.Substrate is provided in the embodiment of frame 102 referring to the example of Fig. 2 202.In some embodiments, substrate 202 can be semiconductor substrate, such as silicon substrate.Substrate 202 may include being formed in half Each layer of conduction or insulating layer on conductor substrate.Depending on design requirement known in the art, substrate 202 may include each A doping configuration.For example, different dopant profiles (for example, n trap, p trap) can be formed in substrate 202 as different components type (for example, n type field effect transistor (NFET), p-type field effect transistor (PFET)) and design region in.Suitable doping can To include the ion implanting and/or diffusion technique of dopant.Substrate 202 usually has between each area of offer different components type Isolated part (for example, shallow trench isolation (STI) component) between domain.Substrate 202 also includes other semiconductors, such as germanium, carbon SiClx (SiC), SiGe (SiGe) or diamond.Optionally, substrate 202 may include that compound semiconductor and/or alloy are partly led Body.In addition, substrate 202 may be selected to include epitaxial layer (epi layers), and it is strained to improve performance, may include exhausted Silicon (SOI) structure and/or there is other suitable improved components on edge body.
In the embodiment of method 100, in block 102, implement anti-break-through (APT) ion implanting.For example, can be in device Channel region below region in implement APT injection, to prevent break-through or undesirable diffusion.In some embodiments, implement First photoetching (light) step is to pattern the region p-type APT, and implements the second lithography step to pattern the region N-type APT.Example Such as, in some embodiments, implementing the first lithography step may include: formation photoresist layer (resist) above substrate 202； Photoresist is set to be exposed to pattern (for example, p-type APT injecting mask)；Implement postexposure bake technique；And lithographic glue and shape At patterned photoresist layer.By way of example, injected by ion implantation technology to form the p-type in the region p-type APT and mix Miscellaneous dose may include boron, aluminium, gallium, indium or other p-type acceptor materials.Hereafter, in some embodiments, it is possible to implement the second photoetching Step, wherein the second lithography step may include: to form photoresist layer above substrate 202；Photoresist is exposed to pattern (example Such as, N-type APT injecting mask), implement postexposure bake technique；And lithographic glue is to form patterned photoresist layer.It is logical The mode for crossing example, being injected by ion implantation technology to form the N type dopant in the region N-type APT may include arsenic, phosphorus, antimony Or other N-type donor materials.In addition, in various embodiments, APT injection can have for example about 1 × 1018cm-3With 1 × 1019cm-3Between high-dopant concentration.In some embodiments, as discussed below, due on the substrate by APT injection Side subsequently forms separation layer (diffusion barrier layer that may be used as dopant) so APT doping high in this way can be advantageously used Agent concentration.APT injection is shown in Figure 2 for injection 204.
Referring to Fig.1, method 100 is carried out to frame 104, wherein grows one or more epitaxial layers on substrate.With reference to Fig. 3 Example, in the embodiment of frame 104, by APT injection substrate 202 above formed extension stack 302.Extension stacks Part 302 includes the epitaxial layer 304 with the first component, and the epitaxial layer 306 with the second component is between epitaxial layer 304.The One and second component can be different.In embodiment, epitaxial layer 304 is SiGe, and epitaxial layer 306 is silicon.However, including It is possible that providing, which has the first component of different oxidations rate and the other embodiments of the second component,.For example, in each reality It applies in example, epitaxial layer 304 has the first oxidation rate, and epitaxial layer 306 has the second oxidation speed less than the first oxidation rate Rate.In some embodiments, epitaxial layer 304 is including SiGe and when epitaxial layer 306 includes Si, the Si oxidation of epitaxial layer 306 Rate is less than the SiGe oxidation rate of epitaxial layer 304.During subsequent oxidation, as discussed below, each portion of epitaxial layer 304 It point can be fully oxidized, and only epitaxial layer 306 can be not oxidized, or only slightly be oxidized in some embodiments (for example, side wall).
It should be noted that bottommost epitaxial layer is labeled as 304A in order to be easy to refer in the processing step below.However, In some embodiments, epitaxial layer 304A is the material substantially similar with the epitaxial layer 304 that is formed in above epitaxial layer 304A. In embodiment, epitaxial layer 304A is SiGe and epitaxial layer 304 is also SiGe.In other embodiments, epitaxial layer 304A has There is the component different from epitaxial layer 304 and/or epitaxial layer 306.The thickness of epitaxial layer 304A can be greater than the epitaxial layer 304 above covered Thickness.
Epitaxial layer 306 and its part can form the channel region of multigate device 200.For example, epitaxial layer 306 can be claimed For be used to form multigate device 200 (such as GAA device) channel region " nano wire ".As described below, these " nano wires " It is also used for forming the source/drain component of multigate device 200.Again, term as used herein, " nano wire " refer to justifying The semiconductor layer of the other configurations of cylindricality and such as bar shaped.It is discussed further below using the epitaxial layer 306 of channel to limit Determine one or more channels of device.
It should be noted that three (3) layer epitaxial layer 304 (including 304A) and three layer 306 is shown in FIG. 3, this is merely to illustrate Purpose but be not intended to limits the present invention within the scope of claim specifically states.It should be recognized that any number of Epitaxial layer can be formed in extension stack 302；The number of layer depends on the desired number of the channel for device 200. In some embodiments, the number of epitaxial layer 306 is between 2 and 10.
In some embodiments, epitaxial layer 304 has the thickness in 2 nanometers to 6 nanometers (nm) ranges.Epitaxial layer 304 (providing on layer 304A) can be basically uniform on thickness.In some embodiments, epitaxial layer 304A has The thickness of about 8nm to 15nm.In some embodiments, the thickness of range of the epitaxial layer 306 with 8nm to 15nm.Some In embodiment, each epitaxial layer 306 in stack is substantially consistent on thickness.Such as described in detail below, epitaxial layer 306 may be used as the channel region of the multigate device subsequently formed, therefore the thickness of epitaxial layer 306 can be examined based on device performance Consider to select.Epitaxial layer 304 is used to limit the clearance distance between the neighbouring channel region of the multigate device subsequently formed, because This 304 thickness of epitaxial layer can be considered based on device performance to select.
By way of example, molecular beam epitaxy (MBE) technique, metal-organic ligand can be passed through (MOCVD) technique and/or other suitable epitaxial growth technologies implement the epitaxial growth of each layer in stack 302.Some In embodiment, each layer of such as epitaxial growth of layer 306 includes material identical with substrate 202.In some embodiments, extension The layer 304,306 of growth includes the material different from substrate 202.As above statement, at least some examples, epitaxial layer 304 is wrapped SiGe (SiGe) layer and epitaxial layer 306 that include epitaxial growth include silicon (Si) layer of epitaxial growth.In some embodiments, outside Prolonging a layer 304A is also SiGe.Optionally, any of epitaxial layer 304 and 306 may include other materials in some embodiments: Such as germanium；Such as compound semiconductor materials of silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide；It is all Such as the alloy semiconductor of SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and/or GaInAsP；Or their combination. As discussed, the material of epitaxial layer 304,306 can be provided based on the different oxidation of offer, etching selectivity characteristic.? In each embodiment, epitaxial layer 304,306 is substantially free of dopant (that is, having from 0cm-3To about 1 × 1017cm-3Non- Levy (extrinsic) concentration of dopant), wherein for example, not implementing deliberate doping in extension growth period.
Also as shown in the example of Fig. 3, hard mask (HM) layer 308 can be formed above extension stack 302.Some In embodiment, HM layer 308 includes oxide skin(coating) (for example, may include SiO2Oxygen pad layer) and be formed in above oxide skin(coating) Nitride layer is (for example, may include Si3N4Pad nitrogen layer).In some instances, HM layer 308 include thermally grown oxide, The oxide of CVD deposition and/or the oxide of ALD deposition.In some embodiments, HM layer 308 includes by CVD or other conjunctions The nitride layer of suitable technology deposition.HM layer 308 can be used for protecting the part of substrate 202 and/or extension stack 302 and/ Or for limiting pattern described below (for example, fin element).
Then, method 100 is carried out to frame 106, wherein forming and patterning fin element.Referring to the example of Fig. 4, in frame In 106 embodiment, the multiple fin elements 402 extended from substrate 202 are formed.In various embodiments, each fin element 402 is equal Substrate portions including being formed by substrate 202, each epitaxial layer (including epitaxial layer 304/304A and 306) in extension stack Part and the part HM from HM layer 308.
The appropriate process including photoetching and etch process can be used to manufacture fin 402.Photoetching process may include: to serve as a contrast 202 top of bottom (for example, 308 top of HM layer of Fig. 3) forms photoresist layer；Photoresist layer is exposed to pattern；After implementing exposure Baking process；And lithographic glue is to form the masking element including photoresist.In some embodiments, electronics can be used Beam (e- beam) photoetching process implements patterning photoresist to form masking element.Then masking element can be used for protecting substrate 202 region and each layer being formed on substrate 202, while etch process is formed in unprotected region across HM layers 308, across extension stack 302 up to the groove 404 in substrate 202, to form the fin 402 of multiple extensions.It can be used Dry ecthing (for example, reactive ion etching), wet etching and/or other suitable techniques etch groove 404.
Also many other embodiments for the method that fin is formed on the substrate can be used, it may for example comprise limit fin area (for example, passing through mask or isolated area) and the epitaxial growth extension stack 302 in the form of fin 402.In some embodiments In, forming fin 402 may include the width for trimming technique to reduce fin 402.Trimming technique may include wet or dry ecthing work Skill.
Method 100 then advancees to frame 108, wherein implementing oxidation technology to form isolated area in fin element.Referring to figure 5, in the embodiment of frame 108, device 200 is exposed to oxidation technology, each of multiple fins 402 of the oxidation technology complete oxidation The epitaxial layer portion 304A of fin.Epitaxial layer portion 304A is converted into oxide layer 502 (providing isolation zones/layers).In some embodiments In, oxide layer 502 has the thickness of from about 5 to about 25 nanometers of (nm) ranges.In some embodiments, oxide layer 502 can wrap Include the oxide (SiGeOx) of SiGe.
The oxidation technology of frame 108 may include forming and patterning each masking layer, so that oxidation is controlled in extension Layer 304A.In other embodiments, due to the component of epitaxial layer 304A, oxidation technology is selective oxidation.In some instances, It can implement oxidation technology by the way that device 200 is exposed to wet oxidation, dry oxidation process or their combination.At least some In embodiment, under the pressure of 1ATM, within the temperature range of about 400 DEG C to 600 DEG C, device 200 is exposed to wet oxygen chemical industry Water vapour or steam (were used as oxidant) by skill, and for about 0.5 to 2 hour time.It should be noted that oxidation provided herein Process conditions are only examples, are not intended to limit.
As described above, in some embodiments, the first epitaxial layer portion 304A may include having the first oxidation rate Material and the second epitaxial layer portion 306 may include the material with the second oxidation rate less than the first oxidation rate.Example Such as, the first epitaxial layer portion 304A includes SiGe and in embodiment that the second epitaxial layer portion 306 includes Si, faster SiGe Oxidation rate (that is, compared to Si) ensures that SiGe layer (the first epitaxial layer portion 304A) is fully oxidized and other epitaxial layers 304 Oxidation be minimized or eliminate.It is provided not it will be understood that any of multiple materials discussed above can choose to be used as First and second epitaxial layer portions of same suitable oxidation rate.
The oxide skin(coating) 502 of the generation of each fin element 402 may be used as mixing to being previously injected to the APT in substrate 202 The diffusion barrier layer of miscellaneous dose (can reside in the substrate 202 below oxide skin(coating) 502).Therefore, in each reality It applies in example, the epitaxial layer 306 that oxide skin(coating) 502 is used to that the APT dopant in substrate portions 202 to be stopped to diffuse to above for example In (may be used as the channel region of multigate device subsequently formed).In other embodiments, oxide layer 502 is omitted.
Method 100 is carried out to frame 110, wherein forming shallow trench isolation (STI) component between fin element.Referring to Fig. 6's Example, STI component 602 are arranged between fin 402.For example, in some embodiments, first in 202 disposed thereon dielectric of substrate Layer fills groove 404 with dielectric material.In some embodiments, dielectric layer may include SiO2, silicon nitride, silicon oxynitride, fluorine Silicate glass (FSG), low K dielectrics, their combination and/or other suitable materials known in the art of doping.? In each example, CVD technique, sub-atmospheric pressure CVD (SACVD) technique, flowable CVD technique, ALD technique, PVD can be passed through And/or other suitable techniques carry out dielectric layer.It in some embodiments, can be to device after the deposition of dielectric layer 200 anneal for example to improve the quality of dielectric layer.In some embodiments, dielectric layer (and the STI component subsequently formed It 602) may include multilayered structure, for example, having one or more layings.
In forming STI component, after the deposition of dielectric layer, such as by chemically mechanical polishing (CMP) technique, it is thinned With the dielectric material of planarization deposition.CMP process can planarize top surface and STI component 602 is consequently formed.As shown in fig. 6, one In a little embodiments, top surface for planarizing device 200 and the CMP process for forming STI component 602 be can be used for from multiple HM layer 308 is removed at each fin element of fin element 402.In some embodiments, it may be selected to use suitable etch process (example Such as, do or wet etching) implement the removal of HM layer 308.
The frame 110 of continuation method 100 keeps the isolated part between fin element recessed.Referring to the example of Fig. 7, make STI component 602 is recessed to make fin extend on STI component 602.In some embodiments, recessed technique may include dry ecthing work Skill, wet etching process and/or their combination.In some embodiments, recessed depth is controlled (for example, by control etching Time) to lead to the desired height ' H ' on the top of the exposure of fin element 402.Highly ' H ' exposes extension stack 302 Each layer.Although the groove that Fig. 7 shows STI component 602 is substantially coplanar with the top surface of isolation structure 502, in other implementations In example, it may not be necessary to so.
Then method 100 is carried out to frame 112, wherein forming sacrificial layer/component.In some embodiments, pseudo- dielectric is formed Layer and/or dummy gate structure.For example, frame 112 may include pseudo- oxide deposition, it is then the deposition of dummy gate structure.Although The discussion is related to replacing grid technology, is formed by the technique dummy gate structure and is then replaced, but other configurations can To be possible.
Referring to Fig. 8, dielectric layer 802 is formed on substrate 202.In some embodiments, dielectric layer 802 may include SiO2, silicon nitride, high-k dielectric material or other suitable materials.In various embodiments, CVD technique, sub-atmospheric pressure can be passed through CVD (SACVD) technique, flowable CVD technique, ALD technique, PVD and/or other suitable techniques carry out dielectric layer 802. For example, dielectric layer 802 can be used for preventing subsequent processing (for example, formation of subsequent dummy gate structure) to fin element 402 It damages.Can also be as described below deposit including these includes the additional puppet of the dummy gate structure 902 of Fig. 9 (for example, sacrificial Domestic animal) layer.
Referring now to Fig. 9, in the further embodiment of frame 112, implement the manufacture and processing of dummy grid stack.Use figure 9 example forms gate stack 902.In embodiment, gate stack 902 is pseudo- (sacrifice) gate stack, then It is removed, as the frame 122 of method 100 is discussed.(however, with reference to above, in some embodiments of method 100, grid pile Overlapping piece 902 or part thereof can be for example kept, for example, it may be high K/ metal gate stacks part).In such embodiment In, can before the formation of the high-K metal gate stack of such as step 122 implementation method 100 certain steps.)
Therefore, in some embodiments using post tensioned unbonded prestressed concrete technique, gate stack 902 be dummy grid stack and The subsequent processing stage of device 200 will be substituted by final gate stack.Specifically, as described below, gate stack 902 can To be substituted in subsequent processing stage by high k dielectric layer (HK) and metal gate electrode (MG).In some embodiments, gate stack Part 902 is formed in 202 top of substrate, and is at least partially disposed on 402 top of fin element.Fin element 402 is located at grid pile 902 part above of overlapping piece can be referred to as channel region.Gate stack 902 also limits the source/drain regions of fin element 402, For example, adjacent to and positioned at the region of the opposite sides of channel region in fin and extension stack 302.
In some embodiments, gate stack 902 includes dielectric layer 802, electrode layer 904 and may include 908 and of layer The hard mask 906 of 910 (for example, oxide skin(coating) 908 and nitride layers 910).In some embodiments, dielectric layer 802 does not include In gate stack 902, for example, being removed before the deposition of gate stack 902.In some embodiments, additionally Dummy grid dielectric layer (other than dielectric layer 802 or substitution dielectric layer 802) is included in gate stack 902.By such as Layer deposition, patterning, etching and other suitable treatment process each processing step form gate stack 902.Show Example property layer depositing operation include CVD (including low pressure chemical vapor deposition and plasma enhanced CVD), PVD, ALD, thermal oxide, electron beam evaporation or Other suitable depositing operations or their combination.In forming gate stack, for example, Patternized technique includes photoetching process (for example, photoetching or electron beam lithography), photoetching process may further include photoresist coating (for example, spin coating), soft baking, cover Mould alignment, exposure, postexposure bake, photoresist developing, rinsing, drying (for example, dehydration and/or hard baking), other are suitable Photoetching technique and/or their combination.In some embodiments, etch process may include dry ecthing (for example, RIE etch), Wet etching and/or other engraving methods.
As it appears from the above, gate stack 902 may include additional gate dielectric.For example, gate stack 902 can be with Including silica.Alternately or additionally, the gate dielectric of gate stack 902 may include silicon nitride, high-k dielectric material Or other suitable materials.In some embodiments, the electrode layer 904 of gate stack 902 may include that the silicon of polycrystalline state is (more Crystal silicon).In some embodiments, hard mask 906 includes such as including SiO2Oxygen pad layer oxide skin(coating) 908.In some realities It applies in example, hard mask 906 includes such as including Si3N4, silicon oxynitride pad nitrogen (pad nitride) layer nitride layer 910 or Optionally include silicon carbide.
As shown in figure 9, in some embodiments, after forming dummy grid 902, from the exposed region of substrate (including The fin 402 not covered by grid 902) removal dielectric layer 802.
Method 100 then advancees to frame 114, wherein from the source/drain regions of fin element (for example, the neighbouring of fin is located at grid The region of channel region below the stack of pole) removal extension stack selective epitaxial layer.As shown in Figure 10, in fin Epitaxial layer 340 in 402 source/drain regions is removed from substrate 202.Figure 10 is shown in the position of epitaxial layer 340 (Fig. 9) Set the gap 1002 at place.Gap 1002 can be filled with the gas of ambient enviroment (for example, air, N2).In embodiment, pass through Selective wet carving technology removes epitaxial layer 340.In some embodiments, selective wet carving technology includes APM etching (example Such as, ammonium hydroxide-hydrogen peroxide-aqueous mixtures).In some embodiments, selective removal includes that oxidation SiGe is then removed SiGeOx.For example, passing through O3Cleaning provides oxidation and then passes through such as NH4The etchant of OH removes SiGeOx.In embodiment In, epitaxial layer 340 is SiGe and epitaxial layer 306 is silicon, so as to selective removal epitaxial layer 340.
Method 100 then advancees to frame 116, wherein deposition of spacer layer on substrate.Spacer layers can be formed in Conformal dielectric layer on substrate.Spacer layers can form spacer element on the side of gate structure.Spacer layers The gap formed as described in frame 114 due to the removal of epitaxial layer can be filled.Referring to Fig.1 1, spacer layers 1102 are arranged Gap (the gap of Figure 10 between each epitaxial layer on substrate 202, in the source/drain regions including filling fin element 402 1002)。
Spacer layers 1102 may include such as silica, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, oxidation of coal The dielectric material of silicon, SiOCN film and/or their combination.In some embodiments, spacer layers 1102 include multilayer, such as Master space part wall, laying etc..It, can be by using such as CVD technique, sub-atmospheric pressure CVD (SACVD) work by way of example Skill, flowable CVD technique, ALD technique, the technique of PVD and/or other suitable techniques are sunk above gate stack 902 Dielectric material is accumulated to form spacer layers 1102.In a particular embodiment, it can be etch-back after deposition (for example, anisotropy Etching) dielectric material.In some embodiments, before forming spacer layers 1102, it is possible to implement ion implantation technology with Drain electrode (LDD) component being lightly doped is formed in semiconductor devices 200.
In some embodiments, the example of 2A and Figure 12 B can be etched back after forming spacer layers 1102 referring to Fig.1 Carve spacer layers 1102 with expose in fin element 402 adjacent to but the part that is not covered by gate structure 902 (for example, source/drain Polar region).Spacer layer material can be retained on the side wall of gate structure 902 to form spacer element.In some embodiments In, the etch-back of spacer layers 1102 may include wet etching process, dry etching process, multi-step etch process and/or they Combination.Although as illustrated in figs. 12 a and 12b, can be stacked from the top surface of exposed extension stack 302 and the extension of exposure The lateral surfaces of part 302 remove spacer layers 1102, but extension of the spacer layers 1102 still in source/drain regions stacks Between each epitaxial layer 306 of part.Figure 12 B shows the partial cross-sectional view corresponding to Figure 12 A.Spacer between epitaxial layer 306 The thickness of layer 1102 can be in about 2nm between 6nm.
Method 100 then advancees to frame 118, wherein forms source/drain component.It can be by implementing epitaxial growth work Skill forms source/drain component, the epitaxial growth technology provide be retained in covering (cladding) epitaxial layer the source electrode of fin/ The epitaxial material of the part of drain electrode.3 example referring to Fig.1, on substrate 202 and adjacent to gate structure 902 and and grid In the relevant fin 402 of pole structure 902/above form source/drain component 1302.Source/drain component 1302 includes by sudden and violent Epitaxial growth of semiconductor material is on the epitaxial layer 306 of dew come the material 1302A that is formed.It is, material 1302A be formed in it is neighbouring Around the nano wire (for example, epitaxial layer 306) of grid；This can be referred to as the formation " coating " around nano wire.
In various embodiments, the semiconductor material 1302A of growth may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP or other suitable materials.In some embodiments, material 1302A can be in situ mix during epitaxy technique Miscellaneous.For example, in some embodiments, epitaxial grown material 1302A can be doped with boron.In some embodiments, extension is raw Long material 1302A can form Si:C source/drain component doped with carbon, and Si:P source/drain can be formed doped with phosphorus Pole component or doped carbon and phosphorus are to form SiCP source/drain component.In embodiment, epitaxial layer 306 is that silicon and extension are raw Long material 1302A is also silicon.In some embodiments, layer 306 and 1302A may include similar material, but by differently Doping.In other embodiments, epitaxial layer 306 includes the first semiconductor material, and epitaxial grown material 1302A includes being different from the Second semiconductor material of semiconductor material.
In some embodiments, epitaxial grown material 1302A is not adulterated in situ, but for example implement injection technology with Doped epitaxial growth material 1302A.As described above, the separation layer 502 being retained in below gate stack 902 can stop it is potential Undesirable diffusion.
Therefore, source/drain component 1302 relevant to grid 902 includes epitaxial material 306 and/or epitaxial grown material 1302A.It should be noted that these components can be formed in the case where not making fin 402 recessed.Dielectric from spacer layers 1102 Material is between epitaxial material 306.Each epitaxial material 306 (for example, nano wire) all extends in channel region, therefore forms more ditches Road, more source/drain regions device.The thickness of spacer layers 1102 in source/drain regions between epitaxial material 306 can To be about 2nm to 6nm.
Method 100 then advancees to frame 120, wherein forms interlayer (ILD) dielectric layer.In a particular embodiment, it is being formed After ILD layer, remove dummy grid stack (as described below).4 example referring to Fig.1, in the embodiment of frame 120, in substrate 202 tops form ILD layer 1402.In some embodiments, it before forming ILD layer 1402, is also formed and is connect above substrate 202 It touches etching stopping layer (CESL).In some instances, CESL includes silicon nitride layer, silicon oxide layer, silicon oxynitride layer and/or ability Other materials known to domain.CESL layers can pass through plasma enhanced chemical vapor deposition (PECVD) technique and/or other conjunctions Suitable deposition or oxidation technology is formed.CESL layer 1702 is shown in FIG. 17.In some embodiments, in epitaxial grown material CESL layer 1702 is deposited after 1302A and before the formation of ILD layer 1402.In some embodiments, ILD layer 1402 includes all As ethyl orthosilicate (TEOS) oxide, undoped silicate or the silica of doping (such as borosilicate glass (BPSG), Fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG)) and/or other suitable dielectric materials Material.ILD layer 1402 can be deposited by pecvd process or other suitable deposition techniques.In some embodiments, it is being formed After ILD layer 1402, semiconductor devices 200 can undergo high fever budget process with ILD layer of annealing.As described above, pre- in high fever During calculating technique, insulating layer 502 can stop APT dopant is potential out of substrate area to diffuse to device channel region.
In some instances, after depositing ILD (and/or CESL), it is possible to implement flatening process is to expose grid pile The top surface of overlapping piece 902.For example, flatening process includes chemically mechanical polishing (CMP) technique, which removes positions in ILD layer 1402 In 902 part above of gate stack (and CESL layers, if there is) and the top surface of planarization semiconductor devices 200. In addition, CMP process can remove the hard mask 906 above gate stack 902 to expose electrode layer 904, such as polycrystalline Silicon electrode layer.Hereafter, in some embodiments, the remainder for the gate stack 902 being previously formed can be removed from substrate Part (for example, dielectric layer 802 and electrode layer 904).In some embodiments, electrode layer 904 can be removed, but does not remove dielectric Layer (for example, 802).Electrode layer 904 (or electrode layer 904 and dielectric layer 802) is removed from gate stack 902 to generate such as Figure 14 institute The groove 1404 shown.
As described below, final gate structure (e.g., including high k dielectric layer and metal gate electrode) can be then formed in In groove 1404.It can be used and select the selection etch process of wet etching, selection dry ecthing or their combination such as to implement The removal of dummy grid stacked components.
Method 100 then advancees to frame 122, wherein the epitaxial layer in the channel region of selective removal device.In embodiment In, it can remove by removing in the groove that pseudo- gate electrode is formed (for example, grid knot will be formed thereon or above it in fin The region of structure or channel region) fin element in selective epitaxy layer.5 example referring to Fig.1, from the channel region of substrate 202 and Epitaxial layers 304 are removed in groove 1404.In some embodiments, epitaxial layers 304 are gone by selective wet etching.In some realities It applies in example, selective wet etching includes HF.In embodiment, epitaxial layer 304 is SiGe and epitaxial layer 306 is silicon, so as to With selective removal SiGe epitaxial layer 304.It should be noted that (for example, Figure 15) during the mid-term processing of frame 122, in channel region In neighbouring nano wire between provide gap 1502 (for example, gap 1502 between epitaxial layer 306).Gap 1502 can be filled Full ambient environmental conditions gas (for example, air, nitrogen etc.).
It should be noted that as depicted in the figures, epitaxial layer 306 (for example, nano wire) has the shape (example of basic sphering Such as, cylindrical).Epitaxial layer 306 (for example, nano wire) has rough bar shaped (for example, cylindrical) in source drain area.? In some embodiments, this shape difference of epitaxial layer 306 is due to caused by the quantity and property of the processing in each area.Example Such as, circle can be formed in channel region, pseudo- oxide removal and/or high k dielectric depositing operation.In some embodiments, each Shape in area is substantially similar.
Method 100 then advancees to frame 124, wherein forms gate structure.Gate structure can be multi-gated transistor Grid.Final gate structure can be high K/ metal gate stacks part, however, other compositions are possible.In some implementations In example, gate structure forms grid relevant to more channel regions (being provided by multiple nano wires in channel region).
6 example referring to Fig.1, in the embodiment of frame 124, high K/ metal gate stacks part 1602 is formed in device 200 Groove 1404 in.In various embodiments, high K/ metal gate stacks part 1602 includes boundary layer, is formed in above boundary layer High-k gate dielectric layer 1604 and/or be formed in the high k dielectric layer 1606 of the top of high-k gate dielectric layer 1604.As used herein With description, high-k dielectrics include the high dielectric constant with the dielectric constant for being greater than thermal oxidation silicon (about 3.9).In height The metal layer used in K/ metal gate stacks part includes metal, metal alloy or metal silicide.Extraly, high K/ metal gate The formation of pole stack may include deposition to form each grid material, one or more layings, and one or more CMP process planarizes the top surface of semiconductor devices 200 to remove excessive material.
In some embodiments, the boundary layer of gate stack 1602 may include such as silica (SiO2)、HfSiO Or the dielectric material of silicon oxynitride (SiON).It can be heavy by chemical oxidation, thermal oxide, atomic layer deposition (ALD), chemical vapor (CVD) and/or other suitable methods are accumulated to form boundary layer.The gate dielectric 1604 of gate stack 1602 may include Such as hafnium oxide (HfO2) high k dielectric layer.Optionally, the gate dielectric 1604 of gate stack 1602 may include such as TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3 (BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、 Si3N4, other high k dielectric layers of nitrogen oxides (SiON), their combination or other and suitable material.High-k gate dielectric layer 1604 can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation and/or other suitable methods.In Figure 16, figure 17, the gate dielectric 1604 of gate stack 1602 is shown in Figure 18 and Figure 19.The gold of high K/ metal gate stacks part 1602 Belonging to layer may include single layer or multilayered structure, and such as metal layer (has selective work content to improve the work content gold of device performance Belong to layer), the various combinations of laying, wetting layer, adhesive layer, metal alloy or metal silicide.By way of example, grid The metal layer of stack 1602 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or their combination.In various embodiments, gate stack The metal layer of part 1602 can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable technique classes.In addition, grid The metal layer of stack 1602 could be separately formed so that for N-FET and P-FET transistor, (different metals is can be used in it Layer).In various embodiments, it is possible to implement CMP process to remove excessive metal from the metal layer of gate stack 1602, To provide the surface of the substantially flat of the metal layer of grid overlapping piece 1602.The metal layer 1606 of gate stack 1602 Figure 16, It is shown in Figure 17, Figure 18.
In addition, metal layer can provide N-type or p-type work function, the grid electricity of transistor (for example, FINFET) may be used as Pole, and at least some embodiments, the metal layer of gate stack 1602 may include polysilicon layer.
Device 200 may be embodied as loopful grid (GAA) device, that is, gate structure 1602 is formed in nano wire (for example, outer Prolong layer 306) more sides.Isometric view and Figure 17 (transversal A), Figure 18 of the multigate device 200 in Figure 16 (pass through gate stack The transversal C of part 1602) and Figure 19 (passing through the transversal B of source/drain) in show in corresponding sectional view.For the ease of with reference to figure 17, Figure 18 and Figure 19 removes ILD layer 1402.As shown in Figure 17 and Figure 18, gate dielectric 1604 is arranged in 306 (example of epitaxial layer Such as, nano wire) below.However, in other embodiments, the other parts (for example, gate electrode 1606) of gate structure 1602 It can be set below epitaxial layer 306.In some embodiments, device 200 can be its grid and be formed in channel region at least The FINFET device of (for example, top surface and two side walls) and/or other configurations known in the art on two sides.Device in Figure 19 200 show source/drain component 1302, and source/drain component 1302, which has, to be arranged in epitaxial layer 306 (for example, nano wire) The coating 1302A of epitaxial growth on multi-surface, while dielectric 1102 is arranged between each epitaxial layer 306.
Semiconductor devices 200, which can be undergone, further to be handled to form all parts known in the art and region.Example Such as, it may include one or more that subsequent processing, which can form on substrate 202 and be configured as connection all parts to be formed, Contact opening, contact metal and each contact/through-hole/line and multilayer interconnection of the functional circuit of multigate device Component (for example, metal layer and interlayer dielectric).In further example, multilayer interconnection component may include such as through-hole or The horizontal interconnection piece of the vertical interconnection of contact and such as metal wire.Each interconnecting member can using including copper, tungsten and/ Or the different conductive materials of silicide.In an example, it inlays and/or dual-damascene technics is used to form cupric (copper Related multilayer interconnection structure).Furthermore, it is possible to before method 100, device and additional processing step is executed later, and And according to the different embodiments of method 100, above-mentioned some processing steps can be replaced or eliminated.
Figure 20 shows the semiconductor making method 2000 including manufacturing multigate device.Method 2000 can be substantially Similar to the method 100 of Fig. 1, other than some differences being highlighted below.However, unless explicitly stated otherwise herein, above by reference to side The similar technique of 100 descriptions is equally applicable in herein.
Figure 21 is the semiconductor devices in each stage of 0 method according to fig. 2 to Figure 29, Figure 30 A and Figure 31 to Figure 34 The isometric view of 2100 embodiment.Figure 30 B, Figure 35, Figure 36 and Figure 37 are each stages of according to fig. 20 method 2000 The sectional view for corresponding respectively to isometric view listed above of the embodiment of semiconductor devices 2100.
Method 2000 starts from frame 2002, provides substrate.Frame 2002 is substantially similar to the frame 102 of the above method 100.Reference The example of Figure 21 provides substrate 202 in the embodiment of frame 2002.Substrate 202 may be substantially similar to such as above by reference to figure 2 descriptions.Also above by reference to as described in Fig. 1 and Fig. 2, implemented APT injection 204.
Referring to Figure 20, method 2000 is carried out to frame 2004, wherein grows one or more epitaxial layers on substrate.Reference The example of Figure 22 forms extension stack 2202 in the embodiment of frame 2004 above the substrate 202 by APT injection.Outside Prolonging stack 2202 includes the epitaxial layer 304 with the first component, and the epitaxial layer 306 with the second component is between each epitaxial layer Between 304.First and second components can be different.In embodiment, epitaxial layer 304 is SiGe, and epitaxial layer 306 is Silicon.However, other embodiments are possible, it include providing that there is different oxidations rate and/or etch-rate in these embodiments The first component and the second component.In various embodiments, epitaxial layer 304 has the first oxidation rate, and epitaxial layer 306 has Less than the second oxidation rate of the first oxidation rate.For example, in some embodiments, epitaxial layer 304 is SiGe and epitaxial layer 306 It is Si, the oxidation rate of Si is less than the oxidation rate of SiGe.During subsequent oxidation, as discussed below, epitaxial layer 304 Each section can be fully oxidized, however epitaxial layer 306 can be it is not oxidized or be only in some embodiments slightly by It aoxidizes (for example, side wall).
Therefore, extension stack 2202 (and epitaxial layer 304,306) and the frame 104 and Fig. 3 above by reference to method 100 It is similar described in extension stack 302, in addition to extension stack 2202 does not include the extension being substantially formed in isolated area Layer (compared to epitaxial layer 304A).As a result, each layer 304 of extension stack 2202 have basically the same thickness (for example, In 10%).In embodiment, each epitaxial layer 304 of extension stack 2202 all has about 2 to 6nm thickness.Implementing In example, each epitaxial layer 306 of extension stack 2202 all has about 6 to 12nm thickness.As described in more detail below, outside Prolonging layer 306 may be used as the channel region of the multigate device subsequently formed, and based on device performance consideration come selective epitaxy layer 306 thickness.Epitaxial layer 304 can be used for limiting the gap between the neighbouring channel region of multigate device subsequently formed with And based on device performance consideration come the thickness of selective epitaxy layer 304.
It should be noted that three layers of epitaxial layer 304 being shown in FIG. 22 in extension stack 2202 and three layer 306, this is only For illustration purposes but it is not intended to and limits the present invention within the scope of claim specifically states.It should be recognized that Any number of epitaxial layer can be formed in extension stack 2202；The number of plies depends on the desired number of the channel of device 2100 Mesh.In some embodiments, the number of epitaxial layer 306 is between 2 and 10.It also, can be in extension heap as shown in the example of Figure 22 Hard mask (HM) layer 308, HM layer 308 and substantially one of the discussion of HM layer 308 above by reference to Fig. 3 are formed above overlapping piece 2202 It causes.
Method 2000 then advancees to frame 2006, wherein forming fin element.Referring to the example of Figure 23, in the implementation of frame 2006 In example, the multiple fin elements 402 extended from substrate 202 are formed.In various embodiments, each fin element 402 includes by serving as a contrast The part of substrate portions, each epitaxial layer (including epitaxial layer 304 and 306) in extension stack 302 that bottom 202 is formed and The part HM from HM layer 308.May be substantially similar to be discussed above by reference to the frame 106 and/or Fig. 4 of method 100 comes Form fin element 402.
Method 2000 then advancees to frame 2008, wherein forming shallow trench isolation (STI) component between fin element.Reference The example of Figure 24 and Figure 25, then STI component 602, which is arranged between fin 402, makes it recessed.STI component 602 can be with the above ginseng Frame 110 and/or Fig. 6 according to method 100 are discussed similar with the example of Fig. 7.Referring to the example of Figure 25, keep STI component 602 recessed Into to be formed in the fin extended on STI component 602 402.In some embodiments, recessed technique may include dry ecthing work Skill, wet etching process and/or their combination.In some embodiments, recessed depth is controlled (for example, by control etching Time) to form the desired height ' H ' on the top of the exposure of fin element 402.Highly ' H ' exposure extension stack 302 is each Layer.
Method 2000 then advancees to frame 2010, wherein forms the sacrificial layer including dummy gate structure.Frame 2010 can be with base The frame 112 of method 100 is similar in sheet.Referring to Figure 26 and Figure 27, dielectric layer 802 and gate structure are formed on device 2100 902 (for example, dummy gate structures).Dielectric layer 802 and/or gate structure 902 can be substantially and above by reference to frame 112 and Fig. 8 It is similar with being discussed for Fig. 9.
Method 2000 then advancees to frame 2012, can be from the fin region of adjacent gate stack (also referred to as fin Source/drain regions, because it is that fin will be subsequently formed as the portion of source/drain component relevant to multigate device 2100 Point) removal extension stack selective epitaxy layer.As shown in Figure 28, the source/drain of fin 402 is removed from substrate 202 Epitaxial layer 304 in polar region, to provide gap 1002 at the position of epitaxial layer 304.Gap 1002 can be filled with surrounding ring Border gas is (for example, air, N2).Frame 2012 can respectively with discussed above by reference to Fig. 1 and Figure 10 it is substantially similar.
Method 2000 then advancees to frame 2014, on substrate deposition of spacer layer.Frame 2014 may be substantially similar to Above by reference to the frame 116 of Fig. 1 and Figure 11 method 100 described.Spacer layers can be including Jie discussed above including silicon Any dielectric material of electric material.Exemplary Figure 29 shows the spacer layers for being arranged on fin 402 and filling gap 1002 1102.It in some embodiments, can be with etch-back after forming spacer layers 1102 referring to the example of Figure 30 A and Figure 30 B Spacer layers 1102 with expose in fin element 402 adjacent to but the part that is not covered by gate structure 902 (for example, source/drain Area).Exemplary diagram 30A and Figure 30 B can with discussed above by reference to Figure 12 A and Figure 12 B it is substantially similar.Such as the above institute It states, as shown in Figure 30 A and Figure 30 B, although spacer layers 1102 can top surface from extension stack 2202 and extension stack 2202 lateral surfaces removal, but extension stack 302 of the spacer layers 1102 still in source/drain regions is each outer Prolong between layer 306.Figure 30 B shows the partial cross-sectional view corresponding to Figure 30 A.Spacer layers 1102 between each epitaxial layer 306 Thickness can be in about 2nm between 6nm.In addition, as shown in fig. 30 a, after etch-back spacer layers 1102, can make STI component 602 is further slight to be recessed, so that the top surface of STI component 602 is lower than the epitaxial layer 304 of bottommost (for example, most The SiGe layer of bottom) bottom surface or bottom side alignment substantially with bottommost epitaxial layer 304.
Method 2000 then advancees to frame 2016, wherein forming source/drain component.Frame 2016 is substantially similar to above The frame 118 of the method 100 described referring to Fig.1.As set forth above, it is possible to form source/drain by implementing epitaxial growth technology Component, the epitaxial growth technology provide the extension of the expose portion of the epitaxial layer in the source/drain of covering (cladding) fin Material.For example, epitaxial material can cover in source/drain regions in addition to dielectric spacer material setting is in epitaxial layer (or nanometer Line) between position outside epitaxial layer or nano wire.Referring to the example of Figure 31, in adjacent gate structures 902 on substrate 202 Source/drain component 1302 is formed on fin 402.Source/drain component 1302 includes by the adjacent gate knot in epitaxial layer 306 Epitaxial growth of semiconductor material on the region of structure 902 and the material 1302A formed.It is, material 1302A is formed in neighbouring grid Around the nano wire (for example, epitaxial layer 306) of pole；This can be referred to as the formation " coating " around nano wire.Including extension The source/drain component 1302 of material 1302A can with above by reference to the similar of Figure 13 discussion.
Method 2000 then advancees to frame 2018, forms interlayer (ILD) dielectric layer.In some embodiments, it is also formed CESL layers.In some embodiments, then gate structure can be removed from substrate.Frame 2018 is substantially similar to above by reference to figure The frame 120 of the method 100 of the example description of 1 and Figure 14.Referring to the example of Figure 32, ILD layer 1402 is formed above substrate 202. As shown in Figure 32, electrode layer 904 (or electrode layer 904 and dielectric layer 802) is removed from gate stack 902 generate groove 1404.Although the middle process that Figure 32 shows the setting dielectric layer 802 in groove 1404 may be used also in other embodiments Remove dielectric layer 802.
Method 2000 then advancees to frame 2020, provides the epitaxial layer being optionally removed in the channel region of device.One In a little embodiments, the selected epitaxial layer in the region (on the area or top will form gate structure) of fin is removed.Frame 2020 It is substantially similar to the frame 122 of the method 100 of Fig. 1 and/or the example of Figure 15.Referring to the example of Figure 33, out of groove 1404 Epitaxial layers 304 are removed at the channel region of substrate 202.As described above, in embodiment, epitaxial layer 304 is SiGe and epitaxial layer 306 It is silicon, so as to selective removal SiGe epitaxial layer 304.It should be noted that during frame 2020 (for example, Figure 33), channel region In neighbouring nano wire between provide gap 1502 (for example, gap 1502 between epitaxial layer 306).
Method 2000 then advancees to frame 2022, forms gate structure.Frame 2022 is substantially similar to above by reference to Fig. 1 And/or the frame 124 of the method 100 of Fig. 1 of the example description of Figure 16, Figure 17, Figure 18 and Figure 19.Referring to the example of Figure 34, in frame In 2022 embodiment, high K/ metal gate stacks part 1602 is formed in the groove 1404 of device 2100.Gate stack 1602 can substantially with it is discussed above similar.
Device 2100 may be used as multigate device (including loopful grid (GAA) device, that is, 1602 shape of gate structure as a result, At on more sides of nano wire (epitaxial layer 304)).Multigate device 2100 Figure 34 isometric view and Figure 35 (transversal A), Show in respective cross-section figure in Figure 36 (across the transversal C of gate structure 1602) and Figure 37 (across the transversal B of source/drain) Out.In Figure 35, Figure 36 and Figure 37, for ease of reference, ILD layer 1402 is removed.As shown in Figure 35 and Figure 36, gate dielectric 1604 are arranged in epitaxial layer 306 (for example, nano wire) in channel region below.However, in other embodiments, gate structure 1602 other parts (for example, gate electrode 1606) also can be set below the epitaxial layer 306 in channel region.In some implementations In example, device 2100 can be the FINFET that its grid is formed on at least two sides (for example, top surface and two sidewalls) of channel region Device and/or other configurations known in the art.
Device 2100 is different from device 200, for example, the isolated area being present in device 200 is omitted (referring to separation layer 502).This can provide in process and in terms of the time advantage.In some embodiments, the performance consideration of multigate device makes Separation layer is not required.Also as being referred to method 200 and device above by reference to described in method 100 and exemplary means 200 The implementation of part 2100 is further processed.
Being shown in Figure 38 includes the semiconductor making method 3800 for manufacturing multigate device.Method 3800 can be basic The method 2000 of the upper method 100 for being similar to Fig. 1 and/or Figure 20, other than the following some differences emphasized.Therefore, unless separately There is statement, the description above with reference to method 100 and/or the similar technique of the offer of method 2000 is equally applicable herein.Figure 38 Show the parallel for manufacturing two kinds of device (N-shaped and p-type transistor can be formed on the same substrate).
Figure 21, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26 and Figure 27 are the embodiments of semiconductor devices 2100 in method 3800 The isometric view of different phase (these figures can simultaneously and/or substantially similarly be applied to the place of two types device Reason).Figure 27, Figure 39 A, Figure 39 B, Figure 40 A, Figure 40 B, Figure 41 A, Figure 41 B, Figure 42 A, Figure 42 B, Figure 43 A, Figure 43 B, Figure 44 A, Figure 44 B, Figure 45 A, Figure 45 B, Figure 46 A, Figure 46 B, Figure 47 A and Figure 47 B show each stage of the method 3800 corresponding to Figure 38 Follow-up phase.Figure 48 A, Figure 48 B, Figure 49 A, Figure 49 B, Figure 50 A and Figure 50 B are to correspond respectively to isometric view listed above Sectional view.It should be noted that the figure of label " A ", for example, Figure 39 A indicates the device of the first kind (for example, p-type field effect transistor Pipe) and the figure of " B " is marked to indicate the device (for example, N-shaped FET) in the Second Type of respective stage.For example, by " A " chart Each type of device that is showing and passing through the expression of " B " figure can be formed on same substrate (for example, substrate 202).One or more A isolated part (for example, STI) can be between the device of the first kind and the device of Second Type.
Method 3800 starts from frame 3802, provides substrate.Frame 3802 is substantially similar to above by reference to Figure 20 and Figure 21 description Method 2000 frame 2002, the example that Figure 20 and Figure 21 are to provide substrate 202.Method 3800 then advancees to frame 3804, In, one or more epitaxial layers are grown on substrate.Frame 3804 is substantially similar to the frame 2004 described above by reference to Figure 20.Figure 22 are the example of extension stack 2202 and form HM layer 308 above substrate 202.
Method 3800 then advancees to frame 3806, wherein forms fin element.Frame 3806 is substantially similar to above by reference to figure The frame 2006 of the method 2000 of 20 descriptions.Figure 23 is the similar example of the multiple fin elements 402 extended from substrate 202.Method 3800 then advance to frame 3808, and shallow trench isolation (STI) component is formed between fin element.Frame 3808 be substantially similar to The frame 2008 of the upper method 2000 referring to Figure 20 description.Figure 24 and Figure 25 is to be arranged between fin 402 and then make it recessed STI component 602 identical example.
Method 3800 then advancees to frame 3806, wherein sacrificial layer or puppet including dummy gate structure is formed on the substrate Layer.In embodiment, pseudo- dielectric (for example, oxide) and dummy gate structure are formed on fin.Frame 3810 is substantially similar to The frame 2020 of method 2000.Figure 26 and Figure 27 be exemplary and including formed dielectric layer 802 and gate structure 902 (for example, Dummy gate structure).
Method 3800 then advancees to frame 3812, and oxidation is located at the selected outer of the extension stack on the device of Second Type Prolong layer, while the fin of the device by the masking layer protection first kind.In embodiment, it is covered by the masking layer of such as hard mask Fin or fin region of the lid corresponding to PFET.In some embodiments, masking layer includes hard mask, and hard mask has oxide skin(coating) (for example, may include SiO2Oxygen pad layer) and/or nitride layer (for example, may include Si3N4Pad nitrogen layer).In some realities It applies in example, masking layer includes the oxide of thermal growth oxide, CVD deposition oxide and/or ALD deposition.In some embodiments In, masking layer includes the nitride layer by CVD or other suitable technology depositions.
While protecting the fin of device of the first kind, implement oxidation technology, so that oxidation (for example, complete oxidation) the The selected epitaxial layer of the extension stack of the device of two types.In some embodiments, the extension of the device of Second Type stacks The SiGe epitaxial layer of part is oxidized (for example, complete oxidation).The substrate of device including the first and second types can be subjected to wet Oxidation technology, dry oxidation process or their combination.In at least some embodiments, using vapor or steam as oxidant, Device is exposed to wet oxidation process.
Referring to the example of Figure 39 A of frame 3812, the device (for example, PFET) of the first kind has what is be disposed thereon to cover firmly Mold layer 3902.As shown in Figure 39 B, while HM layer 3902 is arranged on the device of the first kind, to the device (example of Second Type Such as, NFET) fin source/drain regions epitaxial layer 304 implement oxidation technology.Oxidation technology provides oxide layer 3904.One In a little embodiments, the material of epitaxial layer 304,306 has different oxidations rate to allow selective oxidation processes.For example, In some embodiments, epitaxial layer 304 is SiGe, and epitaxial layer 306 is silicon.SiGe can be with many rates faster than Si by oxygen Change.Figure 39 A is reused as example, in embodiment, epitaxial layer 304 is SiGe to be produced as the oxide layer of SiGeOx 3904.In some embodiments, epitaxial layer 306 is not oxidized.
In some embodiments, epitaxial layer 304 is oxidized completely to form oxide layer 3904.In some embodiments, example Such as, as shown in Figure 22 to Figure 27, the thickness of the epitaxial layer 304 in source/drain regions is about 2 between 6nm.Once extension Layer 304 is oxidized, this layer can be extended to provide the thickness of oxide layer 3904, for example, in some embodiments, oxide layer 3904 Thickness about 5 between 25nm.Such extension can provide the epitaxial layer 306 being applied in the source drain area of fin 402 Stress (for example, the bending for leading to neighbouring layer).This shows in the sectional view of Figure 48 B.In Figure 48 B, due to oxide layer 3904 thickness increases, thus epitaxial layer 306 be no longer between channel region (under grid) and source/drain regions it is coplanar or Total straight line.It should be noted that epitaxial layer 306 keeps substantially consistent thickness (example between source/drain regions and channel region Such as, between 6 and 12nm).This can provide the enhanced strain of device, this can be such as NMOS device beneficial.Such as Upper described, in some embodiments, Second Type device (being shown by figure " B ") is NFET.
In some embodiments, frame 3810 continues to provide the removal for the hard mask layer being located on the device of the first kind. Using the example of Figure 40 A/40B, hard mask layer 3902 is removed from substrate 202.
Method 3800 then advancees to frame 3814, the fin element source from the fin of the device (for example, PFET) of the first kind The selected epitaxial layer in extension stack is removed at pole/drain region.As shown in Figure 41 A/41B, the device of the first kind is had been removed Epitaxial layer 304 in the source/drain regions of the fin 402 of part.Second Type device (Figure 41 B), which is kept substantially, to be had not been changed.Due to The epitaxial layer 304 of exposure in Second Type device has been oxidized to form oxide layer 3904, therefore, etches to epitaxial layer 304 It can have selectivity, lead to the removal in the device epitaxial layers 304 of the first kind.In other embodiments, implement to be suitble to Patterning and masking steps.Figure 41 A shows the gap 1002 at the position of the epitaxial layer 304 (Figure 40) of removal.Gap 1002 can be filled with surrounding environmental gases (for example, air, N2).Frame 3814 and gap 1002 are analogous respectively to above by reference to figure Described in 1 and Figure 10.
Method 3800 then advancees to frame 3816, on substrate with the fin disposed thereon spacer of two kinds of device Layer.Figure 42 A/42B shows the spacer layers 1102 being arranged on fin 402.For the device of the first kind, Figure 42 A is shown Spacer layers 1102 are formed on fin, including are formed in gap 1002.Frame 3816 is substantially similar to above by reference to Fig. 1 and figure The frame 116 of 11 method 100 and/or the frame 2014 for being substantially similar to the method 2000 above by reference to Figure 20.In some implementations It, can be with etch-back spacer layers 1102 with exposure after forming spacer layers 1102 referring to the example of Figure 42 A/42B in example Fin element 402 adjacent to but the part (for example, source/drain regions) that is not covered by gate structure 902.The example of Figure 43 A can It is discussed with being substantially similar to above by reference to 12A and Figure 12 B.As described above, although can be from extension stack 2202 The lateral surfaces of top surface and extension stack 2202 remove spacer layers 1102, but spacer layers 1102 are still between the first kind Device source/drain regions in extension stack 2202 epitaxial layer 306 between.Positioned at the fin member of the device of the first kind The thickness of the spacer layers 1102 between epitaxial layer 306 in part 402 can be in about 2nm between 6nm.Referring concurrently to second The device of type, Figure 43 B show the side wall that etch-back spacer layers 1102 make spacer layers 1102 be retained in gate structure 902 On, to form spacer element.
Method 3800 then advancees to frame 3818, and source/drain portion is formed in the source/drain regions of each types of devices Part.Frame 3818 is substantially similar to above by reference to the frame 2016 of method 2000 of Figure 20 and Figure 31 description and/or substantially similar In the frame 118 of the method 100 above by reference to Fig. 1 and Figure 13 description.As set forth above, it is possible to by implementing epitaxial growth technology come shape At source/drain component, which provides part of covering (cladding) epitaxial layer in the source/drain of fin Epitaxial material.The epitaxial material grown in frame 3818 and the extension material for making it be grown in the layer (for example, epitaxial layer 306) of top Material can be identical or different.Referring to the example of Figure 44 A/44B, for each type of device, source/drain component 4402 and 4404 It is formed on the fin element 402 of adjacent gate stack 902.
Referring to Figure 44 A example, source/drain component 4402 include by epitaxial layer 306 adjacent to gate structure Epitaxial growth of semiconductor material layer on 902 region and the material 4402A formed.It is, material 4402A is formed in neighbouring grid Around the nano wire (for example, epitaxial layer 306) of pole；This can be referred to as the formation " coating " around nano wire.Including extension The source/drain component 4402 of material 4402A can be with the basic class of source/drain material 1302A above by reference to Figure 13 discussion Seemingly.Epitaxial material 4402A can be suitably doped to provide the source/drain component of first kind device (for example, PFET).
Referring to Figure 44 B example, source/drain component 4404 include by epitaxial layer 306 adjacent to gate structure Epitaxial growth of semiconductor material layer on 902 region and the material 4404A formed.It is, material 4404A is formed in neighbouring grid Around the nano wire (for example, epitaxial layer 306) of pole；This can be referred to as the formation " coating " around nano wire.Including extension The source/drain component of material 4404A can be substantially similar with the source/drain material 1302A above by reference to Figure 13 discussion.With Combine relevant type of device (N-shaped, p-type) there can be component appropriate or suitably adulterate in the material of 4404A and 4402A. Therefore, in embodiment, material 4404A and 4402A is different at least one of composition and doping.For example, one In a little embodiments, epitaxial material 4402A provides the source/drain material for being suitable for PFET device；Epitaxial material 4404A provides suitable Source/drain material for NFET device.Therefore, source/drain component 4402 and 4404 can be in identical or different work It is formed in skill.
Method 3800 then advancees to frame 3820, forms interlayer (ILD) dielectric layer.In some embodiments, it is also formed CESL layers.In some embodiments, then gate structure can be removed from substrate.Frame 3820 is substantially similar to above by reference to figure 1 and Figure 14 example description method 100 frame 120 and/or be substantially similar to Figure 20 method 2000 frame 2018 and figure 32 example.Referring to the example of Figure 45 A/45B, ILD layer 1402 is formed above substrate 202.As shown in Figure 45 A/45B, from Gate stack 902 removes electrode layer 904 (or electrode layer 904 and dielectric layer 802) and generates groove 1404.Although Figure 45 A shows The middle process of dielectric layer 802 is set in groove 1404 out, but in other embodiments, it also can remove dielectric layer 802.
Method 3800 then advancees to frame 3822, the epitaxial layer being optionally removed in the channel region of device.One In a little embodiments, by above its in fin element by the selected extension in the region (namely channel region) for forming gate structure Layer removal.It can implement the choosing of two kinds of device (including suitably sheltering element) simultaneously or in a separate step The removal of selecting property.Frame 3822 is substantially similar to the frame 2020 of the method 2000 of Figure 20 and/or the example of Figure 33, and/or substantially The example of frame 122 and/or Figure 15 similar to the method 100 above by reference to Fig. 1.Referring to the example of Figure 46 A/46B, for two kinds The device (N-shaped, p-type) of type, removes epitaxial layers 304 out of substrate 202 channel region and groove 1404.As described above, In embodiment, epitaxial layer 304 is SiGe and epitaxial layer 306 is silicon, so as to be optionally removed SiGe epitaxial layer 304.It answers When note that being mentioned between the neighbouring nano wire in channel region during the processing stage of frame 3822 (for example, Figure 46 A/46B) For gap 1502 (for example, gap 1502 between each epitaxial layer 306).
Method 3800 then advancees to frame 3824, forms one or more gate structures.The gate structure of formation can wrap Include high K/ metal gate stacks part.Frame 3824 may be substantially similar to above by reference to Figure 20, Figure 34, Figure 35, Figure 36 and Figure 37 It the frame 2022 of the method 2000 of description and/or may be substantially similar to above by reference to Fig. 1 and/or Figure 16, Figure 17, Figure 18 and figure The frame 124 of the method 100 of 19 example description.Since the device of each type provides relevant work function, it is accordingly used in first Types of devices and the gate structure that is formed composition, configuration, in terms of can be with the grid knot for Second Type device The difference of structure.It is formed in the groove 1404 of the device of the first kind in the embodiment of frame 3824 referring to the example of Figure 47 A Gate stack 4702.Gate stack 4702 may include boundary layer, gate dielectric (for example, high k) layer 4706 and gate electrode (for example, metal gates) 4710.Referring to the example of Figure 47 B, in the embodiment of frame 3824, in the groove of the device of Second Type Gate stack 4704 is formed in 1404.Gate stack 4704 may include boundary layer, gate dielectric (for example, high k) layer 4706 and gate electrode (for example, metal gates) 4712.Gate stack 4702 and 4704 may include different composition and/or It is formed during different process (technique for being used to form boundary layer, high-k layer and gate electrode).Gate stack 4702 is the first kind Device (for example, PFET) provides suitable work function.Gate stack 4704 is that Second Type device (for example, NFET) provides conjunction Suitable work function.For example, the metal layer of gate stack 4702 and 4704 may include identical or different component, including it is selected from By Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, its These components in the group of his suitable metal material or their combination composition.
Therefore, in some embodiments, method 3800 provides the device 4700 of the first kind.In some embodiments, device Part 4700 is PFET device.In some embodiments, method 3800 provides the device 4710 of Second Type.In some embodiments In, device 4710 is NFET device.Device 4700 and 4710 be can be provided on same substrate and be worked together to form collection At circuit.As described above, the advantage of method 3800 and/or some embodiments of device 4710 is by between the extension source of covering Oxide layer (referring to oxide layer 3904) between pole/drain electrode and the enhanced strain provided.
Device 4700 and/or 4710 may be used as loopful grid (GAA) device, the corresponding formation of gate structure 4702/4704 On more sides of nano wire (epitaxial layer 306) in channel region.Isometric view and figure of the multigate device 4700 in Figure 47 A The correspondence section of 48A (transversal A), Figure 49 A (passing through the transversal B of gate structure 4702), Figure 50 A (passing through the transversal C of source/drain) It is shown in the figure of face.Multigate device 4710 (passes through gate structure in isometric view and Figure 48 B (transversal A), Figure 49 A of Figure 47 B 4702 transversal B), show in the correspondence sectional view of Figure 50 B (passing through the transversal C of source/drain).For the ease of with reference to Figure 48 A, Figure 49 A and Figure 50 A remove ILD layer 1402.As shown in 48A, Figure 49 A, Figure 48 B and Figure 49 B, gate dielectric 4706 is arranged outside Prolong layer 306 (for example, nano wire) below.However, in other embodiments, other portions of corresponding gate structure 4702,4704 (for example, gate electrode 4710,4712) is divided also to can be set below epitaxial layer 306.In some embodiments, device 4700 and/ Or 4710 can be its grid be formed on at least two sides (for example, top and two sidewalls) of channel region FINFET device and/or Other configurations known in the art.Device 4700 and 4710 in Figure 50 A and Figure 50 B shows source/drain component 4402/4404 Coating 4402A, 4404A with the epitaxial growth being arranged on multiple surfaces of epitaxial layer 306 (for example, nano wire), together When dielectric material (being spacer 1102 and oxide layer 3904 respectively) insert between each epitaxial layer 306 of source/drain regions.
Semiconductor devices 4700 and 4710 can undergo further handle with formed all parts known in the art and Region.For example, subsequent processing can be formed on substrate 202, to be configured as connection all parts to be formed may include one Or the contact opening of the functional circuit of multiple multigate devices, contact metal and each contact/through hole and line and Multilayer interconnection component (for example, metal layer and interlayer dielectric).In some embodiments, 4700 He of interconnecting member electrical connection 4710.In another example multilayer interconnection part may include the vertical interconnection of such as through-hole or contact and the water of such as metal wire Flat interconnection piece.Each interconnecting member can be using each conductive material including copper, tungsten and/or silicon.In an example, it inlays And/or dual-damascene technics is used to form the multilayer interconnection structure of cupric.Furthermore, it is possible to before method 3800, device and later Additional processing step is executed, and can replace or omit above-mentioned some techniques according to the different embodiments of method 3800 and walk Suddenly.
Figure 51 shows the semiconductor making method 5100 including multigate device manufacture.Method 5100 can be substantially Similar to the method 3800 of the method 100 of Fig. 1, the method for Figure 20 2000 and/or Figure 38, in addition to some differences being highlighted below Outside.However, unless explicitly stated otherwise herein, the similar technique provided above by reference to side 100, method 2000 and/or method 3800 It is equally applicable in herein with element (being shown by common number designation).The similar above method 3800, method 5100 are shown The operation stage occurred while device for the first and second types.However, in some embodiments, method 5100 It provides and forms separation layer below the channel of fin and source/drain to stop undesirable diffusion in two kinds of device.
Fig. 2 to Fig. 9 is isometric view (this of the embodiment of the semiconductor devices in each stage of the method that is also applied for 5100 A little figures can be applied to occur simultaneously and/or the processing of substantially similar two types device).Fig. 9, Figure 52 A, Figure 52 B, figure 53A, Figure 53 B, Figure 54 A, Figure 54 B, Figure 55 B, Figure 55 A, Figure 56 A, Figure 56 B, Figure 57 A, Figure 57 B, Figure 58 A, Figure 58 B, Figure 59 A, Follow-up phase in Figure 59 B, Figure 60 A and Figure 60 B corresponds to each stage of the method 5100 of Figure 51.Figure 61 A, Figure 61 B, figure 62A, Figure 62 B, Figure 63 A and Figure 63 B correspond to the sectional view of corresponding isometric view listed above.These figures provide realization Method of the method 5100 for forming the introduction of the device of different type (for example, N-shaped and p-type) on a semiconductor substrate.It answers When again, it is to be noted that marking the figure (for example, device (for example, p-type FET) that Figure 52 A indicates the first kind) and label " B " of " A " Figure (for example, Figure 52 B) indicate respective stage Second Type device (for example, N-shaped FET).Such as it is indicated by " A " figure And by " B " figure indicate each type of device can be formed on same substrate (for example, substrate 202).It is one or more Isolated part (for example, STI) can be between the device of the first kind and the device of Second Type.
Method 5100 starts from frame 5202,5204,5206,5208,5210 and 5212, provides substrate and including forming extension The step of stack, fin element, oxide layer, shallow trench isolation component and dummy grid.These frames 5202,5204,5206,5208, Each of 5210 and 5212 are substantially similar to respectively above by reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and figure Frame 102, frame 104, frame 106, frame 108, frame 110 and the frame 112 of the method 100 of 9 descriptions.Although showing single exemplary Device, but the device of device and Second Type for the first kind, one or more processing in these frames can be simultaneously Implement on ground.
Insulation is formed in fin similar to above by reference to the frame 108 in method 100, method 5100 provides at frame 5108 Layer.The insulating layer for being shown as oxide layer 502 may be used as being previously injected to the diffusion barrier of the APT dopant in substrate 202 Layer, APT dopant can reside in the substrate 202 below oxide layer 502.Therefore, in various embodiments, For preventing the APT dopant in substrate portions 202 from diffusing to epitaxial layer 306 for example above, (it may be used as oxide layer 502 The channel region of the multigate device subsequently formed) in.It should be noted that oxide layer 502 is formed to be used for each type of device (N-shaped And p-type).However, in other embodiments, oxide layer 502 can be provided in only in individual devices type, and other type of device It can be processed in the case where no oxide layer (for example, the method 2000 as described in respectively referring to Figure 20 and Figure 38 above And/or shown in method 3800).In some embodiments, formed in the frame 108 of method 5100 oxide layer (referring to Such as Fig. 6) it is about between 5 and 15nm.
After method 5100 implements frame 5112, method 5100 is carried out to frame 5114, wherein aoxidizes the device of Second Type On extension stack selected epitaxial layer, while by masking layer protect the first kind device fin.In embodiment, lead to Cross fin or fin region of the masking layer covering corresponding to PFET, the selected epitaxial layer of the source/drain regions of simultaneous oxidation NFET.One In a little embodiments, masking layer includes hard mask, and hard mask has oxide skin(coating) (for example, may include SiO2Oxygen pad layer) and/ Or nitride layer is (for example, may include Si3N4Pad nitrogen layer).In some embodiments, masking layer include thermal growth oxide, The oxide of CVD deposition oxide and/or ALD deposition.In some embodiments, masking layer includes by CVD or other are suitable Technology deposition nitride layer.
While protecting the fin of device of the first kind, oxygen is implemented to the selected epitaxial layer of the fin of the device of Second Type Chemical industry skill.In some embodiments, the extension heap on the fin in the region of the device of (for example, complete oxidation) Second Type is aoxidized The SiGe epitaxial layer of overlapping piece.The substrate of device including the first and second types can be subjected to wet oxidation process, dry oxidation process Or their combination.In at least some embodiments, using vapor or steam as oxidant, device is exposed to wet oxygen chemical industry Skill.
Referring to the example of Figure 52 A, the device (for example, PFET) of the first kind has the hard mask layer being disposed thereon 3902.As shown in Figure 52 B, while HM layer 3902 is arranged on the device of the first kind, to the source electrode of the device of Second Type/ The epitaxial layer 304 of drain region implements oxidation technology.In some embodiments, the material of epitaxial layer 304,306 has different oxygen Change rate to allow selective oxidation processes.For example, in some embodiments, epitaxial layer 304 is SiGe, and epitaxial layer 306 It is Si.SiGe can be oxidized with the rate more faster than Si.Figure 52 A is reused as example, in embodiment, epitaxial layer 304 be SiGe to generate the oxide layer 3904 of SiGeOx.In some embodiments, epitaxial layer 306 is not oxidized.Institute as above It states, in some embodiments, the bottom epitaxial layer 304 in pre-oxidation Second Type device is to form oxide layer 502.Some In embodiment, the thickness that oxide layer 502 has is thicker than the thickness of oxide layer 3904.In some embodiments, oxide layer 502 and oxygen Changing layer 3904 is SiGeOx.
In embodiment, for example, as shown in Fig. 2 to Fig. 9, the thickness of the epitaxial layer 304 in source/drain regions is about 2 To between 6nm.Once the epitaxial layer 304 in the source/drain regions of Second Type device is oxidized, which can extend to provide In about 5 to the oxide layer 3904 between 15nm thickness.The extension can provide the source for being applied to the fin 402 of Second Type device The stress (for example, causing to be bent) of the epitaxial layer 306 of pole drain region.This shows in the sectional view of Figure 62 B, wherein epitaxial layer 306 be no longer coplanar or total straight line between channel region (under grid) and source/drain regions.It should be noted that epitaxial layer 306 keep substantially consistent thickness (for example, between 6 and 12nm) between source/drain regions and channel region.This can increase The strain of strong device, this can be such as NMOS device beneficial.Bottom, oxide layer 502 in the second device region can To be thicker than oxide layer 3904.In some embodiments, the thickness of the oxide layer 502 in the second device region is 5 between 25nm
In some embodiments, frame 5114 continues to remove the hard mask layer being located on first kind device.Use figure The example of 53A/53B removes hard mask layer 3902 from substrate 202.
Method 5100 then advancees to frame 5116, the adjacent gate from the fin of the device (for example, PFET) of the first kind The fin region of stack, that is, the selected epitaxial layer of source/drain regions removal extension stack.Frame 5116 be substantially similar to The frame of the method 2000 of the frame 3814 of the upper method 3800 referring to Figure 38 description, the frame 114 of the method 100 of Fig. 1 and/or Figure 20 2012.As shown in Figure 54 A/54B, from the source/drain regions of the fin 402 of the device of the removal first kind of substrate 202 Epitaxial layer 304 (Figure 54 A).Second Type device (Figure 54 B) is held essentially constant.Figure 54 A is shown positioned at (the figure of epitaxial layer 304 Gap 1002 at position 53A).It gap 1002 can be filled with surrounding environmental gases (for example, air, N2).In some realities It applies in example, the selectivity permission between epitaxial layer 304 and oxide layer 3904 (epitaxial layer 304 of oxidation) is gone from first kind device Epitaxial layers 304.
Method 5100 then advancees to frame 5118, on substrate, the fin disposed thereon spacer layers of two kinds of device. Frame 5100 is substantially similar to the frame 3816 of the method 3800 above by reference to Figure 38, the method described above by reference to Fig. 1 and Figure 11 100 frame 116 and/or the frame 2014 for being substantially similar to the method 2000 above by reference to Figure 20.Figure 55 A/55B shows setting Spacer layers 1102 on fin 402.For the device of the first kind, Figure 55 A shows spacer layers 1102 and is formed on fin, Including being filled in gap 1002.In some embodiments, referring to Figure 56 A/56B example, formed spacer layers 1102 it Afterwards, can with etch-back spacer layers 1102 with expose in fin element 402 adjacent to but the part that is not covered by gate structure 902 (for example, source/drain regions).What the example of Figure 56 A may be substantially similar to be discussed above with reference to Figure 12 A and Figure 12 B.Such as It is upper described, as shown in Figure 56 A, although can be gone from the top surface of extension stack 2202 and the lateral surfaces of extension stack 2202 Except spacer layers 1102, but extension stack of the spacer layers 1102 still in the source/drain of the device of the first kind Between 302 epitaxial layer 306 and on the side wall of grid.Extension in the fin element 402 of the device of the first kind The thickness of spacer layers 1102 between layer 306 can be in about 2nm between 6nm.Referring concurrently to the device of Second Type, figure 56B shows spacer layers 1102 and is etched back quarter so that spacer layers 1102 are retained on the side wall of gate structure 902, to be formed Spacer element.
Method 5100 then advancees to frame 5120, forms source/drain component.Frame 5120 be substantially similar to above by reference to Figure 38, Figure 44 A and the frame 3818 of the method 3800 of Figure 44 B description, above by reference to the frame of Figure 20 and Figure 31 method 2000 described 2016 and/or be substantially similar to above by reference to Fig. 1 describe method 100 frame 118.As set forth above, it is possible to outer by implementing Growth process forms source/drain component, which provides the source/drain that covering (cladding) is located at fin The epitaxial material of the part of epitaxial layer in extremely.Referring to Figure 57 A/ Figure 57 B, for each type of device, source/drain component 4402 and 4404 are formed on the fin element 402 of adjacent gate stack 902.Referring to Figure 57 A, source/drain component 4402 is wrapped Include by epitaxial layer 306 on the region of adjacent gate structures 902 epitaxial growth of semiconductor material layer come the material that is formed 4402A.It is, material 4402A is formed in around the nano wire (for example, epitaxial layer 306) of adjacent gate；This can be referred to as " coating " is formed around nano wire.Source/drain component including epitaxial material 4402A can with above by reference to Figure 44 A Discuss it is substantially similar and/or be substantially similar to above by reference to Figure 13 describe epitaxial source/drain material 1302A.Reference The example of Figure 57 B, source/drain component 4404 include by the extension on the region of the adjacent gate structures 902 of epitaxial layer 306 The material 4404A for growing semiconductor material layer to be formed.It is, material 4404A is formed in the nano wire (example of adjacent gate Such as, epitaxial layer 306) around；This can be referred to as the formation " coating " around nano wire.Source including epitaxial material 4404A Pole/drain feature can with above by reference to discuss similar of 44B and/or be substantially similar to the extension described above by reference to Figure 13 Source/drain material 1302A.Material for 4404A and 4402A has suitably in combination with relevant type of device (N-shaped, p-type) Component or suitably adulterate.Therefore, in embodiment, material 4404A and 4402A is at least one of composition or doping It is different.For example, in some embodiments, epitaxial material 4402A provides the source/drain material for being suitable for PFET device； Epitaxial material 4404A provides the source/drain material for being suitable for NFET device.Therefore, source/drain component 4402 and 4404 can To be formed in identical or different technique.
Method 5100 then advancees to frame 5122, forms ILD layer and/or removal gate structure.Frame 5122 is substantially similar In the frame 120 of the frame 3820 of method 3800, the frame 2018 of method 2000 and/or method 100.The example of reference Figure 58 A/58B, ILD layer 1402 is formed above substrate 202.As shown in Figure 58 A/58B, electrode layer 904 (or electrode layer 904 and dielectric layer 802) Removal generate groove 1404.
Method 5100 then advancees to frame 5124, the epitaxial layer in the channel region of selective removal device.In some implementations In example, remove selected outer in the region (on the area or top will form gate structure, that is, channel region) of fin element Prolong layer.(can providing suitable masking) simultaneously or in a separate step, implementation is used for the selection of two kinds of device Property removal.Frame 5124 is substantially similar to the frame 20/22 and/or Figure 33 of the method 2000 of the frame 3822 of method 3800, Figure 20 The example of the frame 122 and/or Figure 15 of example and/or the method for Fig. 1 100.Referring to the example of Figure 59 A/59B, for two types Device (N-shaped and p-type), remove epitaxial layers 304 out of substrate 202 channel region and groove 1404.As described above, one In a little embodiments, epitaxial layer 304 is SiGe and epitaxial layer 306 is silicon so as to selective removal SiGe epitaxial layer 304.It should Note that being mentioned between the neighbouring nano wire in channel region during 5124 intermediate treatment stage of frame (for example, Figure 59 A/59B) For gap 1502 (for example, gap 1502 between epitaxial layer 306).
Method 5100 then advancees to frame 5126, forms gate structure.Frame 5126 may be substantially similar to method 3800 Frame 3824, above by reference to Figure 20, Figure 34, Figure 35, Figure 36 and Figure 20 describe method 2000 frame 2022 and/or can be basic The upper frame 124 for being similar to the method 100 described above by reference to the example of Fig. 1 and/or Figure 16, Figure 17, Figure 18 and Figure 19.Referring to figure The example of 60A forms gate stack 4702 in the embodiment of frame 5126 in the groove 1404 of the device of the first kind. Gate stack is formed in the groove 1404 of the device of Second Type in the embodiment of frame 5126 referring to the example of Figure 60 B 4704.Gate stack 4702 and 4704 may include different compositions and/or be formed during different process.Gate stack Any of 4702 and 4704 or both may each be high K/ metal gate stacks part.Gate stack 4702 is provided for the The suitable work function of one types of devices (for example, PFET).Gate stack 4704 provide for Second Type device (for example, NFET suitable work function).For example, the metal layer of gate stack 4702 and 4704 may include identical or different group Point, including selection by Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, These components in group that Ir, Co, Ni, other suitable metal materials or their combination form.
Therefore, method 5100 is provided in some embodiments of the device 6000 of the first kind.In some embodiments, device Part 6000 is PFET device.In some embodiments, method 5100 provides the device 6010 of Second Type.In some embodiments In, device 6010 is NFET device.Device 6000 and 6010 can be provided on same substrate and integrated to be formed together Circuit.As described above, the advantage of method 5000 and/or some embodiments of device 6010 is by between the extension source of covering The thickness increase of oxide layer (see oxide layer 3904) between pole/drain electrode provides enhanced strain.In some embodiments, device 6000 advantage is to exist under oxide layer 502 in channel and/or source/drain regions.In some embodiments, device 6010 Advantage is to exist under oxide layer 502 in channel and/or source/drain regions.
Device 6000 and/or 6010 may be embodied as loopful grid (GAA) device, that is, gate structure 4702/4704 is formed in On more sides of nano wire (epitaxial layer 306).Multigate device 6000 Figure 60 A isometric view and Figure 61 A (transversal A), Corresponding sectional view is shown in Figure 62 A (passing through the transversal B of gate structure 4702), Figure 63 A (passing through the transversal C of source/drain). Multigate device 6010 (passes through the transversal of gate structure 4702 in isometric view and Figure 61 B (transversal A), Figure 62 B of Figure 60 B B), corresponding sectional view is shown in Figure 63 B (passing through the transversal C of source/drain).For the ease of referring to Figure 61 A/B, Figure 62 A/B ILD layer 1402 is removed with Figure 63 A/B.As shown in 61A, Figure 62 A, Figure 61 B and Figure 62 B, gate dielectric 4706 is arranged in extension 306 (for example, nano wire) of layer are below.However, in other embodiments, the other parts of respective gate structure 4702,4704 (for example, gate electrode 4710,4712) also can be set below epitaxial layer 306.In some embodiments, device 6000 and/or 6010 can be the FINFET device that its grid is formed on at least two sides (for example, top and two sidewalls) of channel region and/or With other configurations known in the art.Device 6000 and 6010 in Figure 63 A and Figure 63 B show source/drain component 4402, 4404 have coating 4402A, 4404A of the epitaxial growth being arranged on the multi-surface of epitaxial layer 306 (for example, nano wire), Dielectric material (being spacer 1102 and oxide layer 3904 respectively) is between epitaxial layer 306 simultaneously.
Semiconductor devices 6000 and 6010 can undergo further handle with formed all parts known in the art and Region.For example, subsequent processing can be formed on substrate 202, to be configured as connection all parts to be formed may include one Or the contact opening of the functional circuit of multiple multigate devices, contact metal and each contact/through-hole/line and more Layer interconnecting member (for example, metal layer and interlayer dielectric).In embodiment again, multilayer interconnection part may include such as through-hole or The horizontal interconnection piece of the vertical interconnection of contact and such as metal wire.Each interconnecting member can using including copper, tungsten and/ Or each conductive material of silicon.In an example, inlay and/or dual-damascene technics be used for cupric multilayer interconnection structure.This Outside, before method 5100, device and additional processing step can be executed later, and each implementation according to method 5100 Above-mentioned some processing steps can be replaced or be eliminated to example.
Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.
Therefore, in one in a wide range of embodiments, the method for semiconductor devices manufacture is described, method includes being formed Extend from substrate and fin with source/drain regions and channel region.Fin includes the first epitaxial layer and position with the first component In the second epitaxial layer on the first epitaxial layer, the second epitaxial layer has the second component.Outside the source/drain regions of fin removal second Prolong layer to form gap.Gap is filled with dielectric material.Another epitaxial material is formed at least two surfaces of the first epitaxial layer On to form source/drain component.
In embodiment, a kind of method for manufacturing multigate device is presented.Method includes that growth includes first, the Two and third epitaxial layer epitaxial layers stack overlapping piece.Epitaxial layers stack overlapping piece is patterned to form fin element.It is formed above fin element Dummy gate structure.The second epitaxial layer in the firstth area and the secondth area of fin is transformed into (transformed to) dielectric layer. The third area of fin being located at below dummy gate structure is between the first and secondth area.It is removed after changing the second epitaxial layer pseudo- Gate structure, therefore form groove.Metal gate structure is formed in the trench, and wherein metal gates are arranged outside first and third Prolong on more sides of each of layer.The second epitaxial layer is changed by the second epitaxial layer of oxidation in yet other embodiments,.Another In a little embodiments, the second extension is changed to form gap and fill gap with dielectric material by the second epitaxial layer of removal Layer.
In another embodiment, multiple gate semiconductor device is formed, the offer of multiple gate semiconductor device extends from substrate First fin element.Gate structure extends above the channel region of the first fin element.The channel region of first fin element includes by grid Multiple channel semiconductors that the part of pole structure surrounds.The channel region adjacent gate structures of first fin element.Source/drain regions Including the first semiconductor layer, the dielectric layer above the first semiconductor layer and positioned at the second semiconductor of dielectric layer Layer.

Claims (19)

1. a kind of method of semiconductor devices manufacture, comprising:
The fin extended from substrate is formed, the fin has source/drain regions and channel region, wherein the fin includes having first First epitaxial layer of component and the second epitaxial layer on first epitaxial layer, second epitaxial layer have second group Point；
It is formed and is extended from the substrate and another fin with source/drain regions and channel region, wherein another fin includes First epitaxial layer and second epitaxial layer；
Second epitaxial layer of another fin is aoxidized, while hard mask layer protects the fin；
Second epitaxial layer is removed from the source/drain regions of the fin to form gap；
The gap is filled with dielectric material；
While the dielectric material fills the gap, grown at least two surfaces of first epitaxial layer another Epitaxial material is to form source/drain component；And
Source/drain extensions layer is grown on first epitaxial layer of another fin, wherein the source/drain extensions Second epitaxial layer of the neighbouring oxidation of layer.
2. the method for semiconductor devices manufacture according to claim 1, further includes:
Third epitaxial layer is formed below first epitaxial layer；
The third epitaxial layer is aoxidized to form the third epitaxial layer of oxidation；
Wherein, the lower section of the grid of the third epitaxial layer of the oxidation on the channel region and the source/drain component Lower section.
3. the method for semiconductor devices manufacture according to claim 1, further includes:
Second epitaxial layer is removed from the channel region of the fin to form another gap；And
Gate structure is formed on first epitaxial layer being located in the channel region, wherein the shape in another gap At least partly at the gate structure.
4. the method for semiconductor devices manufacture according to claim 1, further includes:
Before forming the fin, implement anti-break-through (APT) ion implanting for reaching the substrate interior；And
After implementing the anti-break-through ion implanting and before forming the fin, described the is deposited on the substrate One epitaxial layer and the second epitaxial layer described in the first epitaxial layer disposed thereon.
5. the method for semiconductor devices manufacture according to claim 1, further includes:
First epitaxial layer is formed by growth silicon layer；And
Second epitaxial layer is formed by growing germanium-silicon layer directly on the silicon layer.
6. the method for semiconductor devices manufacture according to claim 1, wherein first epitaxial layer has the first oxidation Rate, second epitaxial layer have the second oxidation rate greater than first oxidation rate.
7. the method for semiconductor devices manufacture according to claim 1, wherein the thickness of the second epitaxial layer of the oxidation Greater than the thickness of second epitaxial layer, so that top surface of first epitaxial layer in the channel region of another fin is low In top surface of first epitaxial layer in the source/drain regions of another fin.
8. the method for semiconductor devices manufacture according to claim 1, further includes:
Gate structure is formed on the fin, wherein first extension in the channel region is arranged in the gate structure Layer top, bottom and opposite sides top.
9. the method for semiconductor devices manufacture according to claim 8, comprising:
The top at the top of first epitaxial layer in the channel region, bottom and opposite sides forms the gate structure High k gate dielectric.
10. a kind of method for manufacturing multigate device, which comprises
Growth includes the epitaxial layers stack overlapping piece of the first epitaxial layer, the second epitaxial layer and third epitaxial layer；
The epitaxial layers stack overlapping piece is patterned to form fin；
Dummy gate structure is formed above the fin；
Second epitaxial layer in the firstth area and the secondth area that are located at the fin is transformed into dielectric layer so that firstth area In the dielectric layer thickness be greater than third area in second epitaxial layer thickness, wherein the third of the fin Area is between firstth area and secondth area, wherein the third area is located at below the dummy gate structure；
After changing second epitaxial layer, the dummy gate structure is removed, to form groove；And
Form metal gate structure in the trench, wherein metal gate structure setting in first epitaxial layer and In the multi-panel of each of the third epitaxial layer.
11. the method for manufacture multigate device according to claim 10, wherein the transformation includes oxidation described first Second epitaxial layer in area.
12. the method for manufacture multigate device according to claim 10, wherein the transformation includes:
Removal is located at second epitaxial layer in firstth area to form gap；And
The gap is filled with dielectric material.
13. the method for manufacture multigate device according to claim 10, further includes:
After removing the dummy gate structure, second epitaxial layer is removed described the from the third area of the fin Gap is formed in 3rd area.
14. the method for manufacture multigate device according to claim 13, wherein the high k of the metal gate structure is situated between Electric layer is arranged in the gap in the third area.
15. the method for manufacture multigate device according to claim 12, further includes:
Fourth epitaxial layer is formed below first epitaxial layer, second epitaxial layer and the third epitaxial layer；And
The fourth epitaxial layer is aoxidized to form oxide skin(coating), wherein the thickness of the oxide skin(coating) is greater than the dielectric layer Thickness.
16. a kind of multiple gate semiconductor device, comprising:
Fin element extends from substrate；
Gate structure extends above the channel region of the fin element, wherein the channel region of the fin element includes quilt The first channel semiconductor and the second channel semiconductor that the gate dielectric of the gate structure surrounds；And
The source/drain regions of the fin element, the neighbouring gate structure, wherein the source/drain regions include:
First semiconductor layer, the dielectric layer above first semiconductor layer and positioned at the second of the dielectric layer Semiconductor layer, wherein the thickness of the dielectric layer is greater than first channel semiconductor and second channel semiconductor Between the gate dielectric thickness.
17. multiple gate semiconductor device according to claim 16, further includes: third semiconductor layer, the third are partly led Body layer covers first semiconductor layer and second semiconductor layer and has a common boundary with the side wall of the dielectric layer.
18. multiple gate semiconductor device according to claim 17, wherein first semiconductor layer includes Si, described Dielectric layer includes the SiGe of oxidation, and second semiconductor layer includes Si.
19. multiple gate semiconductor device according to claim 17, wherein the high-K gate dielectric of the gate structure It is arranged between first channel semiconductor and second channel semiconductor.
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US11437513B2 (en) 2022-09-06
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US20200152794A1 (en) 2020-05-14
US11942548B2 (en) 2024-03-26

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