CN106024701B - Trench power device and manufacturing method - Google Patents

Trench power device and manufacturing method Download PDF

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CN106024701B
CN106024701B CN201610557135.7A CN201610557135A CN106024701B CN 106024701 B CN106024701 B CN 106024701B CN 201610557135 A CN201610557135 A CN 201610557135A CN 106024701 B CN106024701 B CN 106024701B
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groove
layer
trench
material layer
semiconductor substrate
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CN106024701A (en
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杨彦涛
王平
夏志平
李云飞
周艳春
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Hangzhou Silan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses a trench power device and a manufacturing method thereof. According to the trench power device and the manufacturing method, the first trench is formed in the semiconductor substrate, the first blocking layer and the filling material layer are arranged in the first trench to form the electrostatic isolation structure, so that the electrostatic isolation structure is arranged in the semiconductor substrate, the situation that the electrostatic isolation structure is higher than the second trench and the third trench is avoided, the surface of the semiconductor substrate is smooth, the problem that the step coverage capability of a subsequent deposition process is poor due to the unevenness of the traditional electrostatic isolation structure, particularly photoresist is poor due to photoetching, exposure is abnormal, photoresist at the step is thinner and cannot be effectively used as an etching blocking layer is solved, and the electrostatic isolation structure with high performance ESD capability is obtained by forming the electrostatic isolation structure by the first filling material layer and the second filling material layer which are deposited in a plurality of times, so that the device structure is realized, and parameters and reliability meet the requirements of products.

Description

Trench power device and manufacturing method
Technical Field
The invention relates to the field of semiconductor equipment, in particular to a trench power device and a manufacturing method thereof.
Background
In semiconductor technology, power discrete devices include devices such as power MOSFETs, high power transistors, and IGBTs. Early power devices were produced based on planar technology, but with the development of semiconductor technology, small size, high power and high performance have become the trend of semiconductor development. The trench technology changes the channel from horizontal to vertical, eliminates the influence of parasitic JFET resistance of a planar structure, greatly reduces the cell size, increases the cell density on the basis of the influence, improves the total width of the channel in a unit area chip, and can increase the channel width-to-length ratio of the device on the unit silicon chip so as to increase the current, reduce the on-resistance and optimize related parameters, thereby realizing the aim that a smaller-sized die has higher power and high performance, and the trench technology is increasingly applied to novel power devices.
Electrostatic discharge (Electro Static Discharge, ESD) is a rapid charge transfer phenomenon between two objects, which is accompanied by a large electric field strength and current density, which if not effectively discharged, would lead to breakdown of the device gate dielectric and even breakdown and burning out of the silicon substrate and dielectric. In circuit products, the electrostatic isolation structures in most integrated circuits are realized by doping silicon in a silicon substrate, which occupies a certain silicon wafer area, but for device products, the electrostatic isolation structures are usually realized in a polysilicon layer (three-dimensional space), so that a certain area can be saved, and the cost is saved. However, the electrostatic isolation structure realized by polysilicon has various disadvantages. As shown in fig. 1, the structure of a conventional trench power device with electrostatic protection function is schematically shown, and the whole device can be divided into an ESD region, a gate wire region and a cell region. The electrostatic isolation structure 3 in the ESD area adopts polysilicon doped with multiple groups of P/N phases to realize ESD protection. Since the electrostatic isolation structure 3 will have a large electric field strength and current density, the electrostatic isolation structure 3 needs to be effectively isolated from the semiconductor silicon substrate 1, and thus a thicker dielectric layer 2 is required to be isolated below the electrostatic isolation structure 3, and the thickness h1 is generally required to be greater than
Figure BDA0001047689390000011
Meanwhile, since the polysilicon itself needs a thickness h2 generally greater than +.>
Figure BDA0001047689390000012
Thus, there will be a step difference of about 1 μm or even greater than 1 μm, which is notThe planar structure can cause poor step coverage of the subsequent process for depositing the dielectric layer 4, particularly poor photoresist uniformity and abnormal exposure of photolithography, and the photoresist at the step is thinner and can not be effectively used as an etching barrier layer, so that the device structure can not be realized, and the parameters and the reliability of the product can not meet the requirements.
Meanwhile, since the polycrystalline doping preferentially diffuses along the grain boundaries rather than along the grain bodies, the diffusion coefficient is greatly affected, and the structure of the electrostatic isolation structure 3 conventionally formed on the polycrystalline silicon is shown in fig. 2. The electrostatic isolation structure 3 forms an N/P/N/P structure on the polysilicon, and its ESD capability is affected by the width of the N/P type polysilicon, the grain size of the polysilicon, the doping amount, the energy, the annealing, etc., and meanwhile, due to the characteristic of the diffusion arc distribution, the impurity in the N/P connected region is uneven (as shown by the arc in fig. 2), and the withstand voltage is unstable, resulting in abnormal leakage. In a particularly small linewidth process, the high performance ESD capability requires precise control of the width, concentration, morphology, etc. of the polysilicon doped N and P types.
How to reduce the step difference generated by the electrostatic isolation structure by optimizing the product structure and the process flow, so that the surface of the whole semiconductor substrate is flat, the problem that the step coverage capability of the subsequent deposition process is poor due to the uneven of the traditional electrostatic isolation structure, particularly photoresist is poor in photoetching, exposure is abnormal, photoresist at the step is thinner and can not be effectively used as an etching barrier layer, and the like is solved, and how to obtain the electrostatic isolation structure with high-performance ESD capability, so that the device structure is realized, parameters and reliability meet the requirements of products, and the method is researched by the technical personnel.
Disclosure of Invention
The invention aims to provide a trench power device and a manufacturing method thereof, which solve the problems that the step coverage capability of a subsequent deposition process is affected due to uneven surface of a semiconductor substrate caused by a traditional electrostatic isolation structure, particularly photoresist is poor in photoresist uniformity and abnormal in exposure, photoresist at a step is thinner and cannot be effectively used as an etching barrier layer and the like.
Another object of the present invention is to obtain an electrostatic isolation structure with high performance ESD capability.
In order to solve the technical problems, the invention provides a manufacturing method of a trench power device, comprising the following steps:
providing a semiconductor substrate;
forming a first groove, a second groove and a third groove in the semiconductor substrate;
forming a first blocking layer on the surface of the semiconductor substrate in the area where the first groove is located and on the bottom wall and the side wall of the first groove;
growing gate dielectric layers on the surfaces of the semiconductor substrate in the areas where the second groove and the third groove are located and the bottom walls and the side walls of the second groove and the third groove;
forming a first filling material layer and filling the first groove, the second groove and the third groove;
flattening the surface of the semiconductor substrate to expose the gate dielectric layer, the first blocking layer and the first filling material layer, wherein the upper surfaces of the gate dielectric layer, the first blocking layer and the first filling material layer are flush;
etching the first filling material layer in the first groove to form a groove;
forming a second filling material layer in the groove to form an electrostatic isolation structure, wherein the first filling material layer is flush with the upper surface of the second filling material layer, and the doping types are different;
forming P wells at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
forming N-type regions on the P-well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
etching the dielectric layer to form contact holes, wherein the contact holes extend into the first filling material layer of the first groove and the second groove and the P well at one side of the third groove respectively; and
and forming a P-type region at the bottom of the contact hole.
Optionally, for the method for manufacturing a trench power device, the doping type of the first filling material layer is N-type doping, and the doping type of the second filling material layer is P-type doping.
Optionally, for the method for manufacturing the trench power device, the depth of the first trench is 1 μm-3.5 μm, the width is 1 μm-10 μm, the depth of the second trench is 1 μm-3.5 μm, the width is 0.5 μm-2 μm, and the depth of the third trench is 1 μm-3.5 μm, and the width is 0.1 μm-0.6 μm.
Optionally, for the method for manufacturing a trench power device, the material of the first blocking layer is one or more of silicon dioxide, silicon nitride and silicon oxynitride.
Optionally, for the method for manufacturing a trench power device, the thickness of the first blocking layer is
Figure BDA0001047689390000031
Optionally, for the method for manufacturing the trench power device, the thickness of the first filling material layer is 0.3 μm-1 μm.
Optionally, the method for manufacturing the trench power device further includes, after forming the first blocking layer, before growing the gate dielectric layer:
forming a first oxide layer on the side walls and the bottom wall of the second groove and the third groove;
and removing the first oxide layer.
Optionally, for the method for manufacturing the trench power device, the first filling material layer is formed by in-situ doping deposition.
Optionally, for the method for manufacturing the trench power device, a dry etching process is used to etch the first filling material layer in the first trench to form a groove.
Optionally, for the method for manufacturing the trench power device, the number of the grooves is multiple.
Optionally, for the method for manufacturing the trench power device, the second filling material layer is formed by in-situ doping deposition, and planarization is performed, so that the second filling material layer is flush with the upper surface of the first filling material layer.
Optionally, for the method for manufacturing the trench power device, the planarization is performed by using a chemical mechanical polishing process or a back etching process.
Optionally, for the method for manufacturing a trench power device, the material of the dielectric layer is one or more of silicon dioxide, silicon nitride, silicon oxynitride, and polysilicon.
Optionally, for the method for manufacturing the trench power device, the depth of the contact hole in the semiconductor substrate is 0.1 μm-0.8 μm.
Optionally, for the method for manufacturing a trench power device, after forming a P-type region at the bottom of the contact hole, the method further includes:
forming a metal layer on the semiconductor substrate, wherein the metal layer fills the contact hole; and
and forming a passivation layer on the metal layer.
The invention also provides a trench power device, comprising:
a semiconductor substrate;
the first groove, the second groove and the third groove are positioned in the semiconductor substrate;
the first blocking layer is positioned on the surface of the semiconductor substrate in the area where the first groove is positioned and is positioned on the bottom wall and the side wall of the first groove;
gate dielectric layers on the surfaces of the semiconductor substrate and the bottom walls and the side walls of the second groove and the third groove in the areas where the second groove and the third groove are located;
the first filling material layer is positioned in the first groove, the second groove and the third groove;
a recess in the first layer of filler material in the first trench;
the second filling material layer is positioned in the groove, the doping types of the first filling material layer and the second filling material layer are different, and the first filling material layer and the second filling material layer in the first groove are used as electrostatic isolation structures together;
a first filling material layer located in the second and third trenches; the upper surfaces of the first filling material layer, the second filling material layer, the gate dielectric layer and the first stopping layer are flush;
p wells positioned at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
the N-type region is positioned on the P well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
a dielectric layer on the semiconductor substrate;
the contact hole penetrates through the dielectric layer and extends into the first filling material layer of the first groove and the second groove and the P well at one side of the third groove respectively; and
and the P-type region is positioned at the bottom of the contact hole.
Optionally, for the trench power device, the doping type of the first filling material layer is N-type doping, and the doping type of the second filling material layer is P-type doping.
Optionally, for the trench power device, the depth of the first trench is 1 μm-3.5 μm, the width is 1 μm-10 μm, the depth of the second trench is 1 μm-3.5 μm, the width is 0.5 μm-2 μm, and the depth of the third trench is 1 μm-3.5 μm, and the width is 0.1 μm-0.6 μm.
Optionally, for the trench power device, the material of the first blocking layer is one or more of silicon dioxide, silicon nitride, and silicon oxynitride.
Optionally, for the trench power device, the thickness of the first blocking layer is
Figure BDA0001047689390000051
Optionally, for the trench power device, the thickness of the first filling material layer is 0.3 μm-1 μm.
Optionally, for the trench power device, the number of the grooves is multiple.
Optionally, for the trench power device, the dielectric layer is made of one or more of silicon dioxide, silicon nitride, silicon oxynitride, and polysilicon.
Optionally, for the trench power device, the contact hole is located in the semiconductor substrate at a depth of 0.1 μm to 0.8 μm.
Optionally, for the trench power device, the method further includes:
a metal layer on the semiconductor substrate, wherein the metal layer fills the contact hole; and
and a passivation layer on the metal layer.
Compared with the prior art, the trench power device and the manufacturing method provided by the invention have the advantages that the first trench is formed in the semiconductor substrate, and the first blocking layer and the filling material layer are arranged in the first trench to form the electrostatic isolation structure, so that the electrostatic isolation structure is arranged in the semiconductor substrate, the situation that the electrostatic isolation structure is higher than the second trench and the third trench is avoided, the surface of the semiconductor substrate is flat, the problem that the step coverage capability of the subsequent deposition process is poor due to the unevenness of the traditional electrostatic isolation structure, particularly photoresist uniformity is poor, exposure is abnormal, photoresist at the step is thinner and cannot be effectively used as an etching blocking layer is effectively solved; further, the electrostatic isolation structure is formed by the first filling material layer and the second filling material layer which are deposited in a separated mode, and the electrostatic isolation structure with high-performance ESD capability is obtained, so that the device structure is realized, and parameters and reliability meet the requirements of products.
Drawings
Fig. 1 is a schematic diagram of a trench power device in the prior art;
FIG. 2 is a schematic structural diagram of an electrostatic isolation structure according to the prior art;
FIG. 3 is a flow chart of a method for fabricating a trench power device in accordance with an embodiment of the present invention;
fig. 4-12 are schematic structural diagrams of a trench power device in accordance with an embodiment of the present invention.
Detailed Description
The trench power device and method of fabrication of the present invention will now be described in more detail with reference to the drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the beneficial effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a trench power device and a manufacturing method thereof, wherein the manufacturing method of the trench power device comprises the following steps:
step S11, providing a semiconductor substrate;
step S12, forming a first groove, a second groove and a third groove in the semiconductor substrate;
step S13, forming a first blocking layer on the surface of the semiconductor substrate in the area where the first groove is located and the bottom wall and the side wall of the first groove;
step S14, growing gate dielectric layers on the surfaces of the semiconductor substrate in the areas where the second groove and the third groove are located and the bottom walls and the side walls of the second groove and the third groove;
step S15, forming a first filling material layer and filling the first groove, the second groove and the third groove;
step S16, flattening is carried out, so that the surface of the semiconductor substrate exposes the gate dielectric layer, the first blocking layer and the first filling material layer, and the upper surfaces of the gate dielectric layer, the first blocking layer and the first filling material layer are flush;
step S17, etching the first filling material layer in the first groove to form a groove;
step S18, forming a second filling material layer in the groove to form an electrostatic isolation structure, wherein the first filling material layer is flush with the upper surface of the second filling material layer, and the doping types are different;
step S19, forming P wells at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
step S20, forming N-type regions on the P-well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
step S21, forming a dielectric layer on the semiconductor substrate;
step S22, etching the dielectric layer to form contact holes, wherein the contact holes extend into the first filling material layers of the first groove and the second groove and the P well at one side of the third groove respectively; and
and S23, forming a P-type region at the bottom of the contact hole.
The trench power device and the method of fabricating the same of the present invention are described in detail below with reference to fig. 3 and fig. 4-12. FIG. 3 is a flow chart of a method for fabricating a trench power device according to an embodiment of the invention; fig. 4-12 are schematic structural diagrams of a trench power device in accordance with an embodiment of the present invention.
First, step S11 is performed, and as shown in fig. 4, the semiconductor substrate 10 is provided. The semiconductor substrate 10 may be a silicon substrate, a silicon germanium substrate, a group iii-v compound substrate, or other semiconductor material substrate known to those skilled in the art, and in this embodiment, a silicon substrate is used. More specifically, the silicon substrate employed in the present embodiment may be formed with a semiconductor device such as a MOS field effect transistor, an IGBT insulated gate field effect transistor, schottky, or the like.
Specifically, in the present step S11, the semiconductor substrate having a specific doping type refers to an N-type and P-type semiconductor substrate doped with a certain impurity amount according to the product characteristics.
Next, step S12 is performed to form a first trench 11a, a second trench 11b, and a third trench 11c in the semiconductor substrate 10. With continued reference to fig. 4, the first trench 11a, the second trench 11b, and the third trench 11c may be obtained by etching silicon on the semiconductor substrate 10 by dry etching. The first grooves 11a have a depth of 1 μm to 3.5 μm and a width of 1 μm to 10 μm, the second grooves 11b have a depth of 1 μm to 3.5 μm and a width of 0.5 μm to 2 μm, and the third grooves 11c have a depth of 1 μm to 3.5 μm and a width of 0.1 μm to 0.6 μm. In the present invention, the purpose of the first trench 11a is to make the following electrostatic isolation structure in the first trench 11a, and the region where the first trench 11a is located is an ESD region, correspondingly, the region where the second trench 11b is located is a gate lead region, and the region where the third trench 11c is located is a cell region.
Next, step S13 is performed, referring to fig. 5, a first blocking layer 11 is formed on the surface of the semiconductor substrate 10 in the region where the first trench 11a is located and on the bottom wall and the side wall of the first trench 11 a. In the embodiment of the present invention, the material of the first blocking layer 11 is silicon dioxide, silicon nitride, silicon oxynitride, or the like, or one or more combinations of the materials of silicon oxide, silicon nitride, silicon oxynitride, or the like.
Specifically, in the present step S13, the material of the first blocking layer 11 in the present embodiment is selected to be silicon oxide, and the thickness is
Figure BDA0001047689390000081
For example->
Figure BDA0001047689390000082
Etc. In this step, the isolation between the electrostatic isolation structure and the substrate is realized by forming the first blocking layer 11, and further, by adjusting the thickness of the first blocking layer 11, the excessive thickness of the filling material layer is avoided, and the ion implantation process and the etching and deposition processes of the electrostatic isolation structure are optimized.
Specifically, the step S13 includes: in step S131, referring to fig. 5, a first blocking layer 11 is formed on the semiconductor substrate 10.
In step S132, the first blocking layer 11 is etched, the first blocking layer 11 on the surface of the semiconductor substrate 10 outside the area where the first trench 11a is located is removed, and only the portion of the first blocking layer 11 covering the bottom wall and the side wall of the first trench 11a and the portion of the first blocking layer 11 located in the area where the first trench 11a is located on the semiconductor substrate 10 remain. This may be accomplished in this embodiment using a thinner BOE etchant.
Next, step S133 is performed to perform high-temperature repair. Preferably, high temperature sacrificial oxidation is performed at a temperature in the range of 1000 ℃ to 1200 ℃ to repair the bottom walls and side walls of the second trench 11b and the third trench 11c at a high temperature, resulting in about
Figure BDA0001047689390000091
And rinsing the first oxide layer with a thinner BOE corrosive liquid to remove the first oxide layer.
Then, step S14 is performed, please continue with fig. 5, in which a gate dielectric layer 12 is grown on the surface of the semiconductor substrate 10 in the region where the second trench 11b and the third trench 11c are located and on the bottom walls and sidewalls of the second trench 11b and the third trench 11c. The growth of the gate dielectric layer 12 can be completed by adopting chlorine doped oxidation, the temperature range is 1000 ℃ to 1200 ℃, and the thickness range of the gate dielectric layer 12 is
Figure BDA0001047689390000092
Preferably, when the thickness of the gate dielectric layer 12 is +.>
Figure BDA0001047689390000093
In this case, the mask layer may be used as a masking layer to be subsequently implanted (the thickness of the gate dielectric layer 12 is related to vth\qg, etc., and the thickness thereof is determined according to the product characteristics, so that those skilled in the art can set the thickness of the gate dielectric layer 12 according to actual needs).
Then, step S15 is performed, please refer to fig. 6, wherein a first filling material layer 13 is formed and fills the first trench 11a, the second trench 11b and the third trench 11c. Preferably, the doping type of the first filling material layer 13 is N-type doping, i.e. the material is selected to be N-type doped polysilicon. This step may use in-situ doping deposition to form the first filler material layer 13. And mainly considering that the second trench 11b and the third trench 11c need N-type doping, the process of depositing N-type doping in this step can greatly optimize the process.
Specifically, in step S15, the deposited undoped polysilicon is required to be thicker than the undoped polysilicon due to its ability to withstand ESD withstand voltage release
Figure BDA0001047689390000094
For example 0.3 μm to 1 μm.
Then, in step S16, please refer to fig. 7, planarization is performed, such that the surface of the semiconductor substrate 10 exposes the gate dielectric layer 12, the first blocking layer 11 and the first filling material layer 13, and the upper surfaces of the gate dielectric layer 12, the first blocking layer 11 and the first filling material layer 13 are level. Specifically, this step includes sequentially removing the first filling material layer 13 and a portion of the first blocking layer 11 on the surface of the semiconductor substrate 10, so that the gate dielectric layer 12, the first blocking layer 11 and the first filling material layer 13 are exposed on the surface of the semiconductor substrate 10, and the upper surfaces of the gate dielectric layer 12, the first blocking layer 11 and the first filling material layer 13 are flush.
The removal of the first filling material layer 13 may be performed by Chemical Mechanical Polishing (CMP) or by a back etching process, so that the first filling material layer 13 in the trench is level with the gate dielectric layer 12 on the surface of the semiconductor substrate 10.
And, the filling material layer in the area where the first trench 11a is located may be polished to be flush with the first blocking layer 11 by a CMP process, and then the exposed thickness of the first blocking layer 11 to the gate dielectric layer 12 is etched by dry etching, and then the first filling material layer 13 protruding in the first trench 11a is polished to be flush with the plane where the gate dielectric layer 12 and the first blocking layer 11 are located by a CMP process, so that the upper surface of the obtained whole structure is flush.
As can be seen from fig. 7, after planarization, a first filling material layer 15a is formed in the first trench, a gate material layer 15b is formed in the second trench, and a gate material layer 15c is formed in the third trench.
After that, step S17 is performed, and as shown in fig. 8, the first filling material layer 15a in the first trench 11a is etched to form a groove 16. The number of the grooves 16 is plural, and the first filling material layers on both sides of the grooves 16 are denoted as first filling material layers 17 for distinction through the first filling material layers 15 a.
Specifically, in this step S17, the first filling material layer 15a in the first trench 11a is etched by using a dry etching process to form the recess 16.
Thereafter, in step S18, referring to fig. 9, a second filling material layer 18 is formed in the recess 16 to form an electrostatic isolation structure, and the first filling material layer 17 is level with the upper surface of the second filling material layer 18 and has different doping types.
Specifically, in step S18, the second filling material layer 18 is formed by in-situ doping deposition, that is, doping a certain impurity type in the deposition process, for example, in this embodiment, the doping impurity type is P-type, which is different from the doping type of the first filling material layer.
Further, after depositing the second filling material layer 18, planarization is performed, and the second filling material layer higher than the gate dielectric layer 12 is removed, typically by a CMP method or a back etching process, so that the second filling material layer 18 is flush with the upper surface of the first filling material layer.
Thereafter, the step S19 is continued, and referring to fig. 10, P-wells 19 are formed on both sides of the first trench 11a, the second trench 11b and the third trench 11c in the semiconductor substrate 10. Specifically, the first ion implantation and annealing may be performed to form P-wells 19 on both sides of the first trench 11a, the second trench 11b, and the third trench 11c in the semiconductor substrate 10.
In the step S19, the first ion implantation and annealing are performed by boron ion implantation with an implantation energy of 60KeV-150KeV and an implantation dose of 1E13/cm 2 -1E14/cm 2 The annealing temperature is 1000-1200 ℃.
Since the implantation concentration of the P-well 19 is relatively light compared to the doping requirement of the first filling material layer 13, the entire wafer can be directly implanted.
Specifically, in this step S19, it is necessary that the thickness of the remaining gate dielectric layer 12 and the first stopper layer 11 on the surface of the semiconductor substrate 10 be uniform, and if the thickness is larger than
Figure BDA0001047689390000101
Will make the implanted atoms less likely to penetrate and will be able to re-grow after drift out the oxide layer dedicated to implantation masking.
More specifically, in this step S19, if the thickness of the remaining gate dielectric layer 12 and first stopper layer 11 on the surface of the semiconductor substrate 10 is smaller than
Figure BDA0001047689390000102
The effect as implantation mask will be poor, therefore, the thickness of the remaining gate dielectric layer 12 and first stopper 11 on the surface of the semiconductor substrate 10 should be +.>
Figure BDA0001047689390000111
Thereafter, step S20 is performed, please continue with fig. 10, in which an N-type region 20 is formed on the P-well 19 in the semiconductor substrate 10 by the first trench 11a, the second trench 11b and the third trench 11c. Specifically, a second ion implantation may be performed to form N-type regions 20 on the P-well 19 at both sides of the first trench 11a, the second trench 11b and the third trench 11c in the semiconductor substrate 10, where the junction depth of the N-type regions 20 is smaller than the depth of the P-well 19.
Specifically, the step S20 may be performed with the same mask plate as the previous step S18, so as to save cost.
The second ion implantation adopts phosphorus ion or arsenic ion implantation, the implantation energy is 60KeV-150KeV, and the implantation dosage is 1E14/cm 2 -1E16/cm 2 。
As can be seen from the implantation doses in the steps S19 and S20, the doping concentration of the N-type region 20 is greater than that of the P-well 19, so that the N-type region 20 is an N-type heavily doped region.
Thereafter, step S21 may be further performed, referring to fig. 11, to form a dielectric layer 21 on the semiconductor substrate 10. Specifically, the dielectric layer 21 may be formed by a deposition process and subjected to a reflow annealing. The reflow annealing process optimizes the planarization process of dielectric layer 21 during formation and also the anneal activation process for the implantation of the preceding first fill material layer 13, second fill material layer 18, and N-type region 20. The reflow annealing temperature is 800-1000 ℃.
Continuing to step S22, referring to fig. 11, the dielectric layer 21 is etched to form contact holes 21a,21b and 21c, wherein the contact holes 21a,21b and 21c extend into the first filling material layer 17 in the first trench 11a, the first filling material layer 13 in the second trench 11b and the P-well 19 at one side of the third trench 11c, respectively. The contact holes 21a,21b and 21c are located in the semiconductor substrate 10 to a depth h3 equal to the depth of the N-type region 20 after annealing, and have a depth of 0.1 μm to 0.8 μm.
Continuing to step S23, as shown in fig. 11, P-type regions 21d are formed at the bottoms of the contact holes 21a,21b and 21 c. Specifically, the third ion implantation and annealing are performed to form the P-type region 21d. The third ion implantation is to implant element B11 or BF 2 B11 may be injected first and BF may be injected later 2 。
Specifically, in step S23, the implantation energy is 20KeV-100KeV, and the implantation dose is 1E14/cm 2 -1E16/cm 2 For example, zero angle implantation may be employed. After implantation, a furnace tube or rapid annealing (RTA) may be selected, with an annealing temperature of 500-1000 ℃. As can be seen from the implantation doses in step S19 and step S23, the doping concentration of the formed P-type region 21d is greater than that of the P-well 19, so that the P-type region 21d is a P-type heavily doped region.
Continuing to step S24, referring to fig. 12, a metal layer 22 is formed on the semiconductor substrate 10, and the metal layer 22 fills the contact holes 21a,21b and 21c and contacts the P-type region 21d. Specifically, the deposited metal layer 22 may be a metal or a compound material including titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tungsten (W), aluminum (Al), aluminum silicide (AlSi), copper silicon aluminum alloy (AlSiCu), copper (Cu), or nickel (Ni). Specifically, the metal layer 22 may be a metal wire formed after dry etching.
Further, after step S24 is completed, the metallization of the device is already implemented, and the passivation layer protection can be added according to the product requirement, so as to complete the processing of the front structure of the device;
furthermore, after the front structure is completed, the final realization of the device is completed through a series of back processes such as thinning, gold backing, scribing and the like.
Referring to fig. 3 to 12, the trench power device provided by the present invention includes:
a semiconductor substrate 10;
a first trench 11a, a second trench 11b, and a third trench 11c in the semiconductor substrate 10; preferably, the depth of the first groove 11a is 1 μm-3.5 μm and the width thereof is 1 μm-10 μm, the depth of the second groove 11b is 1 μm-3.5 μm and the width thereof is 0.5 μm-2 μm, and the depth of the third groove 11c is 1 μm-3.5 μm and the width thereof is 0.1 μm-0.6 μm;
the first blocking layer 11 is preferably formed of one or a combination of silicon dioxide, silicon nitride and silicon oxynitride on the surface of the semiconductor substrate 10 in the region of the first trench 11a and on the bottom wall and side wall of the first trench 11a, and the thickness of the first blocking layer 11 on the bottom wall of the first trench 11a is
Figure BDA0001047689390000121
A gate dielectric layer 12 on the surface of the semiconductor substrate 10 and on the bottom walls and side walls of the second trench 11b and the third trench 11c in the region where the second trench 11b and the third trench 11c are located; preferably, the gate dielectric layer 12 has a thickness of
Figure BDA0001047689390000122
First filling material layers 17, 13 located in the first trench 11a, the second trench 11b, and the third trench 11c; preferably, the thickness of the first filling material layers 17, 13 is 0.3 μm-1 μm;
a recess 16 in a first layer 17 of filler material located in said first trench 11 a; the number of the grooves 16 is a plurality;
a second filling material layer 18 located in the groove 16, the doping types of the first filling material layers 17 and 13 and the second filling material layer 18 are different, and the first filling material layer 17 and the second filling material layer 18 in the first groove 11a are used as electrostatic isolation structures together; the upper surfaces of the first filling material layers 17, 13, the second filling material 18, the gate dielectric layer 12 and the first blocking layer 11 are flush;
p-wells 19 located on both sides of the first trench 11a, the second trench 11b, and the third trench 11c in the semiconductor substrate 10;
an N-type region 20 located on the P-well 19 on both sides of the first trench 11a, the second trench 11b, and the third trench 11c in the semiconductor substrate 10; the junction depth of the N-type region 20 is smaller than the depth of the P-well 19;
a dielectric layer 21 on the semiconductor substrate 10;
contact holes 21a,21b and 21c penetrating the dielectric layer 21 and extending into the first filling material layer 17 in the first trench 11a, the first filling material layer 13 in the second trench 11b and the P-well 19 at the side of the third trench 11c, respectively, wherein the contact holes 21a,21b and 21c are located in the semiconductor substrate 10 to a depth equal to the depth of the N-type region 20 after annealing, and the depth is 0.1 μm to 0.8 μm;
a P-type region 21d located at the bottom of the contact hole 21;
a metal layer 22, the metal layer 22 filling the contact holes 21a,21b and 21c and contacting the P-type region 21d; preferably, the material of the metal layer 22 is titanium, titanium nitride, titanium silicide, tungsten, aluminum silicide, copper-silicon-aluminum alloy, copper or nickel, or a compound of metals; and
a passivation layer on the metal layer 22.
Therefore, the trench power device and the manufacturing method provided by the invention are characterized in that a semiconductor substrate is provided; forming a first groove, a second groove and a third groove in the semiconductor substrate; forming a first blocking layer on the surface of the semiconductor substrate in the area where the first groove is located and on the bottom wall and the side wall of the first groove; growing gate dielectric layers on the surfaces of the semiconductor substrate in the areas where the second groove and the third groove are located and the bottom walls and the side walls of the second groove and the third groove; forming a first filling material layer and filling the first groove, the second groove and the third groove; flattening the surface of the semiconductor substrate to expose the gate dielectric layer, the first blocking layer and the first filling material layer, wherein the upper surfaces of the gate dielectric layer, the first blocking layer and the first filling material layer are flush; etching the first filling material layer in the first groove to form a groove; forming a second filling material layer in the groove to form an electrostatic isolation structure, wherein the first filling material layer is flush with the upper surface of the second filling material layer, and the doping types are different; forming P wells at two sides of the first groove, the second groove and the third groove in the semiconductor substrate; forming N-type regions on the P-well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate; forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to form contact holes, wherein the contact holes extend into the first filling material layer of the first groove and the second groove and the P well at one side of the third groove respectively; and forming a P-type region at the bottom of the contact hole. The electrostatic isolation structure is formed, the electrostatic isolation structure is arranged in the semiconductor substrate, the situation that the electrostatic isolation structure is higher than the second groove and the third groove is avoided, the surface of the semiconductor substrate is smooth, the problem that the step coverage capability of a subsequent deposition process is poor due to the unevenness of a traditional electrostatic isolation structure, particularly photoresist uniformity is poor due to photoetching, exposure is abnormal, photoresist at the step is thinner and cannot be effectively used as an etching barrier layer is solved, and further, the electrostatic isolation structure is formed by a first filling material layer and a second filling material layer which are deposited in a separated mode, and the electrostatic isolation structure with high performance ESD capability is obtained, so that the device structure is realized, and parameters and reliability meet the requirements of products.
Furthermore, the trench power device structure and the manufacturing method of the invention can be applied to products including but not limited to CMOS, BCD, power MOSFET, high-power transistor, IGBT, schottky and the like.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (25)

1. A manufacturing method of a trench power device comprises the following steps:
providing a semiconductor substrate;
forming a first groove, a second groove and a third groove in the semiconductor substrate;
forming a first blocking layer on the surface of the semiconductor substrate in the area where the first groove is located and on the bottom wall and the side wall of the first groove;
growing a gate dielectric layer on the surface of the semiconductor substrate in the area where the second groove and the third groove are located and the bottom wall and the side wall of the second groove and the third groove, wherein the thickness of the first blocking layer is larger than that of the gate dielectric layer;
forming a first filling material layer and filling the first groove, the second groove and the third groove;
flattening the surface of the semiconductor substrate to expose the gate dielectric layer, the first blocking layer and the first filling material layer, wherein the upper surfaces of the gate dielectric layer, the first blocking layer and the first filling material layer are flush;
etching the first filling material layer in the first groove to form a groove;
forming a second filling material layer in the groove to form an electrostatic isolation structure, wherein the first filling material layer is flush with the upper surface of the second filling material layer, and the doping types are different;
forming P wells at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
forming N-type regions on the P-well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
etching the dielectric layer to form contact holes, wherein the contact holes extend into the first filling material layer of the first groove and the second groove and the P well at one side of the third groove respectively; and
and forming a P-type region at the bottom of the contact hole.
2. The method of manufacturing a trench power device of claim 1 wherein the doping type of the first filling material layer is N-type doping and the doping type of the second filling material layer is P-type doping.
3. The method of fabricating a trench power device of claim 1 wherein said first trench has a depth of 1 μm to 3.5 μm and a width of 1 μm to 10 μm, said second trench has a depth of 1 μm to 3.5 μm and a width of 0.5 μm to 2 μm, and said third trench has a depth of 1 μm to 3.5 μm and a width of 0.1 μm to 0.6 μm.
4. The method of fabricating a trench power device of claim 1 wherein the material of the first blocking layer is one or more combinations of silicon dioxide, silicon nitride, silicon oxynitride.
5. The method of claim 1, wherein the first blocking layer has a thickness of 1000 a-20000 a.
6. The method of fabricating a trench power device of claim 1 wherein said first filler material layer has a thickness of 0.3 μm to 1 μm.
7. The method of fabricating a trench power device of claim 1, further comprising, after forming the first stop layer, prior to growing the gate dielectric layer:
forming a first oxide layer on the side walls and the bottom wall of the second groove and the third groove;
and removing the first oxide layer.
8. The method of fabricating a trench power device of claim 1 wherein said first filler material layer is formed using in-situ doped deposition.
9. The method of fabricating a trench power device of claim 1 wherein a first filler material layer in said first trench is etched using a dry etch process to form a recess.
10. The method of manufacturing a trench power device of claim 1 wherein the number of grooves is a plurality.
11. The method of fabricating a trench power device of claim 1 wherein said second fill material layer is formed by in-situ doping deposition and planarized such that said second fill material layer is level with an upper surface of said first fill material layer.
12. The method of claim 1, wherein the planarizing is performed using a chemical mechanical polishing process or a back etching process.
13. The method of claim 1, wherein the dielectric layer is made of one or more of silicon dioxide, silicon nitride, silicon oxynitride, and polysilicon.
14. The method of fabricating a trench power device of claim 1 wherein said contact hole is located in said semiconductor substrate to a depth of 0.1 μm to 0.8 μm.
15. The method of manufacturing a trench power device of claim 1, further comprising, after forming a P-type region at a bottom of said contact hole:
forming a metal layer on the semiconductor substrate, wherein the metal layer fills the contact hole; and
and forming a passivation layer on the metal layer.
16. A trench power device comprising:
a semiconductor substrate;
the first groove, the second groove and the third groove are positioned in the semiconductor substrate;
the first blocking layer is positioned on the surface of the semiconductor substrate in the area where the first groove is positioned and is positioned on the bottom wall and the side wall of the first groove;
the first blocking layer is arranged on the bottom wall and the side wall of the second groove and the third groove, and the thickness of the first blocking layer is larger than that of the gate dielectric layer;
the first filling material layer is positioned in the first groove, the second groove and the third groove;
a recess in the first layer of filler material in the first trench;
the second filling material layer is positioned in the groove, the doping types of the first filling material layer and the second filling material layer are different, and the first filling material layer and the second filling material layer in the first groove are used as electrostatic isolation structures together; the upper surfaces of the first filling material layer, the second filling material layer, the gate dielectric layer and the first stopping layer are flush;
p wells positioned at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
the N-type region is positioned on the P well at two sides of the first groove, the second groove and the third groove in the semiconductor substrate;
a dielectric layer on the semiconductor substrate;
the contact hole penetrates through the dielectric layer and extends into the first filling material layer of the first groove and the second groove and the P well at one side of the third groove respectively; and
and the P-type region is positioned at the bottom of the contact hole.
17. The trench power device of claim 16 wherein the doping type of the first fill material layer is N-type doping and the doping type of the second fill material layer is P-type doping.
18. The trench power device of claim 16 wherein the first trench has a depth of 1 μm to 3.5 μm and a width of 1 μm to 10 μm, the second trench has a depth of 1 μm to 3.5 μm and a width of 0.5 μm to 2 μm, and the third trench has a depth of 1 μm to 3.5 μm and a width of 0.1 μm to 0.6 μm.
19. The trench power device of claim 16 wherein the material of the first blocking layer is one or more combinations of silicon dioxide, silicon nitride, silicon oxynitride.
20. The trench power device of claim 16, wherein a thickness of the first blocking layer is 1000 a-20000 a.
21. The trench power device of claim 16 wherein the first filler material layer has a thickness of 0.3 μm to 1 μm.
22. The trench power device of claim 16 wherein the number of grooves is a plurality.
23. The trench power device of claim 16 wherein the dielectric layer is one or more of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon.
24. The trench power device of claim 16 wherein said contact hole is located in said semiconductor substrate to a depth of 0.1 μm to 0.8 μm.
25. The trench power device of claim 16, further comprising:
a metal layer on the semiconductor substrate, wherein the metal layer fills the contact hole; and
and a passivation layer on the metal layer.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097433A (en) * 2009-12-10 2011-06-15 力士科技股份有限公司 Trench metal-oxide semiconductor field effect transistor (MOSFET) and manufacture method thereof
CN102299102A (en) * 2010-06-22 2011-12-28 茂达电子股份有限公司 Power semiconductor assembly with drain voltage protection and manufacturing method thereof
CN103187288A (en) * 2011-12-29 2013-07-03 立新半导体有限公司 Preparation method of groove semiconductor power device with static protection function
CN104347422A (en) * 2013-08-09 2015-02-11 上海华虹宏力半导体制造有限公司 Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit
CN104465628A (en) * 2014-12-11 2015-03-25 张家港凯思半导体有限公司 Groove power MOSFET device and manufacturing method and static protection structure thereof
CN205911311U (en) * 2016-07-12 2017-01-25 杭州士兰集成电路有限公司 Slot power device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564047B2 (en) * 2011-09-27 2013-10-22 Force Mos Technology Co., Ltd. Semiconductor power devices integrated with a trenched clamp diode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097433A (en) * 2009-12-10 2011-06-15 力士科技股份有限公司 Trench metal-oxide semiconductor field effect transistor (MOSFET) and manufacture method thereof
CN102299102A (en) * 2010-06-22 2011-12-28 茂达电子股份有限公司 Power semiconductor assembly with drain voltage protection and manufacturing method thereof
CN103187288A (en) * 2011-12-29 2013-07-03 立新半导体有限公司 Preparation method of groove semiconductor power device with static protection function
CN104347422A (en) * 2013-08-09 2015-02-11 上海华虹宏力半导体制造有限公司 Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit
CN104465628A (en) * 2014-12-11 2015-03-25 张家港凯思半导体有限公司 Groove power MOSFET device and manufacturing method and static protection structure thereof
CN205911311U (en) * 2016-07-12 2017-01-25 杭州士兰集成电路有限公司 Slot power device

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