TWI748271B - Integrated chip and method of forming the same - Google Patents

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.

Description

Integrated wafer and its forming method

The embodiment of the present invention relates to an integrated wafer and a method of forming the same.

Modern integrated wafers include millions or billions of semiconductor elements formed on a semiconductor substrate, such as silicon. Integrated chips (IC) can use many different types of transistor components depending on the application of the IC. In recent years, the increase in the market for mobile and RF (Radio Frequency) components has caused a significant increase in the use of high-voltage transistor components. For example, since high voltage transistor elements can handle high breakdown voltages (for example, breakdown voltages greater than about 50 volts) and high frequencies, power amplifiers in the RF transmission/reception chain often use high voltage transistor elements.

In some embodiments, the present disclosure relates to an integrated wafer. The integrated chip includes: a gate structure, arranged above the substrate, between the source region and the drain region; a first interlayer dielectric (ILD) layer, arranged above the substrate and the gate structure; and a second ILD Layer, arranged above the first ILD layer; a field plate etch stop structure, between the first ILD layer and the second ILD layer; a field plate, extending from the uppermost surface of the second ILD layer to the field plate etch stop structure; and more Conductive contacts from the top surface of the second ILD layer Extends to the source and drain regions.

In other embodiments, the present disclosure relates to an integrated wafer. The integrated chip includes: a gate structure arranged above the substrate between the source region and the drain region; a dielectric structure arranged above the substrate and the gate structure; a field plate etching termination structure arranged in the dielectric structure; A plurality of conductive contacts arranged in the dielectric structure; and a field plate arranged on the field plate etch stop structure, the field plate having a bottommost surface, the bottommost surface being parallel to the upper surface of the substrate and The top surface and the bottom surface of the plurality of conductive contacts are arranged in a first horizontal plane intersect with the sidewalls of the plurality of conductive contacts.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a gate structure between a source region and a drain region on a substrate; forming a contact etch stop layer on the substrate; forming a first ILD layer above the contact etch stop layer; forming a first ILD layer Then a field plate etch stop structure is formed between the gate structure and the drain region; a second ILD layer is formed above the field plate etch stop structure; and a plurality of contacts extending through the first ILD layer and the second ILD layer are simultaneously formed And a field plate extending through the second ILD layer to the field plate etch stop structure.

100, 2000, 2200, 2300, 2400, 3500, 3600, 3700: high voltage transistor components

102: Semiconductor substrate

104, 804: source region

105: Arrow

106: Drain Region

108: gate electrode

110: gate dielectric layer

112: Passage area

114, 204, 702, 2104: drift zone

116, 210: Gate structure

118, 1504, 3402: the first ILD layer

120, 814: contacts

120a: first contact

120b: second contact

120c: third contact

122, 214, 408, 902: field board

124: Dielectric layer

126, 416, 502, 602, 3406: the second ILD layer

128: The first post-process (BEOL) metal line layer

200, 300, 400, 500, 600, 700a, 700b, 700c, 800, 1000: LDMOS element

202, 2106: main area

206: STI area

208: contact area

212: Sidewall spacer

302: Quarantine

402: Silicide barrier

404, 3404, 4502: field plate etching stop layer

406, 1502: contact etching stop layer

406u: the top surface

410, 1702: the first metal material

412, 1802: second metal material

414: Lining

418, 504, 604: the first metal wire layer

420: Flat surface

506, 606: Conductive path

704: Deep Well

706, 710: buried layer

708: Block Area

802, 2102: Base

802b: dorsal

802f: Front side surface

806: epitaxial layer

812: conductive material

816: Overlying metal wire layer

818: Electrical Path

900, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2100, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3800, 3900, 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900, 5000, 5100, 5200, 5300, 5400, 5500,, 5600, 5700, 5800, 5900, 6000, 6100, 6200, 6300, 6400, 6500, 6600, 6700, 6800, 6900 , 7000, 7100, 7200, 7300, 7400, 7500, 7600: cross-sectional view

906: top view

1002: Self-aligned drift zone

1002s, 3402s, 3502s: sidewall

1100, 3300, 7700: method

1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 3302, 3304, 3306, 3308, 3310, 3312, 3314, 3316, 3318, 7702, 7704, 7706, 7708, 7710, 7712 7714, 7716, 7718, 7720: action

1204: high energy dopant

1602: the first etchant

1604, 2702, 3003, 4604: masking layer

1606: contact opening

1608: Field Board Opening

1704, 3102, 5602, 5806: line

2002, 4102: RPO

2004: Composite etch stop layer

2006, 2008, 3704: Dielectric materials

2108: Lateral distance

2110, 3004: non-zero depth

2112, th1 : first thickness

2116, d, d1, dr, dV : distance

2120: Top view

2302, 2402: the first dielectric material

2304, 2404: second dielectric material

2306, 2406: third dielectric material

2408: Fourth Dielectric Material

3002, 4602: Etchant

3403: Interface

3408: third ILD layer

3410: Etch stop layer

3602: Metal gate structure

3604: Metal gate electrode

3606: gate dielectric

3702, 3902: cavity

5102: Sacrificial gate structure

5104: Sacrifice gate electrode

5702: Replace gate cavity

d _L1 : first lateral distance

d _L2 : second lateral distance

s : Spacing

t : thickness

th2 : second thickness

th3 : third thickness

th4 : fourth thickness

th5 : fifth thickness

w : width

When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that in accordance with standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be increased or decreased arbitrarily.

Figure 1 shows a cross-sectional view of some embodiments of the disclosed high-voltage transistor elements with field plates.

Figures 2 to 4 show cross-sectional views of some additional embodiments of the disclosed high-voltage laterally diffused MOSFET (LDMOS) element with field plates.

5 to 6 show cross-sectional views of some embodiments of the field plate bias configuration of the high voltage LDMOS element realized by metal interconnection wiring.

7A to 7C show cross-sectional views of some embodiments of high voltage LDMOS devices in different switching isolation configurations.

Figure 8 shows a cross-sectional view of a source downward high voltage transistor device with a field plate.

9A to 9B show some embodiments of the disclosed high-voltage LDMOS with field plates on the metal line layer.

Figure 10 shows some embodiments of high voltage LDMOS devices with self-aligned drift regions.

Figure 11 shows a flowchart of some embodiments of a method of forming a high voltage transistor element with a field plate.

12 to 19 show cross-sectional views illustrating some embodiments of a method of forming a high-voltage transistor element with a field plate.

Figures 20-24 show some embodiments of the disclosed high-voltage transistor elements having a composite etch stop layer defining a field plate.

25 to 32 show cross-sectional views illustrating some embodiments of a method of forming a high voltage transistor element having a composite etch stop layer defining a field plate.

Figure 33 shows a flowchart of some embodiments of a method of forming a high voltage transistor element with a composite etch stop layer defining a field plate.

Figures 34 to 39 show cross-sectional views of some embodiments of the disclosed high voltage transistor elements having a field plate etch stop structure defining a field plate, the field plate comprising A bottom surface that is vertically offset from the bottom surface of the conductive contact.

40 to 50 show cross-sectional views illustrating some embodiments of a method of forming a high-voltage transistor element having a field plate etch stop structure defining a field plate, the field plate including a conductive contact from the bottom The bottom surface where the surface is offset vertically.

Figures 51 to 65 show cross-sectional views illustrating some additional embodiments of a method of forming a high-voltage transistor element having a field plate etch stop structure defining a field plate, the field plate including a conductive contact The bottom surface that is vertically offset from the bottom surface.

66 to 76 show cross-sectional views illustrating some additional embodiments of a method of forming a high-voltage transistor element having a field plate etch stop structure defining a field plate, the field plate including a conductive contact The bottom surface that is vertically offset from the bottom surface.

FIG. 77 shows a flowchart of some embodiments of a method of forming a high voltage transistor element having a field plate etch stop structure defining a field plate, the field plate including a vertical offset from the bottom surface of the conductive contact The bottom surface.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are directly formed or arranged in contact, and may also include additional features. An embodiment in which the first feature and the second feature are formed or arranged so that the first feature and the second feature may not directly contact. In addition, the present invention may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the various embodiments and/or configurations discussed. The relationship between the settings.

In addition, for ease of description, for example, "below", "below", "lower", "above", Spatial relative terms such as "upper" describe the relationship of one component or feature relative to another component or feature as shown in the figure. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can also be interpreted accordingly.

High-voltage transistor elements are usually constructed with field plates. The field plate is a conductive member placed above the channel region to improve the performance of the high voltage transistor element by manipulating the electric field generated by the gate electrode (for example, reducing the peak electric field). By manipulating the electric field generated by the gate electrode, the high-voltage transistor element can achieve a higher breakdown voltage. For example, a laterally diffused metal oxide semiconductor (LDMOS) transistor element usually includes a field plate that extends from the channel region to the adjacent drift disposed between the channel region and the drain region. Area.

The field plates can be formed in a number of different ways. For example, a conductive gate material (such as polysilicon) can be extended from the gate electrode toward the drift region to form a field plate. However, in this type of configuration, the field plate is synchronized with the gate bias voltage, which _{puts a burden on the gate-drain capacitance (C gd} ) and deteriorates the switching loss of the element. Alternatively, the conductive gate material can be patterned to form spaced field plates. This type of configuration reduces the gate-drain capacitance (C _gd ), but the placement of the field plate is often limited by design rules. In yet another alternative, non-gate materials can be used for field plate formation. However, this type of solution uses additional processing steps, increasing the manufacturing cost of the resulting integrated wafer.

Therefore, the present disclosure relates to high-voltage electric field plates with field plates made of non-gate Piezoelectric crystal elements, high-voltage transistor elements and back-end-of-the-line (BEOL) metal layers are formed at the same time to realize a low-cost manufacturing method. In some embodiments, the high-voltage transistor element has a gate electrode, and the gate electrode is disposed above the substrate, between the source region and the drain region positioned in the substrate. The dielectric layer extends laterally from above the gate electrode to a drift region arranged between the gate electrode and the drain region. The field plate is located in the first inter-level dielectric (ILD) layer of the overlying substrate. The field plate extends laterally from above the gate electrode to above the drift region and vertically from the dielectric layer to the top surface of the first ILD layer. A plurality of metal contacts having the same material as the field plate extends vertically from the bottom surface of the first ILD layer to the top surface of the first ILD layer.

FIG. 1 shows a cross-sectional view of some embodiments of a high voltage transistor element 100 with a field plate 122.

The high-voltage transistor device 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 have a second doping type, and the doping concentration is higher than that of the semiconductor substrate 102. In some embodiments, the first doping type may be p-type doping and the second doping type may be n-type doping.

The gate structure 116 is arranged above the semiconductor substrate 102 in a position laterally arranged between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. When receiving a bias voltage, the gate electrode 108 is configured to generate an electric field, and the electric field controls the movement of charge carriers in the channel region 112 which is laterally arranged between the source region 104 and the drain region 106. For example, during operation, a gate-source voltage (V _GS ) can be selectively applied to the gate electrode 108 associated with the source region 104 to form a conductive channel in the channel region 112. Although V _GS is applied to form a conductive channel, a drain to source voltage (V _DS ) is applied to move charge carriers between the source region 104 and the drain region 106 (for example, as indicated by the arrow 105).

The channel region 112 extends laterally from the source region 104 to the adjacent drift region 114 (ie, the drain extension region). The drift region 114 includes a second doping type having a relatively low doping concentration, which provides a higher resistance at a high operating voltage. The gate structure 116 is disposed above the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position overlying a portion of the drift region 114.

The first interlayer dielectric (ILD) layer 118 is disposed on the semiconductor substrate 102. One or more conductive metal structures are disposed in the first ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 configured to provide a source region 104, a drain region 106 or a gate electrode 108 and an overlying first ILD layer The vertical connection between the first back end of line (BEOL) metal line layer 128 in the second ILD layer 126 of 118.

The one or more conductive metal structures may also include a field plate 122 disposed in the first ILD layer 118 at a position overlying the gate electrode 108 and the portion of the drift region 114. The field plate 122 includes the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed above the dielectric layer 124 configured to separate the field plate 122, the drift region 114, and the gate electrode 108. In some embodiments, the dielectric layer 124 extends laterally beyond the field plate 122 in one or more directions.

During operation, the field plate 122 is configured to act on the electric field generated by the gate electrode 108. The field plate 122 may be configured to change the distribution of the electric field generated by the gate electrode 108 in the drift region 114, which enhances the internal electric field of the drift region 114 and improves the drift. The offset doping concentration of the region 114 thereby enhances the breakdown voltage capability of the high voltage transistor 100.

FIG. 2 shows a cross-sectional view of some additional embodiments of the disclosed high voltage transistor element including a high voltage lateral diffused MOSFET (LDMOS) element 200 with a field plate 214.

The LDMOS device 200 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping, and the source region 104 and the drain region 106 include highly doped regions having a second doping type different from the first doping type. In some embodiments, the first doping type may be n-type doping and the second doping type may be p-type doping. In some embodiments, the source region 104 and the drain region 106 may have a doping concentration in the range of ^{about 10 19} cm ⁻³ and about 10 ²⁰ cm ^−3.

The contact region 208 (eg, “p-type contact” (p-tap) or “n-type contact” (n-tap)) having the first doping type (eg, p+ doping) laterally adjoins the source region 104. The contact area 208 provides an ohmic connection for the semiconductor substrate 102. In some embodiments, the contact region 208 may have a p-type doping concentration in the range of ^{about 10 18} cm ⁻³ and about 10 ²⁰ cm ^−3. The contact region 208 and the source region 104 are arranged in the body region 202. The body region 202 has a first doping type with a higher doping concentration than the semiconductor substrate 102. For example, the semiconductor substrate 102 may have ^{a doping concentration ranging between about 10 14} cm ^-3 and about 10 ¹⁶ cm ^-3 , and the body region 202 may have a doping concentration ranging between about 10 ¹⁶ cm -3 and about 10 ^{18 cm -3.} The doping concentration in the range of cm ^-3.

The drain region 106 is disposed in the drift region 204, and the drift region is disposed in the semiconductor substrate 102 at a position laterally adjacent to the body region 202. The drift region 204 includes a second doping type having a relatively low doping concentration, which provides a higher resistance when the LDMOS device 200 is operated at a high operating voltage. In some embodiments, the drift region 204 may have a doping concentration in the range of ^{about 10 15} cm ^-3 and about 10 ¹⁷ cm ^-3.

The gate structure 210 is arranged above the semiconductor substrate 102 in a position laterally arranged between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend from above the body region 202 to a position overlying a portion of the drift region 204. The gate structure 210 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may include silicon dioxide (SiO ₂ ) or a high-k gate dielectric material, and the gate electrode 108 may include polysilicon or a metal gate material (such as aluminum). In some embodiments, the gate structure 210 may further include sidewall spacers 212 disposed on opposite sides of the gate electrode 108. In various embodiments, the sidewall spacers 212 may include nitride-based sidewall spacers (for example, including SiN) or oxide-based sidewall spacers (for example, SiO ₂ , SiOC, etc.).

One or more dielectric layers 124 are disposed above the gate electrode 108 and the drift region 204. In some embodiments, the one or more dielectric layers 124 continuously extend from above a portion of the gate electrode 108 to above a portion of the drift region 204. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 204, the gate electrode 108, and the sidewall spacers 212.

The field plate 214 is disposed above the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from above the gate electrode 108 to above the drift region 204. The size of the field plate 214 may be different according to the size and characteristics of the LDMOS device 200. In some embodiments, the field plate 214 may have a size between about 50 nanometers and about 1 micrometer. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may include a relatively low dielectric constant (e.g. For example, a dielectric material less than or equal to about 3.9), which provides electrical isolation between the plurality of contacts 120 and/or the field plate 122. In some embodiments, the first ILD layer 118 may include an ultra-low-k dielectric material or a low-k dielectric material (such as SiCO).

The field plate 214 extends vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plate 214 may extend vertically to a height greater than or equal to the height of the contact 120 and the top surface of the first ILD layer 118. The field plate 122 has a non-flat surface adjacent to one or more dielectric layers 124. The uneven surface causes the field plate 122 to have a first thickness t ₁ in the region above the gate electrode 108 and a second thickness t ₂ greater than the first thickness t ₁ in the region overlying the drift region 204.

The plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120 a coupled to the contact region 208, a second contact 120 b coupled to the drain region 106, and a third contact 120 c coupled to the gate electrode 108. In some embodiments, the first contact 120 a may include abutting contacts (not shown) that contact both the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may include the same metal material. For example, the plurality of contacts 120 and the field plate 122 may include tungsten (W), tantalum-nitride (TaN), titanium (Ti), titanium-nitride (TiN) One or more of aluminum copper (AlCu), copper (Cu) and/or other similar conductive materials.

FIG. 3 shows a cross-sectional view of some additional embodiments of the disclosed high-voltage LDMOS device 300 with a field plate 214.

The LDMOS device 300 includes an isolation region 302 arranged in the drift region 204 at a position laterally arranged between the gate structure 210 and the drain region 106. The isolation region 302 improves the isolation between the gate structure 210 and the drain region 106 in order to prevent The dielectric breakdown between the gate structure 210 and the drift region 204 when the LDMOS device 300 is operated at a large operating voltage. For example, the isolation region 302 can be introduced into the drift region 204 of the LDMOS device to increase the breakdown voltage of the LDMOS device 300 without significantly changing the manufacturing process of the LDMOS device, which is designed to operate at the breakdown voltage . In some embodiments, the isolation region 302 may include shallow trench isolation (STI). In other embodiments, the isolation region 302 may include a field oxide.

FIG. 4 shows a cross-sectional view of some additional embodiments of the disclosed high voltage LDMOS device 400 with a field plate 408.

The LDMOS device 400 includes a plurality of dielectric layers (402-404) arranged between the field plate 122 and the gate structure 210 and/or the drift region 204. The plurality of dielectric layers (402-404) are configured to electrically isolate the field plate 408 from the gate structure 210 and/or the drift region 204. In an embodiment, the plurality of dielectric layers (402-404) may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers (402-404) may include one or more dielectric layers used during a typical CMOS manufacturing process. In order to limit the additional manufacturing steps used to electrically isolate the field plate 408 from the gate structure 210 and/or the drift region 204.

For example, the plurality of dielectric layers (402-404) may include a silicide barrier layer 402. In some embodiments, the silicide barrier layer 402 may include a resist-protection oxide (RPO) layer configured to prevent the formation of silicide. The silicide barrier layer 402 may be disposed over the gate electrode 108 and the part of the drift region 204. In some embodiments, the silicide barrier layer 402 may continuously extend from above the gate electrode 108 to above the drift region 204.

In some embodiments, the plurality of dielectric layers (402-404) may also include field Etch stop layer (ESL) 404. The field plate ESL 404 may be disposed above the silicide barrier layer 402 and configured to control the etching of the opening of the field plate 408. The field plate ESL 404 may consider the difference in etching depth between the contact 120 and the field plate 408, and/or the difference in etching rate (eg, due to etching load effects). In some embodiments, for example, the field plate ESL 404 may include a silicon nitride (SiN) layer.

In some alternative embodiments (not shown), the plurality of dielectric layers (402-404) may additionally or alternatively include gate dielectric layers. In such an embodiment, the gate dielectric layer may be arranged laterally adjacent to the gate structure 210 at a position overlying the drift region 204. In some embodiments, the dielectric layer oxide may include silicon dioxide (eg, SiO ₂ ) or a high-k gate dielectric material. In still other embodiments, the plurality of dielectric layers (402-404) may additionally or alternatively include an ILD layer (e.g., the first ILD layer 118).

A contact etch stop layer (CESL) 406 is disposed on the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, the CESL 406 extends above the semiconductor substrate 102 at a position between the plurality of contacts 120 and the field plate 408 such that the CESL 406 abuts the sidewalls of the plurality of contacts 120 and the field plate 408. The CESL 406 covers the gate structure 210. In some embodiments, the CESL 406 may also be overlying multiple dielectric layers (402-404). In other embodiments, one or more of the plurality of dielectric layers (402-404) (for example, the field plate ESL 404) may overly the CESL 406. In some embodiments, CESL 406 may include a nitride layer. For example, CESL 406 may include silicon nitride (SiN).

The field plate 408 is disposed within the first ILD layer 118 and abuts the CESL 406 and one or more of the plurality of dielectric layers (402-404). In some embodiments, the field plate 408 extends through the CESL 406 to abut one or more of the plurality of dielectric layers (402-404). In such embodiments, one or more of the plurality of dielectric layers (402-404) make the field The plate 408 is separated from the gate structure 210 and the drift region 204.

In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The first metal material 410 may include a gel layer disposed along the outer edge of the field plate 408, and the second metal material 412 is embedded in the first metal material 410 in the inner region of the field plate 408 (ie, the second metal material 412 passes through The first metal material 410 is separated from the CESL 406). In some embodiments, the liner layer 414 may be disposed between the first ILD layer 118 and the first metal material 410.

In some embodiments, the first metal material 410 disposed along the outer edge of the field plate 408 has a top surface arranged along a substantially planar surface 420 (ie, a planar surface formed by a planarization process). The flat surface 420 may be aligned with the top surface of the plurality of contacts 120. In some embodiments, the first metal material 410 includes the same material as the plurality of contacts 120, and the second metal material 412 includes the same material as the first metal wire layer 418 overlying the plurality of contacts 120. For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

It should be understood that due to its integration with the back end of line (BEOL) metallization layer, the disclosed field plate allows various field plate bias configurations that are easily available due to different design considerations. For example, the field plate bias voltage can be changed by changing the metal wiring layer instead of changing the design of the disclosed high-voltage element. In addition, it should be understood that biasing high-voltage transistor components through BEOL metal interconnect wiring allows the integration of various field plate bias configurations on the same wafer using a single manufacturing process flow.

Figures 5 to 6 show cross-sectional views of some embodiments of field plate bias configurations for high voltage transistor elements implemented by BEOL metal interconnect wiring. although 5 to 6 show the connection between the field plate 214 and the contact area 208 or the gate electrode 108 by means of the first metal line layer (for example, 504 or 604), but the BEOL metal interconnection wiring is not limited thereto. In fact, it should be understood that the field plate 214 can be connected to the source region, the gate electrode by any combination of BEOL metal interconnection layers (for example, the first metal line layer, the first metal via layer, the second metal wire layer, etc.) Electrodes, drain regions or bulk contacts.

FIG. 5 shows a cross-sectional view of a high voltage LDMOS element 500 in which the field plate 214 is electrically coupled to the contact area 208 along the conductive path 506. The field plate 214 is connected to the first metal line layer 504 and is disposed in the second ILD layer 502. The first metal line layer 504 is coupled to the first contact 120 a adjacent to the contact area 208. By electrically coupling the field plate 214 to the contact area 208, the field plate 214 is biased by the source voltage. The source voltage bias field plate 214 provides the high-voltage LDMOS element 500 with low on-state resistance Rds(on) and low dynamic power dissipation (for example, low Rds(on)*Qgd vs. BV). Low dynamic power dissipation provides good performance during high frequency switching applications.

FIG. 6 shows a cross-sectional view of a high voltage LDMOS device 600 in which the field plate 214 is electrically coupled to the gate electrode 108 along a conductive path 606. The field plate 214 is connected to the first metal line layer 604 and is disposed in the second ILD layer 602. The first metal wire layer 604 is connected to the second contact 120 b adjacent to the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by the gate voltage. The high voltage LDMOS device 600 is provided with a low Rds(on) vs. breakdown voltage through the gate voltage bias field plate 214.

Multiple field plate bias configurations allow the disclosed field plate to form a universal high voltage transistor element that can be used in different applications. For example, the on-state resistance Rds(on) of the high-voltage transistor element with the gate bias field plate is lower than the Rds(on) of the high-voltage transistor element with the source bias field plate. However, the high-voltage field plate with source bias The Rds(on))*Qgd of the piezoelectric crystal element is lower than the Rds(on))*Qgd of the high-voltage transistor element with a gate node bias field plate. Therefore, high-voltage transistor elements with gate bias field plates (e.g., high-voltage LDMOS element 500) can be used in low-frequency switching applications (e.g., below 10 MHz), while those with source bias field plates High voltage transistor elements (for example, high voltage LDMOS element 600) can be used in high frequency switching applications (for example, higher than 10 MHz).

7A to 7C show cross-sectional views of some embodiments of high voltage LDMOS devices 700a-700c in different switching isolation configurations.

As shown in FIG. 7A, the high-voltage LDMOS element 700a is configured as a low-side switch (for example, a switch connected to ground in an inverter). In this type of configuration, the high-voltage LDMOS element 700a has a source region 104 that floats during the switching period so that the voltage on the source region 104 can be changed.

As shown in FIG. 7B, the high-voltage LDMOS element 700b is configured as a high-side switch (for example, _{a switch connected to V DD in} an inverter). In this type of configuration, the high voltage LDMOS element 700b has the source region 104 connected to the source voltage. The high voltage LDMOS element 700b has a drift region 702 that extends below the body region 202 to prevent the source The pole voltage rises above the base voltage.

As shown in FIG. 7C, the high voltage LDMOS device 700c is completely isolated from the substrate to allow independent biasing. The high voltage transistor element 700c includes a deep well 704 and a counter-doped underlying buried layer 706 configured to provide vertical isolation. In some embodiments, the deep well 704 may have a first doping type (for example, the same doping type as the body region 202), and the buried layer 706 may have a second doping type.

The high-voltage LDMOS device 700c further includes one or more additional STI regions 206 laterally separating the drain region from the bulk region 708 and a buried layer 710 having a second doping type. The bulk region 708 overlies the deep well 704, and the buried layer 710 overlies the well region 712 having the second first doping type and is adjacent to the buried layer 706. The contact 120 is configured to provide a bias voltage to the bulk region 708 and the buried layer 710 so as to form junction isolation between the deep well 704 and the buried layer 706 and the well region 712. Junction isolation allows the fully isolated high voltage LDMOS element 700c to operate within a series of bias voltages.

FIG. 8 shows a cross-sectional view of a source-down high-voltage transistor element 800 with a field plate 214.

The high-voltage transistor element 800 includes a substrate 802 of a first doping type (for example, a p+ doping type) with a high doping concentration. The source region 804 is disposed along the backside 802b of the substrate 802. In various embodiments, the source region 804 may include a highly doped region or a metal layer. The epitaxial layer 806 having the first conductivity type is disposed on the front surface 802f of the substrate 802. The dopant concentration of the epitaxial layer 806 is less than the dopant concentration of the substrate 802. The source contact region 810, the drain region 106, the body region 808, and the drift region 204 are disposed in the top surface of the epitaxial layer 806.

The conductive material 812 extends from the top surface of the epitaxial layer 806 to the substrate 802. The conductive material 812 may include a highly doped deep well region. The conductive material 812 allows source connections to be made from the backside of the substrate 802, thereby reducing the complexity of metal wiring and achieving various package compatibility. In some embodiments, the field plate 214 may be biased by a source voltage by means of an electrical path 818 extending through a contact 814 adjacent to the conductive material 812 and an overlying metal line layer 816 coupled to the field plate 214.

9A to 9B show some embodiments of the disclosed high-voltage LDMOS device having a field plate 902 in the metal line layer. Although Figures 9A to 9B show the field board It is shown on the first metal line layer, but it should be understood that the disclosed field plate is not limited to the first metal line layer, but can actually be implemented on an alternative layer of the BEOL metallization stack.

As shown in the cross-sectional view 900 of FIG. 9A, the field plate 902 is disposed in the first metal line layer, within the second ILD layer 904 overlying the first ILD layer 118. In some embodiments, the field plate 902 has substantially flat top and bottom surfaces in order to provide the field plate 902 with a flat profile. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by means of the first ILD layer 118. The field plate 902 covers portions of the gate electrode 108 and the drift region 204 and is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 may be laterally separated from the drain region 106 by a distance d. In some embodiments, the field plate 902 may extend laterally from above the gate electrode 108 to above the drift region 204.

As shown in the top view 906 of FIG. 9B, the field plate 902 includes a metal structure overlying portions of the gate electrode 108 and the drift region 204. The metal structure is not connected to the underlying member or to another metal structure on the first metal line layer by means of the contact 120. In effect, the metal structure will be connected to an overlying via (not shown) that is configured to connect the field plate to an overlying metal line layer that biases the field plate 902.

FIG. 10 shows some embodiments of the disclosed high-voltage LDMOS device 1000 with a self-aligned drift region 1002.

The self-aligned drift region 1002 has sidewalls 1002s that are substantially aligned with the sidewalls of the gate electrode 108 and the gate dielectric layer 110. In some alternative embodiments, the self-aligned drift region 1002 may be formed to have sidewalls 1002s that are substantially aligned with the edges of the sidewall spacers 212. By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 is laterally separated from the body region 202 by the spacing s, thereby minimizing the gate-drain The poles overlap and achieve low gate-drain charge (Qgd) and good high-frequency performance. The field plate 214 overlying the self-aligned drift region 1002 can further reduce the gate-drain charge (Qgd).

FIG. 11 shows a flowchart of some embodiments of a method 1100 of forming a high voltage transistor element with a field plate. The method can form the field plate using process steps that have been used during the standard CMOS manufacturing process, and thus can provide a low-cost universal field plate.

Although the disclosed methods (for example, method 1100, method 3300, and method 7700) are illustrated and described herein as a series of actions or events, it should be understood that the illustrated sequence of such actions or events should not be interpreted in a restrictive sense . For example, in addition to the actions or events illustrated and/or described herein, some actions may occur in a different order and/or simultaneously with other actions or events. In addition, not all of the illustrated actions may be required to implement one or more aspects or embodiments described herein. Furthermore, one or more of the actions described herein may be performed in one or more separate actions and/or stages.

At act 1102, a substrate is provided, the substrate having a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region located between the source region and the drain region and adjacent to the channel region.

At action 1104, the gate structure is formed above the substrate in a position arranged between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.

At act 1106, the drift region may be formed using a self-aligned process, which in some embodiments is selectively implanted in the semiconductor substrate according to the gate structure to form the drift region.

At act 1108, one or more dielectric layers are selectively formed on the gate Above the electrode and part of the drift zone.

At act 1110, a contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are formed over the substrate.

At act 1112, the first ILD layer is selectively etched to define contact openings and field plate openings.

At act 1114, the contact opening and the field plate opening are filled with the first metal material.

At act 1116, a planarization process may be performed to remove the excess first metal material overlying the first ILD layer.

At act 1118, a second metal material corresponding to the first metal line layer is deposited. In some embodiments, the second metal material may further fill the field plate opening. In such embodiments, the second metal material is embedded in the first metal material in the opening of the field plate.

At act 1120, a second interlayer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.

Figures 12 to 19 show cross-sectional views illustrating some embodiments of a method of forming a MOSFET element with a field plate. Although FIGS. 12 to 19 are described with respect to the method 1100, it should be understood that the structure disclosed in FIG. 12 to FIG. 19 is not limited to this method, and may actually be used as a method independent structure alone.

FIG. 12 shows some embodiments of a cross-sectional view 1200 corresponding to action 1102.

As depicted in the cross-sectional view 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be substantially doped with the first doping type. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., silicon, SOI), The semiconductor body of any type includes, but is not limited to, semiconductor dies or wafers or one or more dies on the wafer, as well as any other types of semiconductors and/or formed thereon and/or otherwise associated therewith Epitaxial layer.

Various implantation steps can be used to selectively implant the semiconductor substrate 102 to form multiple implanted regions (eg, well regions, contact regions, etc.). For example, the semiconductor substrate 102 can be selectively implanted to form the body region 202, the drift region 204, the source region 104, the drain region 106, and the contact region 208. The semiconductor substrate 102 can be selectively shielded (for example, using a photoresist mask), and then a high-energy dopant 1204 (for example, a p-type dopant substance such as boron or an n-type dopant such as phosphorus) is introduced Into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions. For example, as shown in the cross-sectional view 1200, the shielding layer 1202 is selectively patterned to expose a portion of the semiconductor substrate 102, and then a high-energy dopant 1204 is implanted into the exposed portion to form the source region 104 And the drain region 106.

It should be understood that the implantation region shown in the cross-sectional view 1200 is an example of a possible implantation region, and the semiconductor substrate 102 may include other configurations of the implantation region, for example, as shown in FIGS. 1 to 10 Any one of the configured configurations, FIG. 13 shows some embodiments of a cross-sectional view 1300 corresponding to action 1104.

As shown in the cross-sectional view 1300, the gate structure 210 is formed above the semiconductor substrate 102 in a position arranged between the source region 104 and the drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 on the semiconductor substrate 102 and by forming a gate electrode material 108 on the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by a vapor deposition technique. Then the gate dielectric layer 110 and the gate electrode material The material 108 is patterned and etched (for example, according to a photoresist mask) to define the gate structure 210. In some embodiments, the sidewall spacers 212 may be formed on the opposite side of the gate electrode 108 by depositing nitride-based materials or oxide-based materials on the semiconductor substrate 102, and selectively etching the nitride-based materials. Materials or oxide-based materials to form the sidewall spacers 212.

FIG. 14 shows some embodiments of a cross-sectional view 1400 corresponding to action 1108.

As shown in the cross-sectional view 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by vapor deposition techniques, and then patterned and etched (eg, according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of the gate electrode 108 and be laterally spaced from the drain region 106.

In some embodiments, the one or more dielectric layers 124 may include a silicide barrier layer, such as a photoresist protective oxide (RPO) layer. In other embodiments, the one or more dielectric layers 124 may additionally and/or alternatively include a field plate etch stop layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by vapor deposition technology. In still other embodiments, the one or more dielectric layers 124 may additionally and/or alternatively include a gate dielectric layer or an interlayer dielectric (ILD) layer.

FIG. 15 shows some embodiments of a cross-sectional view 1500 corresponding to action 1110.

As shown in the cross-sectional view 1500, a contact etch stop layer (CESL) 1502 is formed over the semiconductor substrate 102. In some embodiments, CESL 1502 may be formed by a vapor deposition process. The first interlayer dielectric (ILD) layer 1504 is subsequently formed in Above CESL 1502. In some embodiments, the first ILD layer 1504 may include an ultra-low-k dielectric material or a low-k dielectric material (such as SiCO). In some embodiments, the first ILD layer 1504 may also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin coating process. It should be understood that the term inter-layer dielectric (ILD) layer as used herein may also refer to an inter-metal dielectric (IMD) layer.

FIG. 16 shows some embodiments of a cross-sectional view 1600 corresponding to action 1112.

As shown in the cross-sectional view 1600, the first ILD layer 1504 is selectively exposed to a first etchant 1602 configured to form a contact opening 1606 and a field plate opening 1608. In some embodiments, the contact opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to the first etchant 1602 according to the shielding layer 1604 (for example, a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have greater etching selectivity between the first ILD layer 1504 and the field plate ESL in the one or more dielectric layers 124. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have an etching chemical substance including oxygen (oxygen; O ₂ ), nitrogen (nitrogen; N ₂ ), hydrogen (hydrogen; H ₂ ), and argon (argon; Ar) and/or one or more of fluorine substances (for example, CF ₄ , CHF ₃ , C ₄ F _8, etc.). In other embodiments, the first etchant 1602 may include a wet etchant including buffered hydroflouric acid (BHF).

FIG. 17 shows some embodiments of a cross-sectional view 1700 corresponding to actions 1114 to 1116.

As shown in the cross-sectional view 1700, the contact opening 1606 and the field plate opening 1608 is filled with a first metal material 1702. In some embodiments, the first metal material 1702 may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the first metal material 1702 may be formed by depositing a seed layer by means of physical vapor deposition followed by a plating process (for example, an electroplating or electroless plating process). Then, a planarization process (such as chemical mechanical planarization) may be performed to remove the excess first metal material 1702 and form a flat surface along the line 1704.

In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the diffusion barrier layer and/or the liner layer may be deposited into the contact opening 1606 and the field plate opening 1608 before the first metal material 1702 is deposited.

FIG. 18 shows some embodiments of a cross-sectional view 1800 corresponding to action 1118.

As shown in the cross-sectional view 1800, a second metallic material 1802 is deposited. The second metal material 1802 is formed in the remaining openings in the field plate openings and above the first ILD layer 118. In some embodiments, the second metal material 1802 may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the second metal material 1802 may be formed by depositing a seed layer by means of physical vapor deposition followed by a plating process. In some embodiments, the second metal material 1802 may include copper (Cu) or aluminum copper (AlCu) alloy.

After formation, the second metal material 1802 can be selectively patterned to define one or more metal structures of the first metal line layer 418 overlying the first ILD layer 118. In some embodiments, the second metal material 1802 may be formed by forming a patterned masking layer (for example, a photoresist layer or a hard mask layer) (not shown) over the second metal material 1802 and subsequently patterning The second metal is etched in the exposed area of the chemical masking layer The material 1802 is selectively patterned.

FIG. 19 shows some embodiments of a cross-sectional view 1900 corresponding to action 1120.

As shown in the cross-sectional view 1900, the second ILD layer 416 is formed over the one or more metal structures of the first ILD layer 118 and the first metal line layer 418. In various embodiments, the second ILD layer 416 may be formed by depositing a second ILD material over one or more metal structures of the first ILD layer 118 and the first metal line layer 418. After the second ILD layer 416 is formed, a planarization process (for example, CMP) is performed to remove the excess second ILD layer 416 and expose the top surface of one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may include an ultra-low-k dielectric material or a low-k dielectric material (for example, SiCO) formed by a vapor deposition processor or a spin coating process.

It is understood that the height difference between the multiple contacts (for example, the contact 120) and the field plate (for example, the field plate 122) may cause difficulties during the manufacturing of the disclosed transistor element. For example, since the field plate (e.g., field plate 122) is formed over the dielectric layer 124 (e.g., photoresist protective oxide), the field plate (e.g., field plate 122) has more contacts (e.g., The contact 120) has a smaller height. However, the field plate (for example, the field plate 122) and the plurality of contacts (for example, the contact 120) are formed using the same etching process. The height difference can cause over-etching of the field plate opening (for example, the field plate opening 1608 of FIG. 16), which causes a short circuit between the field plate (for example, the field plate opening 122) and the conductive channel of the transistor element; or Leading to insufficient etching of the contact opening (for example, the contact opening 1606 of FIG. 16), which causes a plurality of contacts (for example, the contact 120) and the source region (for example, the source region 104), the drain region ( For example, poor connection between the drain region 106) and/or the gate region (eg, the gate region 116).

In order to prevent excessive etching of the field plate openings or insufficient etching of the contact openings, in some embodiments, a composite etch stop layer may be used to control the etching depth of the field plate openings. By controlling the etching depth of the field plate opening, the composite etch stop layer allows the multiple contacts (for example, contact 120) and the field plate (for example, field plate 122) to be accurately formed to different heights.

Figure 20 shows a cross-sectional view of some embodiments of a high voltage transistor element 2000 with a composite etch stop layer defining a field plate.

The high-voltage transistor device 2000 includes a gate structure 116 disposed on the semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, the gate structure 116 may have a first thickness th ₁ in the range of about 1000 angstroms and about 2000 angstroms. The source region 104 and the drain region 106 are disposed within the semiconductor substrate 102 on opposite sides of the gate structure 116.

The photoresistive protective oxide (RPO) 2002 is arranged above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 to laterally exceed the outermost sidewall of the gate structure 116. In some embodiments, the RPO 2002 may extend vertically from the upper surface of the gate structure 116 to the upper surface of the semiconductor substrate 102, and extend laterally from directly above the gate structure 116 to between the gate structure 116 and the drain region 106. between. In some embodiments, RPO 2002 may include silicon dioxide, silicon nitride, and the like. In some embodiments, the RPO 2002 may have a second thickness th ₂ in the range of about 100 angstroms and about 1000 angstroms.

The composite etch stop layer 2004 is arranged above the RPO 2002. In some embodiments, the composite etch stop layer 2004 directly contacts one or more upper surfaces of the RPO 2002. The first interlayer dielectric (ILD) layer 118 and the field plate 122 are arranged above the composite etch stop layer 2004. The first ILD layer 118 surrounds the field plate 122 and the plurality of contacts 120, The multiple contacts are coupled to the source region 104, the drain region 106 and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include a diffusion barrier (not shown) surrounding a conductive core including one or more metals.

The composite etch stop layer 2004 includes a plurality of different dielectric materials 2006 to 2008 stacked on the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have outermost sidewalls that are substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have the outermost sidewalls that are substantially aligned with the outermost sidewalls of the RPO 2002. In such embodiments, the RPO 2002 has a first width that is substantially equal to the second width of the composite etch stop layer 2004. The plurality of different dielectric materials 2006 to 2008 have different etching properties, and the different etching properties provide corresponding dielectric materials in the plurality of different dielectric materials 2006 to 2008 with different etching selectivities to the etchant. The different etch selectivity allows the composite etch stop layer 2004 to slowly etch the field plate opening (ie, the opening that defines the field plate 122), and thus at the same time, tightly control the height of the field plate and realize the contact between the multiple contacts 120 and the field plate 122. The height difference (e.g., enabling the plurality of contacts 120 to have a greater height than the field plate 122).

For example, in some embodiments, the bottom of the field plate 122 is vertically higher than one or more of the plurality of contacts 120 (eg, the contacts coupled to the source region 104 and the drain region 106) The interface of the bottom surface comes into contact with the composite etch stop layer 2004. In such embodiments, during the manufacture of the high voltage transistor element 2000, the composite etch stop layer 2004 reduces the etching rate of the etchant used to form the field plate openings (ie, the openings that define the field plate 122). The reduction in the etching rate causes the field plate 122 to have a bottom surface higher than the bottom surface of one or more of the plurality of contacts 120.

In some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 directly contacting the upper surface of the RPO 2002 and a second dielectric material 2008 directly contacting the upper surface of the first dielectric material 2006. In some embodiments, the first dielectric material 2006 may have a third thickness th ₃ , and the second dielectric material 2008 may have a fourth thickness th ₄ . In some embodiments, the RPO 2002 and the composite etch stop layer 2004 may each have a substantially constant thickness between the outermost sidewalls. If the third thickness th ₃ and the fourth thickness th _{4 are} too small (for example, less than the minimum value described below), the composite etch stop layer 2004 cannot effectively terminate the etching to form the field plate opening. If the third thickness and the fourth thickness th ₃ th ₄ is too large (e.g., greater than the maximum value set forth below), then the impact of the high voltage transistor device 2000 for reducing the field plate 122, thereby negatively affecting the device performance.

In some embodiments, the first dielectric material 2006 may include or may be silicon nitride (Si _x N _y ), and the second dielectric material 2008 may include or may be silicon dioxide (SiO ₂ ). In such embodiments, the first thickness th ₁ may be in a first range of about 50 angstroms and about 400 angstroms, and the second thickness th ₂ may be in a second range of about 150 angstroms and about 700 angstroms. In other embodiments, the first dielectric material 2006 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2008 may include or may be silicon nitride (SiN _x ) or silicon oxynitride (SiO 2) _x N _y ). In such embodiments, the first thickness th ₁ may be in a first range between about 600 angstroms and about 900 angstroms. In some embodiments, the second thickness th ₂ may be within a second range of about 100 angstroms and about 500 angstroms.

21A to 21B show some additional embodiments of the disclosed high voltage transistor device with a composite etch stop layer defining a field plate.

As shown in the cross-sectional view 2100 of FIG. 21A, the high-voltage transistor element includes a semiconductor substrate 102 having a body region 2106 disposed on the substrate In the drift zone 2104 above 2102. The source region 104 is arranged in the body region 2106, and the drain region 106 is arranged in the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (for example, n-type), and the body region 2106 and the substrate 2102 may have a first doping type opposite to the first doping type. Two-doped type (for example, p-type). In some embodiments, the source region 104 and the drain region 106 may include a highly doped region (ie, n+ region) having a higher doping concentration than the drift region 2104.

The gate structure 116 is arranged on the semiconductor substrate 102 between the source region 104 and the drain region 106. The RPO 2002 is arranged above the gate structure 116 and extends laterally beyond the outermost sidewall of the gate structure 116. The composite etch stop layer 2004 is arranged between the RPO 2002 and the field plate 122. In some embodiments, the RPO 2002 may enclose the field plate 122 (ie, extend beyond the outermost sidewall of the field plate 122) by one or more lateral distances 2108 in the range of about 0 microns and about 2 microns.

In some embodiments, the field plate 122 may extend to the non-zero depth 2110 in the composite etch stop layer 2004. In this type of embodiment, the field plate 122 contacts the sidewall of the composite etch stop layer 2004. In different embodiments, the field plate 122 may also contact the horizontally extending surface of the composite etch stop layer 2004 or the horizontally extending surface of the RPO 2002. In some embodiments, the non-zero depth 2110 may be in the range of about 400 angstroms and about 700 angstroms. Since the field plate 122 extends into the composite etch stop layer 2004, the composite etch stop layer 2004 has a first thickness 2112 directly below the field plate 122 and a second thickness greater than the first thickness 2112 outside the field plate 122. In some embodiments, the first thickness 2112 is in the range of about 0 angstroms and about 10000 angstroms. In some additional embodiments, the first thickness 2112 is between about 600 angstroms and about 300 angstroms.

As shown in the top view 2120 of FIG. 21B (along the cross-sectional line AA′ of FIG. 21A), the field plate 122 has a width 2114 that extends in the first direction in the range of about 150 nm and about 2000 nm. The distance within. The field plate 122 also has a length 2122 that extends in the second direction (perpendicular to the first direction) a distance of less than about 1000 microns.

Referring again to the cross-sectional view 2100 of FIG. 21A, in some embodiments, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116. For example, the field plate 122 may be laterally separated from the gate structure 116 by a distance 2116 in the range of about 0 nanometers and about 500 nanometers. In other embodiments (not shown), the field plate 122 may overlap the gate structure 116 laterally (ie, extend directly above the gate structure). For example, the field plate 122 may overlap the gate structure 116 laterally by a distance in the range of about 0 nanometers and about 200 nanometers.

In some embodiments, the silicide layer 2118 is disposed over the source region 104, the drain region 106, and the portion of the gate structure 116 that is not covered by the RPO 2002. In various embodiments, the silicide layer 2118 may include a compound with silicon and metals such as nickel, platinum, titanium, tungsten, magnesium, and the like. In some embodiments, the silicide layer 2118 has a thickness ranging between about 150 angstroms and about 400 angstroms.

Figure 22 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 2200 with a composite etch stop layer defining a field plate.

The high-voltage transistor element 2200 includes a gate electrode 108 arranged above the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 are above the gate electrode 108 and the semiconductor substrate 102. A contact etch stop layer (CESL) 406 is disposed above the composite etch stop layer 2004. In some embodiments, the bottom surface of the composite etch stop layer 2004 can directly contact the RPO 2002, and the top surface of the composite etch stop layer 2004 can directly contact the CESL 406. The CESL 406 laterally extends beyond the outermost sidewall of the composite etch stop layer 2004 and contacts the semiconductor substrate 102. In some embodiments, the CESL 406 may have a thickness th ₅ in the range of about 100 angstroms and about 1000 angstroms. In some embodiments, CESL 406 may include silicon nitride, silicon carbide, and the like.

The field plate 408 is disposed in the first ILD layer 118 above the CESL 406. In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The composite etch stop layer 2004 is laterally arranged between the field plate 408 and the gate structure 116 and vertically arranged between the field plate 122 and the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 have sidewalls contacting 406. The composite etch stop layer 2004 additionally has a horizontally extending surface (for example, an upper surface) that contacts the CESL 406.

In some embodiments, the field plate 122 may extend into one or more of a plurality of different dielectric materials 2006 to 2008 within the composite etch stop layer 2004. For example, in some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 contacting the upper surface of the first dielectric material 2006. The field plate 122 may extend through the second dielectric material 2008 (e.g., silicon oxide) and have a bottom surface contacting the first dielectric material 2006 (e.g., silicon nitride). In such embodiments, the second dielectric material 2008 can vertically separate the bottommost point of the field plate 122 from the RPO 2002. In other embodiments, the field plate 122 may additionally extend through the first dielectric material 2006 and have a bottom surface and/or sidewalls contacting the RPO 2002. In some embodiments, the field plate 122 may extend vertically through the second dielectric material 2008 and also be laterally separated from the gate structure 116 by the second dielectric material 2008.

Although the disclosed composite etch stop layer 2004 is shown in FIGS. 20 to 22 as having two different dielectric materials stacked on top of the RPO 2002 to the dielectric Electrical material 2008, but it should be understood that the disclosed composite etch stop layer 2004 is not limited to this type of configuration. In fact, in various embodiments, the composite etch stop layer 2004 may include an additional layer of dielectric material. Figures 23-24 show some non-limiting examples of alternative embodiments of the disclosed composite etch stop layer 2004.

Figure 23 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 2300 with a composite etch stop layer defining a field plate.

The high-voltage transistor 2300 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2302, a second dielectric material 2304 contacting the upper surface of the first dielectric material 2302, and a third dielectric material 2306 contacting the upper surface of the second dielectric material 2304. In some embodiments, the first dielectric material 2302 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2304 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), and the third dielectric material 2306 may include or may be silicon dioxide (SiO ₂ ).

In some embodiments, the first dielectric material 2302 may have a first thickness, the second dielectric material 2304 may have a second thickness, and the third dielectric material 2306 may have a third thickness. In some embodiments, the first thickness may be within a first range of about 300 angstroms and about 900 angstroms, the second thickness may be within a second range of about 50 angstroms and about 200 angstroms, and the third thickness may be between about 50 angstroms and about 200 angstroms. Within the third range of about 200 angstroms and about 600 angstroms.

Figure 24 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 2400 with a composite etch stop layer defining a field plate.

The high voltage transistor element 2400 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2402, a second dielectric material 2404 contacting the upper surface of the first dielectric material 2402, a third dielectric material 2406 contacting the upper surface of the second dielectric material 2404, and The fourth dielectric material 2408 contacts the upper surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2404 may be or may include silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), the third dielectric material 2406 may include or may be _{silicon dioxide (SiO 2} ), and the fourth dielectric material 2408 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride (SiO _x N _y ).

In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness, and the fourth dielectric material 2408 may Has a fourth thickness. In some embodiments, the first thickness may be within a first range of about 300 angstroms and about 900 angstroms, the second thickness may be within a second range of about 50 angstroms and about 200 angstroms, and the third thickness may be between about 50 angstroms and about 200 angstroms. It is within a third range of approximately 200 angstroms and approximately 600 angstroms, and the fourth thickness may be within a fourth range of approximately 50 angstroms and approximately 200 angstroms.

25 to 32 show cross-sectional views illustrating some embodiments of a method of forming a high voltage transistor element having a composite etch stop layer defining a field plate. Although referring to the cross-sectional view 2500 to the cross-sectional view 3200 shown in the method description in FIGS. 25 to 32, it should be understood that the structure shown in FIGS. 25 to 32 is not limited to the method and can actually be independently independent于说方法。 In the method.

As shown in the cross-sectional view 2500 of FIG. 25, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, optional The semiconductor substrate 102 is selectively implanted to form different implanted regions (for example, any of those implanted regions shown in FIGS. 1 to 10). In some embodiments, the semiconductor substrate 102 may be selectively shielded (for example, using a photoresist mask) and then high-energy dopants (for example, p-type dopant species such as boron or n-type such as phosphorous The dopant) is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions.

The gate structure 116 is formed on the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by depositing a gate dielectric layer 110 on the semiconductor substrate 102 and by depositing a gate electrode material 108 on the gate dielectric layer 110. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned (eg, etched according to a photoresist mask and/or a hard mask) to define the gate structure 116.

As shown in the cross-sectional view 2600 of FIG. 26, a photoresistive protective oxide (RPO) 2002 is formed over the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 beyond the outermost sidewall of the gate structure 116. RPO 2002 is configured to block the formation of silicide on the bottom layer. In some embodiments, RPO 2002 may be deposited by vapor deposition technology (eg, CVD). In some embodiments, RPO 2002 may include _{silicon dioxide (SiO 2} ), silicon nitride, and the like.

As shown in the cross-sectional view 2700 of FIG. 27, a composite etch stop layer 2004 including a plurality of different dielectric materials 2006 to 2008 is selectively formed over the RPO 2002. In some embodiments, a plurality of different dielectric materials 2006 to 2008 may be sequentially deposited by a vapor deposition technique. In some embodiments, the composite etch stop layer 2004 may include two of a silicon nitride (Si _x N _y ) layer, a silicon oxynitride (SiO _x N _y ) layer, and/or a _{silicon dioxide (SiO 2} ) layer. Or more stacked layers.

In some embodiments, a plurality of different dielectric materials 2006 to 2008 and RPO 2002 may be patterned using the same shielding layer 2702 (eg, photoresist layer) and etching process. Using the same shielding layer 2702 to pattern a plurality of different dielectric materials 2006 to 2008 and RPO 2002 reduces the cost of forming the composite etch stop layer 2004. In such embodiments, the plurality of different dielectric materials 2006 to 2008 and RPO 2002 may have substantially aligned sidewalls.

As shown in the cross-sectional view 2800 of FIG. 28, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the composite etch stop layer 2004. In some embodiments, CESL 406 may be formed by a vapor deposition process. The CESL may include a nitride layer (for example, Si ₃ N ₄ ), a carbide layer (SiC), and so on.

As shown in the cross-sectional view 2900 of FIG. 29, a first interlayer dielectric (ILD) layer 118 is formed over the CESL 406. In some embodiments, the first ILD layer 118 may include oxide (for example, SiO ₂ ), ultra-low-k dielectric material, low-k dielectric material (for example, SiCO), and so on. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.

As shown in the cross-sectional view 3000 of FIG. 30, the first ILD layer 118 is selectively exposed to an etchant 3002 (eg, according to the masking layer 3003) to form contact openings 1606 and field plate openings 1608 in the first ILD layer 118 . The contact opening 1606 and the field plate opening 1608 have an etch depth offset of a non-zero distance 3004. In some embodiments, the non-zero depth 3004 may be in the range of about 400 angstroms and about 2000 angstroms. In some embodiments, the field plate opening 1608 extends into the composite etch stop layer 2004 such that the sidewalls of the composite etch stop layer 2004 define the field plate opening 1608. In various embodiments, the composite etch stop layer 2004 or RPO 2002 may define the bottom of the field plate opening 1608.

In some embodiments, the etchant 3002 can reduce the thickness of the composite etch stop layer 2004 by an amount in the range of about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in the range of about 0 angstroms and about 1,000 angstroms. In some additional embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in the range of about 300 angstroms and about 900 angstroms.

The etchant 3002 used to form the contact opening 1606 and the field plate opening 1608 is selected to etch through the material of the CESL 406. However, since the composite etch stop layer 2004 is formed of a plurality of different materials, the composite etch stop layer 2004 can resist etching by the etchant 3002 to a higher degree. The composite etch stop layer 2004 thus allows the contact opening 1606 to extend to the semiconductor substrate 102 while preventing the field plate opening 1608 from extending to the semiconductor substrate 102. The composite etch stop layer 2004 also allows a high degree of uniformity of the etching depth at different locations on the substrate, between the same batch of substrates, and/or above the substrates of different batches. For example, the composite etch stop layer 2004 allows the etch depth of the field plate opening 1608 on different substrates to be within a deviation of about 2% or less. This etch depth uniformity allows for improved device uniformity and performance compared to devices that do not have the composite etch stop layer 2004.

As shown in the cross-sectional view 3100 of FIG. 31, the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.) and/or plating processes (eg, electroplating or electroless plating processes). Then, a planarization process (such as chemical mechanical planarization) may be performed to remove the excess conductive material or materials and form a flat surface along the line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, a diffusion barrier layer and/or liner layer may be deposited into the contact opening 1606 and the field plate opening 1608 before depositing one or more conductive materials.

As shown in the cross-sectional view 3200 of FIG. 32, the second ILD layer 126 is formed above the first ILD layer 118, and the first back end of line (BEOL) metal line layer 128 is formed in the second ILD layer 126. In various embodiments, the second ILD layer 126 may be formed by depositing a second ILD material over the first ILD layer 118. The second ILD layer 126 is then etched to form a trench extending in the second ILD layer 126. The trench is filled with conductive material, and a planarization process (for example, CMP) is performed to remove excess conductive material from above the second ILD layer 126.

Figure 33 shows a flowchart of some embodiments of a method 3300 of forming a high voltage transistor element with a composite etch stop layer defining a field plate.

At act 3302, a gate structure is formed over the substrate. FIG. 25 shows a cross-sectional view 2500 of some embodiments corresponding to act 3302.

At act 3304, the source and drain regions are formed in the substrate, on opposite sides of the gate structure. In some additional embodiments, one or more additional doped regions (for example, body regions, drift regions, etc.) may also be formed in the substrate. FIG. 25 shows a cross-sectional view 2500 of some embodiments corresponding to act 3304.

At act 3306, a photoresistive protective oxide (RPO) is formed above the gate structure and laterally between the gate structure and the drain region. FIG. 26 shows a cross-sectional view 2600 of some embodiments corresponding to act 3306.

At act 3308, a composite etch stop layer is formed over the RPO. FIG. 27 shows a cross-sectional view 2700 of some embodiments corresponding to act 3308.

At act 3310, a contact etch stop layer (CESL) is formed on the composite etch stop layer. Figure 28 shows a cross-section of some embodiments corresponding to act 3310 面图2800。 2800.

At act 3312, a first interlayer dielectric (ILD) layer is formed over CESL. Figure 29 shows a cross-sectional view 2900 of some embodiments corresponding to act 3312.

At act 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and the field plate openings have different depths. FIG. 30 shows a cross-sectional view 3000 of some embodiments corresponding to act 3314.

At act 3316, the multiple contact openings and field plate openings are filled with one or more conductive materials. Figure 31 shows a cross-sectional view 3100 of some embodiments corresponding to act 3316.

At act 3318, conductive interconnects are formed in the second ILD layer above the first ILD layer. FIG. 32 shows a cross-sectional view 3200 of some embodiments corresponding to act 3318.

Figure 34 shows a cross-sectional view of some embodiments of a high voltage transistor element 3400 with a field plate etch stop structure defining a field plate, the field plate including a bottom surface that is vertically offset from the bottom surface of the conductive contact .

The high-voltage transistor element 3400 includes a gate structure 116 arranged vertically above the semiconductor substrate 102 in a position laterally between the source region 104 and the drain region 106. In some embodiments, the semiconductor substrate 102 may further include a body region 2106 surrounding the source region 104 and/or a drift region 2104 between the body region 2106 and the drain region 106. The photoresistive protective oxide (RPO) 2002 is above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 to laterally between the gate structure 116 and the drain region 106. A contact etch stop layer (CESL) 406 is disposed on the RPO 2002, the gate structure 116, and the semiconductor substrate 102.

The dielectric structure 3401 is arranged above the CESL 406. The dielectric structure 3401 includes a first ILD layer 3402 disposed above the CESL 406, a second ILD layer 3406 above the first ILD layer 3402, and a third ILD layer 3408 above the second ILD layer 3406. In some embodiments, the first ILD layer 3402 has an uppermost surface overlying the top of the gate structure 116 with a non-zero distance d _1. In some embodiments, the second ILD layer 3406 is separated from the third ILD layer 3408 by an etch stop layer 3410. In such embodiments, the second ILD layer 3406 has a bottom surface that directly contacts the top surface of the first ILD layer 3402 and a top surface that directly contacts the bottom surface of the etch stop layer 3410. The plurality of contacts 120 extend vertically from the top surface of the second ILD layer 3406 to the lower surface of the first ILD layer 3402 (through the interface 3403 of the first ILD layer 3402 and the second ILD layer 3406). The plurality of contacts 120 are configured to contact the source region 104, the drain region 106 and the gate structure 116.

The field plate etch stop structure 3404 is disposed between the first ILD layer 3402 and the second ILD layer 3406. The bottommost surface and the topmost surface of the field plate etch stop structure 3404 are vertically between the bottom surface and the top surface of the plurality of contacts 120. In some embodiments, the field plate etch stop structure 3404 is disposed directly above the RPO 2002. In some such embodiments, the field plate etch stop structure 3404 is completely confined above the RPO 2002, while in other embodiments, the field plate etch stop structure 3404 can extend from directly above the RPO 2002 to a lateral direction between the RPO 2002 and the RPO 2002. Between the polar regions 106. In some embodiments, the field plate etch stop structure 3404 may have relatively outermost sidewalls laterally between the gate structure 116 and the drain region 106. For example, field plate etch stop structure 3404 may have a first lateral separation distance d _L1 and the gate structure 116 of the external sidewalls of the first and second most opposing lateral distance d _L2 and drain regions 106 separated Two outermost side walls. In other embodiments, the field plate etch stop structure 3404 may extend to directly above the gate structure 116 and/or the drain region 106.

The field plate 122 is disposed on the field plate etch stop structure 3404. The field plate 122 includes the same material as the plurality of contacts 120 (for example, tungsten, cobalt, etc.). The bottommost surface of the field plate 122 is vertically between the bottom surface and the top surface of the plurality of contacts 120. For example, the bottommost surface of the field plate 122 may be arranged along a horizontal plane 3405 that is parallel to the upper surface of the substrate 102 and extends through the side walls of the plurality of contacts 120. The bottom surface of the field plate 122 by a distance d _V and the semiconductor substrate 102 separated. In some embodiments, the distance d _V has a value between about 400 angstroms and about 700 angstroms. 3400 element high voltage transistor breakdown voltage is proportional to the distance d _V. For example, as the distance d _V decreases, the breakdown voltage of the high-voltage transistor 3400 also decreases.

The field plate etch stop structure 3404 includes a material having a high etch selectivity with respect to the first ILD layer 3402 and the second ILD layer 3406. For example, in various embodiments, the field plate etch stop structure 3404 may include silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), amorphous silicon (a-Si), hafnium oxide (HfO _x ), zirconium oxide (ZrO _x ), metal oxides and so on. In various embodiments, the field plate etch stop structure 3404 may have a thickness t in the range of about 1 nanometer and about 100 nanometers. In various embodiments, the field plate etch stop structure 3404 may have a width w in the range of about 10 nanometers and about 1,000 nanometers. The high etch selectivity allows the field plate 122 to be formed with the plurality of contacts 120 at the same time, while providing a vertical offset between the bottommost surface of the field plate 122 and the bottom surface of the plurality of contacts 120. It provides good control of vertical displacement (i.e., good control of the breakdown voltage of the high voltage transistor device 3400) to the distance between the bottom surface of the semiconductor substrate 102 and field plate 122 d _V a.

35 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 3500 with a field plate etch stop structure defining a field plate, the field plate including a bottom that is vertically offset from the bottom surface of the conductive contact surface.

The high voltage transistor element 3500 includes a field plate etch stop structure 3404 disposed above the first ILD layer 3402. In some embodiments, the field plate etch stop structure 3404 may have sidewalls oriented at a non-zero angle with respect to a line perpendicular to the upper surface of the first ILD layer 3402. For example, in some embodiments, the non-zero angle may be in the range of 0° and about 30°.

The second ILD layer 3406 is disposed above the field plate etch stop structure 3404 and the first ILD layer 3402. In some embodiments, the first ILD layer 3402 includes sidewalls 3502s defining protrusions 3502 under the field plate etch stop structure 3404. In such embodiments, the second ILD layer 3406 laterally contacts the first ILD layer 3402 along the sidewall 3502s.

36 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 3600 with a field plate etch stop structure defining a field plate, the field plate including a bottom that is vertically offset from the bottom surface of the conductive contact surface.

The high-voltage transistor element 3600 includes a metal gate structure 3602 arranged above the semiconductor substrate 102 between the source region 104 and the drain region 106. The metal gate structure 3602 includes a metal gate electrode 3604 separated from the substrate by a gate dielectric 3606. In some embodiments, the metal gate electrode 3604 may include aluminum, ruthenium, palladium, hafnium, zirconium, titanium, and the like. In some embodiments, the gate dielectric 3606 includes a high-k dielectric, such as hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, aluminum oxide, zirconium oxide, and the like.

A contact etch stop layer (CESL) 406 is disposed on the semiconductor substrate 102. The CESL 406 has an uppermost surface 406u laterally adjacent to the metal gate structure 3602. The first ILD layer 3402 is disposed above the CESL 406. In some embodiments, the metal gate structure 3602, CESL 406, and the first ILD layer 3402 have substantially flat (For example, the plane within the tolerance of the chemical mechanical planarization process) the uppermost surface. The second ILD layer 3406 is disposed above the first ILD layer 3402. The second ILD layer 3406 contacts the upper surface of the metal gate structure 3602, CESL 406 and the first ILD layer 3402.

The field plate etch stop structure 3404 is disposed above the uppermost surface of the first ILD layer 3402, at a position laterally between the metal gate structure 3602 and the drain region 106. The field plate etch stop structure 3404 has a bottom surface disposed along a horizontal plane that extends along the uppermost surface of the metal gate structure 3602, CESL 406, and first ILD layer 3402. In some embodiments (not shown), the first ILD layer 3402 may be recessed between the outermost sidewall of the field plate etch stop structure 3404 and the CESL 406. The field plate 122 is above the field plate etch stop structure 3404. The field plate 122 extends from the top of the second ILD layer 3406 to the field plate etch stop structure 3404 so that the bottommost surface of the field plate 122 is above the top of the metal gate structure 3602.

FIG. 37 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 3700 with a field plate etch stop structure defining a field plate, the field plate including a bottom that is vertically offset from the bottom surface of the conductive contact surface.

The high-voltage transistor element 3700 includes a metal gate structure 3602 arranged above the semiconductor substrate 102 between the source region 104 and the drain region 106. The CESL 406 is disposed above the semiconductor substrate 102 and has an uppermost surface 406u laterally adjacent to the metal gate structure 3602. The first ILD layer 3402 is disposed above the CESL 406. The second ILD layer 3406 is disposed above the first ILD layer 3402. The second ILD layer 3406 contacts the uppermost surface of the metal gate structure 3602, CESL 406 and the first ILD layer 3402.

The first ILD layer 3402 has sidewalls 3402s defining a cavity 3702 in the first ILD layer 3402, and the cavity is between the metal gate structure 3602 and the drain region 106 between. In some embodiments, the sidewall 3402s extends from the uppermost surface of the first ILD layer 3402 to the CESL 406 so that the bottom of the cavity 3702 is defined by the CESL 406.

In some embodiments, the dielectric material 3704 is disposed in the cavity 3702, and the field plate etch stop structure 3404 is disposed in the cavity 3702 above the dielectric material 3704. In some embodiments, the dielectric material 3704 may include oxide (eg, silicon oxide), nitride, or the like. In some other embodiments, where the field plate etch stop structure 3404 is a dielectric, the dielectric material 3704 can be omitted (for example, the field plate etch stop structure 3404 is made to contact the CESL 406). The second ILD layer 3406 is disposed above the first ILD layer 3402, and the field plate 122 is above the field plate etch stop structure 3404. The field plate 122 is laterally surrounded by the second ILD layer 3406. The field plate 122 extends from the top of the second ILD layer 3406 to the field plate etch stop structure 3404.

In some embodiments, the field plate etch stop structure 3404 extends from the top of the dielectric material 3704 to the top of the first ILD layer 3402. In such embodiments, the bottom of the field plate 122 is separated from the semiconductor substrate 102 by a distance d _V defined by the dielectric material 3704, the field plate etch stop structure 3404, and the CESL 406. In some embodiments, the distance d _V is substantially equal to the thickness of the first ILD layer 3402.

In other embodiments, cross-sectional view of FIG. 38 is shown in 3800, etching stop field plate structure 3404 has a concave below the uppermost surface of the uppermost surface of the first ILD layer 3402 by a non-zero distance d _r. Recessing the field plate etch stop structure 3404 below the uppermost surface of the first ILD layer 3402 allows the distance d _V between the bottommost surface of the field plate 122 and the semiconductor substrate 102 to be reduced to be lower than the thickness of the first ILD layer 3402.

Figure 39 shows a cross-sectional view of some additional embodiments of a high voltage transistor element 3900 with a field plate etch stop structure defining a field plate, the field plate including a bottom that is vertically offset from the bottom surface of the conductive contact surface.

The high-voltage transistor element 3900 includes an RPO 2002 that is laterally disposed between the metal gate structure 3602 and the CESL 406 and vertically between the semiconductor substrate 102 and the CESL 406. The first ILD layer 3402 is disposed above the CESL 406, and the second ILD layer 3406 is disposed above the first ILD layer 3402. The second ILD layer 3406 contacts the uppermost surface of the metal gate structure 3602, CESL 406 and the first ILD layer 3402.

The sidewalls of the first ILD layer 3402 and the second ILD layer 3406 define a cavity 3902, which extends vertically from the top of the second ILD layer 3406 to the CESL 406 and is laterally located between the metal gate structure 3602 and the drain region 106 between. The dielectric material 3704 is disposed in the cavity 3902, and the field plate etch stop structure 3404 is disposed in the cavity 3902 above the dielectric material 3704. In some embodiments, the field plate etch stop structure 3404 extends from the top of the dielectric material 3704 to the top of the second ILD layer 3406. In other embodiments (not shown), the field plate etch stop structure 3404 may have an uppermost surface recessed below the top of the second ILD layer 3406.

The third ILD layer 3408 is disposed above the second ILD layer 3406. The field plate 122 extends through the third ILD layer 3408 to the field plate etch stop structure 3404. The bottom surface of the field plate 122 to separate non-zero distance d _v from the semiconductor substrate 102 vertically. Using the first ILD layer 3402 and the second ILD layer 3406 to define the cavity 3902 allows a larger range of non-zero distance d _v .

40-50 show a cross-sectional view 4000 to a cross-sectional view 5000 of some embodiments of a method for forming a high-voltage transistor element having a field plate etch stop structure defining a field plate, the field plate includes A bottom surface that is vertically offset from the bottom surface of the conductive contact. Although referring to the cross-sectional view 4000 to the cross-sectional view 5000 shown in the method description in FIGS. 40 to 50, it should be understood that the structure shown in FIGS. 40 to 50 is not limited to the method and can actually be independently independent于说方法。 In the method.

As shown in the cross-sectional view 4000 of FIG. 40, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implanted regions (for example, any of those implanted regions shown in FIGS. 1 to 10). In some embodiments, the semiconductor substrate 102 may be selectively shielded (for example, using a photoresist mask) and then high-energy dopants (for example, p-type dopant species such as boron or n-type such as phosphorous The dopant) is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions.

A gate structure 116 having a gate dielectric layer 110 and a gate electrode material 108 is formed on the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 may be formed by depositing a gate dielectric layer on the semiconductor substrate 102 and by depositing a gate electrode material on the gate dielectric layer. The gate dielectric layer and the gate electrode material may then be patterned (eg, etched according to a photoresist mask and/or a hard mask) to define the gate structure 116.

As shown in the cross-sectional view 4100 of FIG. 41, a photoresist protective oxide (RPO) layer 4102 is formed over the gate structure 116. RPO 4102 is configured to block the formation of silicide on the bottom layer. In some embodiments, the RPO layer 4102 may be deposited by a vapor deposition technique (eg, CVD). In some embodiments, the RPO layer 4102 may include silicon dioxide (SiO2), silicon nitride, or the like.

As shown in the cross-sectional view 4200 of FIG. 42, the RPO layer (RPO layer 4102 of FIG. 41) is selectively patterned to define RPO 2002. In some embodiments, the RPO layer is selectively patterned so that the RPO 2002 from directly above the gate structure 116 The first outermost sidewall extends to the second outermost sidewall laterally between the gate structure 116 and the drain region 106. In some embodiments, the RPO layer can be selectively patterned by forming a shielding layer 2702 over the RPO layer and then exposing the RPO layer to an etchant in areas not covered by the shielding layer 2702.

As shown in the cross-sectional view 4300 of FIG. 43, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the RPO 2002. In some embodiments, CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (for example, Si ₃ N ₄ ), a carbide layer (SiC), and so on.

As shown in the cross-sectional view 4400 of FIG. 44, a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406. In some embodiments, the first ILD layer 3402 may include oxide (for example, SiO ₂ ), ultra-low-k dielectric material, low-k dielectric material (for example, SiCO), and so on. In some embodiments, the first ILD layer 3402 may be formed by a vapor deposition process.

As shown in the cross-sectional view 4500 of FIG. 45, a field plate etch stop layer 4502 is formed above the first ILD layer 3402. In various embodiments, the field plate etch stop structure 4502 may include silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), amorphous silicon (a-Si), hafnium oxide (HfO _x ), zirconia (ZrO _x ), metal oxide and so on. In various embodiments, the field plate etch stop layer 4502 may be formed to have a thickness ranging between about 1 nanometer and about 150 nanometers.

As shown in the cross-sectional view 4600 of FIG. 46, the field plate etch stop layer (field plate etch stop layer 4502 of FIG. 45) is patterned to define the field plate etch stop structure 3404 above the first ILD layer 3402. In some embodiments, the field can be selectively patterned by forming a shielding layer 4604 over the field plate etch stop layer and then exposing the field plate etch stop layer to an etchant 4602 in areas not covered by the shielding layer 4604 Board etching stop layer. In some embodiments, the etchant 4602 may include ions for ion bombardment etching. In other embodiments, the etchant 4602 may include a plasma etchant (for example, with a fluorine chemical substance, a chlorine chemical substance, etc.).

As shown in the cross-sectional view 4700 of FIG. 47, the second ILD layer 3406 is formed above the first ILD layer 3402 and the field plate etch stop structure 3404. In some embodiments, the second ILD layer 3406 may include oxide (for example, SiO ₂ ), ultra-low-k dielectric material, low-k dielectric material (for example, SiCO), and so on. In some embodiments, the second ILD layer 3406 may be formed by a vapor deposition process. In some embodiments, the second ILD layer 3406 is formed in direct contact with the first ILD layer 3402.

As shown in the cross-sectional view 4800 of FIG. 48, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The resulting field plate opening 1608 is defined by the second ILD layer 3406 and the upper surface of the field plate etch stop structure 3404. The etching process uses a highly selective etchant between the field plate etch stop structure 3404 and the first ILD layer 3402 and the second ILD layer 3406 (for example, the etchant etches the second layer faster than the field plate etch stop structure 3404). An ILD layer 3402 and a second ILD layer 3406), so that the contact opening 1606 and the field plate opening 1608 have a non-zero distance of etch depth offset.

Since the thickness of the deposition process is generally easier to control than the depth of the etching process, the distance between the bottom of the field plate opening 1608 and the semiconductor substrate 102 can be well controlled (because it is used to form the CESL 406, the first ILD layer 3402 And the thickness of the deposition process of the field plate etch stop structure 3404), so as to obtain a field plate with well-defined electrical properties (for example, well-defined breakdown voltage). In some embodiments, the gap between the bottom of the field plate opening 1608 and the semiconductor substrate 102 The distance may be in the range of about 400 angstroms and about 700 angstroms.

As shown in the cross-sectional view 4900 of FIG. 49, the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials to define a plurality of contacts 120 and field plates 122. In some embodiments, one or more conductive materials may be deposited by means of deposition techniques (eg, CVD, PVD, PE-CVD, sputtering, etc.) and/or plating processes (eg, electroplating or electroless plating processes). Then, a planarization process (such as chemical mechanical planarization) may be performed to remove the excess conductive material or materials and form a flat surface along the line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN), among others. In some embodiments, a diffusion barrier layer and/or liner layer may be deposited into the contact opening 1606 and the field plate opening 1608 before depositing one or more conductive materials.

As shown in the cross-sectional view 5000 of FIG. 50, the third ILD layer 3408 is formed above the second ILD layer 3406, and the first back end of line (BEOL) metal line layer 128 is formed in the third ILD layer 3408. In various embodiments, the third ILD layer 3408 may be formed by depositing a third ILD material on the second ILD layer 3406. The third ILD layer 3408 is then etched to form trenches extending in the third LD layer 3408. The trench is filled with conductive material, and a planarization process (for example, CMP) is performed to remove excess conductive material from above the second ILD layer 3406.

FIGS. 51 to 65 show a cross-sectional view of some additional embodiments of a method of forming a high-voltage transistor element having a field plate etch stop structure defining a field plate. It includes a bottom surface that is vertically offset from the bottom surface of the conductive contact. Although referring to the cross-sectional view 5100 to the cross-sectional view 6500 shown in the method description in FIGS. 51 to 65, it should be understood that the structure shown in FIGS. 51 to 65 is not limited to the method and can actually be independently independent Yu said party Law.

As shown in the cross-sectional view 5100 of FIG. 51, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implanted regions (for example, any of those implanted regions shown in FIGS. 1 to 10).

The sacrificial gate structure 5102 is formed on the semiconductor substrate 102 between the source region 104 and the drain region 106. The sacrificial gate structure 5102 includes a sacrificial gate electrode 5104. In some embodiments, the sacrificial gate electrode 5104 may include polysilicon. In some embodiments, the sacrificial gate structure 5102 may further include a gate dielectric 3606 that separates the sacrificial gate electrode 5104 from the semiconductor substrate 102. In some embodiments, the gate dielectric 3606 may include a high-k dielectric material.

As shown in the cross-sectional view 5200 of FIG. 52, a photoresist protective oxide (RPO) layer 4102 is formed over the sacrificial gate structure 5102. In some embodiments, the RPO layer 4102 may be deposited by vapor deposition techniques (eg, CVD, PVD, etc.). In some embodiments, the RPO layer 4102 may include silicon dioxide (SiO2), silicon nitride, or the like.

As shown in the cross-sectional view 5300 of FIG. 53, the RPO layer (RPO layer 4102 of FIG. 52) is selectively patterned to define RPO 2002. In some embodiments, the RPO layer is selectively patterned so that the RPO 2002 extends from the first outermost sidewall directly above the sacrificial gate structure 5102 to the second lateral side between the sacrificial gate structure 5102 and the drain region 106. The outermost side wall. In some embodiments, the masking layer 2702 can be formed by forming the masking layer 2702 over the RPO layer and then exposing the RPO layer to be uncovered by the masking layer 2702. The etchant in the covered area selectively pattern the RPO layer.

As shown in the cross-sectional view 5400 of FIG. 54, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the RPO 2002. In some embodiments, CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (for example, Si ₃ N ₄ ), a carbide layer (SiC), and so on.

As shown in the cross-sectional view 5500 of FIG. 55, a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406.

As shown in the cross-sectional view 5600 of FIG. 56, the first planarization process is performed along the line 5602. The first planarization process removes the portions of the first ILD layer 3402, CESL 406, and RPO 2002 above the sacrificial gate structure 5102. By removing the portions of the first ILD layer 3402, CESL 406, and RPO 2002 above the sacrificial gate structure 5102, the top of the sacrificial gate electrode 5104 is exposed.

As shown in the cross-sectional view 5700 of FIG. 57, the sacrificial gate structure 5102 is removed to form a replacement gate cavity 5702 between the sidewalls of the CESL 406. In some embodiments, an etchant selected relative to the sacrificial gate structure 5102 may be used to remove the sacrificial gate structure 5102.

As shown in the cross-sectional view 5800 of FIG. 58, a metal gate electrode 3604 is formed in the replacement gate cavity 5702 to define a metal gate structure 3602. In some embodiments, conductive materials (e.g., aluminum, tantalum, nickel, molybdenum, etc.) can be deposited on the replacement gate by using a deposition process (e.g., CVD, PE-CVD, PVD, ALD, sputtering, etc.) A metal gate electrode 3604 is formed in the cavity 5702. In some embodiments (not shown), one or more gate dielectrics may be formed in the replacement gate cavity 5702 before the deposition of the conductive material. After the conductive material is deposited in the replacement gate cavity 5702, a second planarization process (for example, a CMP process) is performed (along line 5806). The second planarization process removes the conductive material from above the first ILD layer 3402 to define the metal gate electrode 3604.

As shown in the cross-sectional view 5900 of FIG. 59, an etching process is performed to define a cavity 3702 in the first ILD layer 3402, between the metal gate structure 3602 and the drain region 106. The cavity 3702 is defined by the sidewall of the first ILD layer 3402 and the upper surface of the CESL 406. In some embodiments, a cavity 3702 may be defined, thereby forming a shielding layer (not shown) over the first ILD layer 3402 and then exposing the first ILD layer 3402 to the etchant in areas not covered by the shielding layer.

As shown in the cross-sectional view 6000 of FIG. 60, a dielectric material 3704 is formed in the cavity 3702. In some embodiments, the dielectric material 3704 may include oxide (eg, silicon oxide), nitride, or the like. In some embodiments, the dielectric material 3704 can be removed from the cavity 3702 through a deposition process (for example, CVD, PE-CVD, PVD, ALD, etc.), followed by a chemical mechanical planarization (CMP) process and/or an etching process. It is formed by removing the dielectric material.

As shown in the cross-sectional view 6100 of FIG. 61, the field plate etch stop structure 3404 is formed in the cavity 3702 above the dielectric material 3704. In various embodiments, the field plate etch stop structure 3404 may include silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), amorphous silicon (a-Si), hafnium oxide (HfO _x ), zirconia (ZrO _x ), metal oxide and so on. In various embodiments, the field plate etch stop structure 3404 may be formed to have a thickness ranging between about 1 nanometer and about 150 nanometers. In some embodiments, the field plate etch stop structure 3404 may be deposited with a field plate etch stop material (for example, silicon nitride, amorphous silicon, metal oxide, etc.), followed by a chemical mechanical planarization (CMP) process and/ Or the etching process removes the dielectric material and/or the field plate etch stop material from the outside of the cavity 3702 to form it.

As shown in the cross-sectional view 6200 of FIG. 62, the second ILD layer 3406 is formed above the first ILD layer 3402 and the field plate etch stop structure 3404.

As shown in the cross-sectional view 6300 of FIG. 63, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. In some embodiments, the etching process exposes the upper surface of the second ILD layer 3406 to the etchant 3002 in the area not covered by the shielding layer 3003 to define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The field plate opening 1608 is defined by the sidewall of the second ILD layer 3406 and the upper surface of the field plate etch stop structure 3404. The contact opening 1606 and the field plate opening 1608 have a non-zero distance etch depth offset. In some embodiments, the non-zero depth may be in the range of about 400 angstroms and about 700 angstroms.

As shown in the cross-sectional view 6400 of FIG. 64, the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by means of vapor deposition techniques (for example, CVD, PVD, PE-CVD, sputtering, etc.) and/or plating processes (for example, electroplating or electroless plating processes) . Then, a planarization process (such as chemical mechanical planarization) may be performed to remove the excess conductive material or materials and form a flat surface along the line 3102.

As shown in the cross-sectional view 6500 of FIG. 65, the third ILD layer 3408 is formed above the second ILD layer 3406, and the first back end of line (BEOL) metal line layer 128 is formed in the third ILD layer 3408.

66 to 76 show a cross-sectional view 6600 to cross-sectional view 7600 illustrating some additional embodiments of a method of forming a high-voltage transistor element having a field plate etch stop structure defining a field plate, the field plate It includes a bottom surface that is vertically offset from the bottom surface of the conductive contact. Although referring to the method description in Fig. 66 to Fig. 76, The cross-sectional view 6600 to the cross-sectional view 7600 are shown, but it should be understood that the structure shown in FIG. 66 to FIG. 76 is not limited to the method and may actually be independent of the method alone.

As shown in the cross-sectional view 6600 of FIG. 66, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively implanted to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implanted regions (for example, any of those implanted regions shown in FIGS. 1 to 10).

The sacrificial gate structure 5102 is formed on the semiconductor substrate 102 between the source region 104 and the drain region 106. The sacrificial gate structure 5102 includes a sacrificial gate electrode 5104. In some embodiments, the sacrificial gate electrode 5104 may include polysilicon. In some embodiments, the sacrificial gate structure 5102 may further include a gate dielectric 3606 that separates the sacrificial gate electrode 5104 from the semiconductor substrate 102. In some embodiments, the gate dielectric 3606 may include a high-k dielectric material.

As shown in the cross-sectional view 6700 of FIG. 67, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the sacrificial gate structure 5102. In some embodiments, CESL 406 may be formed by a vapor deposition process. The CESL 406 may include a nitride layer (for example, Si ₃ N ₄ ), a carbide layer (SiC), and so on.

As shown in the cross-sectional view 6800 of FIG. 68, a first interlayer dielectric (ILD) layer 3402 is formed over the CESL 406.

As shown in the cross-sectional view 6900 of FIG. 69, the first planarization process is performed along the line 5602. The first planarization process removes portions of the first ILD layer 3402 and CESL 406 from above the sacrificial gate structure 5102. By going from above the sacrificial gate structure 5102 The portions of the first ILD layer 3402 and CESL 406 are removed, and the top of the sacrificial gate electrode 5104 is exposed.

As shown in the cross-sectional view 7000 of FIG. 70, the sacrificial gate structure 5102 is removed to form a replacement gate cavity 5702 between the sidewalls of the CESL 406. In some embodiments, the sacrificial gate structure 5102 can be removed by using an etchant selected with respect to the sacrificial gate structure 5102. The metal gate electrode 3604 is then formed in the replacement gate cavity 5702 to define the metal gate structure 3602. In some embodiments, the metal gate electrode 3604 may be formed by depositing a conductive material in the replacement gate cavity 5702. In some embodiments, one or more gate dielectrics may be formed in the replacement gate cavity 5702 before the deposition of the conductive material. After the conductive material is deposited in the replacement gate cavity 5702, a second planarization process (for example, a CMP process) is performed (along line 5806). The second planarization process (along line 5806) removes conductive material from above the first ILD layer 3402 to define the metal gate electrode 3604.

As shown in the cross-sectional view 7100 of FIG. 71, an etching process is performed to define a cavity 3702 in the first ILD layer 3402, between the metal gate structure 3602 and the drain region 106. The cavity 3702 is defined by the sidewall of the first ILD layer 3402 and the upper surface of the CESL 406. In some embodiments, a cavity 3702 may be defined, thereby forming a shielding layer (not shown) over the first ILD layer 3402 and then exposing the first ILD layer 3402 to the etchant in areas not covered by the shielding layer.

As shown in the cross-sectional view 7200 of FIG. 72, a dielectric material 3704 is formed in the cavity 3702. In some embodiments, the dielectric material 3704 may include oxide (eg, silicon oxide), nitride, or the like. A field plate etch stop structure 3404 is then formed in the cavity 3702 above the dielectric material 3704. In various embodiments, the field plate etch stop structure 4502 may include silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ), amorphous silicon (a-Si), hafnium oxide (HfO _x ), zirconia (ZrO _x ), metal oxide and so on. In some embodiments, the field plate etch stop layer 4502 can be achieved by depositing a field plate etch stop material (eg, CVD, PE-CVD, PVD, ALD, etc.), followed by removing the dielectric material and/or from outside the cavity 3702 The field plate is formed by the chemical mechanical planarization process and/or the etching process of the stop material.

As shown in the cross-sectional view 7300 of FIG. 73, the second ILD layer 3406 is formed over the first ILD layer 3402 and the field plate etch stop structure 3404.

As shown in the cross-sectional view 7400 of FIG. 74, an etching process is performed to simultaneously define a plurality of contact openings 1606 and field plate openings 1608. The plurality of contact openings 1606 are defined by the sidewalls of the first ILD layer 3402 and the second ILD layer 3406. The field plate opening 1608 is defined by the second ILD layer 3406 and the upper surface of the field plate etch stop structure 3404. The contact opening 1606 and the field plate opening 1608 have a non-zero distance etch depth offset. In some embodiments, the non-zero depth may be in the range of about 400 angstroms and about 700 angstroms.

As shown in the cross-sectional view 7500 of FIG. 75, the contact opening 1606 and the field plate opening 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by means of vapor deposition techniques (for example, CVD, PVD, PE-CVD, sputtering, etc.) and/or plating processes (for example, electroplating or electroless plating processes) . A planarization process (eg, chemical mechanical planarization) may then be performed to remove the excess conductive material or materials from above the second ILD layer 3406.

As shown in the cross-sectional view 7600 of FIG. 76, the third ILD layer 3408 is formed above the second ILD layer 3406, and the first back end of line (BEOL) metal line layer 128 is formed in the third ILD layer 3408.

Figure 77 shows the formation of a field plate etch stop junction with a defined field plate A flowchart of some embodiments of a method 7700 of constructing a high voltage transistor element, the field plate includes a bottom surface that is vertically offset from the bottom surface of the conductive contact.

At act 7702, a gate structure is formed over the substrate. 40, 51, and 66 show a cross-sectional view 4000, a cross-sectional view 5100, and a cross-sectional view 6600 of various embodiments corresponding to action 7702.

At act 7704, the source and drain regions are formed within the substrate, on opposite sides of the gate structure. In some additional embodiments, one or more additional doped regions (for example, body regions, drift regions, etc.) may also be formed in the substrate. 40, 51, and 66 show a cross-sectional view 4000, a cross-sectional view 5100, and a cross-sectional view 6600 of various embodiments corresponding to action 7704.

At act 7706, a photoresistive protective oxide (RPO) may be formed over the gate structure and laterally between the gate structure and the drain region. 41 to 42 and 52 to 53 show cross-sectional views 4100 to 4200 and cross-sectional views 5200 to 5300 of various embodiments corresponding to action 7706.

At act 7708, a contact etch stop layer (CESL) is formed over the gate structure and the substrate. Figures 43, 54 and 67 show cross-sectional views 4300, 5400, and 6700 of various embodiments corresponding to act 7708.

At act 7710, a first interlayer dielectric (ILD) layer is formed over CESL. 44, 54 and 68 show cross-sectional views 4400, 5400, and 6800 of various embodiments corresponding to action 7710.

At act 7712, the field plate etch stop structure is formed after the formation of the first ILD layer. FIGS. 45 to 46, 59 to 61, and 71 to 72 show cross-sectional views 4500 to 4600 of various embodiments corresponding to action 7712, Cross-sectional view 5900 to cross-sectional view 6100 and cross-sectional view 7100 to cross-sectional view 7200.

At act 7714, a second ILD layer is formed over the first ILD layer and the field plate etch stop structure. FIGS. 47, 62, and 73 show a cross-sectional view 4700, a cross-sectional view 6200, and a cross-sectional view 7300 of various embodiments corresponding to action 7714.

At act 7716, the first ILD layer and the second ILD layer are selectively etched to simultaneously define a plurality of contact openings extending through the first ILD layer and the second ILD and extending through the second ILD layer to the field plate etch Terminate the field plate opening of the structure. FIGS. 48, 63, and 74 show a cross-sectional view 4800, a cross-sectional view 6300, and a cross-sectional view 7400 of various embodiments corresponding to action 7716.

At act 7718, the multiple contact openings and field plate openings are filled with one or more conductive materials. 49, 64, and 75 show a cross-sectional view 4900, a cross-sectional view 6400, and a cross-sectional view 7500 of various embodiments corresponding to action 7718.

At act 7720, conductive interconnects are formed in the third ILD layer above the second ILD layer. 50, 65, and 76 show a cross-sectional view 5000, a cross-sectional view 6500, and a cross-sectional view 7600 corresponding to various embodiments of action 7720.

Therefore, the present disclosure relates to a high voltage transistor element having a field plate etch stop structure defining a field plate, the field plate including a bottom surface that is vertically offset from the bottom surface of the conductive contact.

In some embodiments, the present disclosure relates to an integrated wafer. The integrated chip includes: a gate structure, arranged above the substrate, between the source region and the drain region; a first interlayer dielectric (ILD) layer, arranged above the substrate and the gate structure; and a second ILD Layer, arranged above the first ILD layer; a field plate etch stop structure, between the first ILD layer and the second ILD layer; a field plate, extending from the uppermost surface of the second ILD layer to the field plate etch stop structure; and more A conductive contact extends from the uppermost surface of the second ILD layer to the source region and the drain region. In some embodiments, the integrated wafer further includes a dielectric layer extending laterally from directly above the gate structure to between the gate structure and the drain region; and contacts disposed on the substrate, the dielectric layer, and the gate structure Etch stop layer. In some embodiments, the bottommost surface of the field plate is arranged along a horizontal plane parallel to the upper surface of the substrate and extending through the side walls of the plurality of conductive contacts. In some embodiments, the field plate etch stop structure has a bottommost surface above the topmost surface of the first ILD layer. In some embodiments, the first ILD layer has sidewalls defining a cavity laterally between the gate structure and the drain region, and the field plate etch stop structure is arranged in the cavity between the sidewalls of the first ILD layer. In some embodiments, the integrated wafer further includes a dielectric material disposed in the cavity between the field plate etch stop structure and the substrate. In some embodiments, the integrated wafer further includes a contact etch stop layer disposed above the substrate and the gate structure, and the upper surface of the contact etch stop layer defines the bottom of the cavity. In some embodiments, the field plate etch stop structure includes amorphous silicon. In some embodiments, the field plate etch stop structure includes silicon nitride, silicon oxynitride, or metal oxide. In some embodiments, the field plate etch stop structure includes a relatively outermost sidewall laterally between the gate structure and the drain region. In some embodiments, the integrated wafer further includes an etch stop layer disposed above the second ILD layer, the bottommost surface of the second ILD layer contacts the first ILD layer, and the uppermost surface of the second ILD layer contacts the etch stop layer.

In other embodiments, the present disclosure relates to an integrated wafer. The integrated chip includes: a gate structure, which is arranged above the substrate and located between the source region and the drain region; a dielectric structure, which is arranged above the substrate and the gate structure; a field plate etching termination structure, which is arranged In the dielectric structure; a plurality of conductive contacts are arranged in the dielectric structure; and a field plate is arranged on the field plate etch stop structure, the field plate has a bottommost surface, and the bottommost surface is parallel to the The upper surface of the substrate is arranged in a first horizontal plane intersecting the side walls of the plurality of conductive contacts between the top surface and the bottom surface of the plurality of conductive contacts. In some embodiments, the field plate etch stop structure has a bottommost surface that is parallel to the first horizontal plane and is between the top and bottom surfaces of the plurality of conductive contacts and the sidewalls of the plurality of conductive contacts. Intersecting second horizontal plane arrangement. In some embodiments, the dielectric structure includes a plurality of stacked ILD layers; and the field plate and the plurality of conductive contacts are laterally surrounded by the first ILD layer of the plurality of stacked ILD layers and extend vertically to the first ILD layer. The top of the ILD layer. In some embodiments, the dielectric structure includes a first ILD layer and a second ILD layer above the first ILD layer; conductive contacts extend from the bottom of the first ILD layer to the top of the second ILD layer; and the field The plate etch stop structure is above a portion of the first ILD layer and below the lower surface of the second ILD layer. In some embodiments, the dielectric structure includes a first ILD layer and a second ILD layer above the first ILD layer; and the field plate etch stop structure contacts the uppermost surface of the first ILD layer.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a gate structure between a source region and a drain region on a substrate; forming a contact etch stop layer on the substrate; forming a first ILD layer above the contact etch stop layer; forming a first ILD layer Then a field plate etch stop structure is formed between the gate structure and the drain region; a second ILD layer is formed above the field plate etch stop structure; and a plurality of contacts extending through the first ILD layer and the second ILD layer are simultaneously formed And a field plate extending through the second ILD layer to the field plate etch stop structure. In some embodiments, the method further includes forming a field plate etch stop layer on the first ILD layer; And patterning the field plate etch stop layer to define the field plate etch stop structure as having the outermost sidewall between the gate structure and the drain region. In some embodiments, the method further includes selectively patterning the first ILD layer to define a cavity between the gate structure and the drain region; and forming a field plate etch stop structure in the cavity. In some embodiments, the method further includes forming a dielectric material in the cavity; and forming a field plate etch stop structure above the dielectric material.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and/or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made in this article without departing from the spirit and scope of the present disclosure. .

400: LDMOS element

102: Semiconductor substrate

104: source region

106: Drain Region

108: gate electrode

110: gate dielectric layer

118: First ILD layer

120: Contact

210: Gate structure

212: Sidewall spacer

402: Silicide barrier

404: Field plate etching stop layer

406: contact etch stop layer

410: The first metal material

412: second metal material

414: Lining

416: The second ILD layer

418: first metal wire layer

420: Flat surface

Claims (10)

An integrated wafer comprising: a gate structure arranged above a substrate and located between a source region and a drain region; a first interlayer dielectric layer arranged above the substrate and laterally surrounding the gate Structure; a second interlayer dielectric layer, arranged above the first interlayer dielectric layer and the gate structure, wherein the gate structure is located between the substrate and the second interlayer dielectric layer; The field plate etch stop structure has a relatively outermost sidewall laterally located between the gate structure and the drain region; a field plate extends from the uppermost surface of the second interlayer dielectric layer to the field A plate etch stop structure; and a plurality of conductive contacts extending from the uppermost surface of the second interlayer dielectric layer to the source region and the drain region. The integrated wafer described in the first item of the scope of patent application further includes: a dielectric layer that continuously extends along the sidewall of the gate structure to between the gate structure and the drain region; and contact etching A stop layer is arranged above the substrate and the dielectric layer, wherein the field plate etch stop structure contacts the upper surface of the etch stop layer. The integrated wafer according to claim 1, wherein the bottommost surface of the field plate is arranged along a horizontal plane parallel to the upper surface of the substrate and extending through the side walls of the plurality of conductive contacts. The integrated wafer according to the first item of the scope of patent application, wherein the field plate etch stop structure has a maximum value above the topmost surface of the first interlayer dielectric layer. The bottom surface. The integrated wafer according to claim 1, wherein the first interlayer dielectric layer has sidewalls defining a cavity laterally between the gate structure and the drain region, the A field plate etch stop structure is arranged in the cavity between the sidewalls of the first interlayer dielectric layer. The integrated wafer described in item 1 of the scope of patent application further includes: an etching stop layer disposed above the second interlayer dielectric layer, wherein the bottommost surface of the second interlayer dielectric layer contacts the first An interlayer dielectric layer, and the uppermost surface of the second interlayer dielectric layer contacts the etch stop layer. An integrated wafer comprising: a gate structure arranged above a substrate and located between a source region and a drain region; and an etching stop layer arranged above the substrate and arranged on the gate structure and the drain electrode Between regions; a dielectric structure, disposed above the etch stop layer and the gate structure, wherein the dielectric structure includes a first interlayer dielectric layer and a dielectric structure above the first interlayer dielectric layer A second interlayer dielectric layer; a field plate etch stop structure, arranged in the dielectric structure, wherein the field plate etch stop structure is above a portion of the first interlayer dielectric layer and the second interlayer Below the lower surface of the electrical layer, and wherein the etch stop layer continuously extends beyond the relatively outermost sidewall of the field plate etch stop structure; a plurality of conductive contacts are arranged in the dielectric structure, wherein the A plurality of conductive contacts extend from the bottom of the first interlayer dielectric layer to the top of the second interlayer dielectric layer; and a field plate disposed on the field plate etch stop structure, wherein the field plate have The bottommost surface, the bottommost surface being along a first horizontal plane parallel to the upper surface of the substrate and intersecting the sidewalls of the plurality of conductive contacts between the top and bottom surfaces of the plurality of conductive contacts Layout. The integrated wafer according to claim 7, wherein the field plate etch stop structure has a bottommost surface, and the bottommost surface is parallel to the first horizontal plane and on the top surface of the gate structure It is arranged on a second horizontal plane intersecting the side wall of the gate structure between the bottom surface. The integrated wafer according to the seventh item of the scope of patent application, wherein the field plate and the plurality of conductive contacts are laterally surrounded by the first interlayer dielectric layer and extend vertically to the first The top of the interlayer dielectric layer. A method for forming an integrated wafer includes: forming a gate structure between a source region and a drain region above a substrate; forming a contact etching stop layer above the substrate; and forming a first contact etching stop layer above the contact etching stop layer. An interlayer dielectric layer; after forming the first interlayer dielectric layer, a field plate etch stop structure is formed between the gate structure and the drain region, wherein the field plate etch stop structure has a lateral direction Ground is located on the relatively outermost sidewall between the gate structure and the drain region; a second interlayer dielectric layer is formed above the field plate etch stop structure, wherein the gate structure is located between the substrate and the drain region. Between the second interlayer dielectric layer; and simultaneously forming a plurality of contacts extending through the first interlayer dielectric layer and the second interlayer dielectric layer and through the second interlayer dielectric layer The field plate of the etch stop structure extends to the field plate.

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