WO2023216163A1

WO2023216163A1 - Semiconductor device, integrated circuit and electronic device

Info

Publication number: WO2023216163A1
Application number: PCT/CN2022/092313
Authority: WO
Inventors: 张全良; 姚昌荣; 吴亮
Original assignee: 华为技术有限公司
Priority date: 2022-05-11
Filing date: 2022-05-11
Publication date: 2023-11-16

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device, an integrated circuit and an electronic device. The semiconductor device has both a high breakdown voltage BV and a low specific on-state resistance Ron,sp. The semiconductor device comprises: a substrate; an active layer, which is arranged on the substrate, wherein the active layer comprises a first doped region and a second doped region in contact with the first doped region, the first doped region and the second doped region having different doping types; at least two dielectric material layers, which are arranged on the active layer; and at least two field plates, which are arranged in the dielectric material layers, wherein each field plate penetrates one or more dielectric material layers, a projection of each field plate on the active layer overlaps with the second doped region, and the end of each field plate close to the active layer is insulated from the active layer.

Description

Semiconductor devices, integrated circuits and electronic equipment

Technical field

This application relates to the field of semiconductor technology, and in particular to a semiconductor device, integrated circuit and electronic equipment.

Background technique

Currently, most electronic devices are equipped with integrated circuits, such as power management integrated circuits, display driver integrated circuits, etc. Different integrated circuits include one or more semiconductor devices used to implement their functions. Among them, in some power integrated circuits, the most commonly used semiconductor device is the lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS).

LDMOS has the advantages of easy driving and high frequency. The most important properties of LDMOS are breakdown voltage (breakdown voltage, BV) and specific on-state resistance (Ron, sp). But the silicon limit defines that the breakdown voltage BV is proportional to the specific on-resistance. Therefore, obtaining a semiconductor device with both high breakdown voltage BV and low specific on-resistance Ron,sp is an urgent problem that needs to be solved.

Contents of the invention

Embodiments of the present application provide a semiconductor device, an integrated circuit, and an electronic device. The semiconductor device has both high breakdown voltage BV and low specific on-resistance Ron,sp.

In order to achieve the above objectives, embodiments of the present application provide the following technical solutions:

In a first aspect, a semiconductor device is provided, including: a substrate; an active layer provided on the substrate; the active layer includes a first doped region and a second doped region in contact with the first doped region, The doping types of the first doped region and the second doped region are different; at least two dielectric material layers provided on the active layer; and at least two field plates provided in the dielectric material layer, the field plates passing through One or more dielectric material layers, and the projection of the field plate on the active layer overlaps with the second doped region, and one end of the field plate close to the active layer is insulated from the active layer. For example, when the second doped region is connected to a high voltage, if there is no field plate, then the high voltage connected to the second doped region will be at the contact between the first doped region and the second doped region. The concentrated electric field intensity may cause breakdown of the contact surface between the first doped region and the second doped region. Then when the field plate exists, when the second doped region is connected to the same high voltage, the projection of the field plate on the active layer will form a first electric field intensity on the side away from the first doped region. The projection on the layer will form a second electric field intensity on the side close to the first doped region, and the first electric field intensity is greater than the second electric field intensity. Then the current contact surface between the first doped region and the second doped region is concentrated. The intensity of the electric field received is weakened, that is to say, the field plate weakens the intensity of the electric field concentrated on the contact surface between the first doped region and the second doped region, thereby causing the breakdown voltage BV of the semiconductor device to become higher. At the same time, the field plate is insulated from the active layer, so when the semiconductor device is turned on, that is, when the first doped region and the second doped region are turned on, the field plate will not affect the transmission of carriers in the active layer. It will affect the specific on-resistance Ron,sp of the semiconductor device, so as to obtain a semiconductor device with high breakdown voltage BV and low specific on-resistance Ron,sp.

Optionally, the at least two dielectric material layers include a first dielectric material layer and a second dielectric material layer; the first dielectric material layer is disposed on a side of the active layer away from the substrate; the second dielectric material layer The layer is disposed on the side of the first dielectric material layer away from the substrate; the at least two field plates include a first field plate and a second field plate; the first field plate penetrates the first dielectric material layer, and the first field plate and A first electrode is disposed between the second dielectric material layers; a second field plate penetrates the first dielectric material layer and the second dielectric material layer; and a second electrode is disposed on a surface of the second field plate away from the active layer. In this optional method, the production method of two dielectric material layers and two field plates is specifically shown, and electrodes are provided on both field plates, because when the field plates do not have a determined voltage value, the field plates It will be in a floating state, which will make the stability of the semiconductor device worse. Therefore, if necessary, the field plate can be given a certain voltage value by connecting the electrodes provided on the field plate to a predetermined voltage.

Optionally, a third electrode is further provided between the first dielectric material layer and the second dielectric material layer, and the first electrode and the third electrode are located on both sides of the second field plate. In this alternative, the first electrode and the third electrode are located on both sides of the second field plate, so when making the second field plate, the specific position of the second field plate can be determined by the first electrode and the third electrode.

Optionally, the first field plate is in contact with the second field plate or not. In this alternative solution, the same voltage value can be applied to the first field plate and the second field plate when the first field plate and the second field plate are in contact. When the first field plate and the second field plate are not in contact, the same voltage value can be applied to the first field plate and the second field plate. The same or different voltage values may be applied to the first field plate and the second field plate.

Optionally, it also includes: a gate electrode disposed on the active layer, the gate electrode being insulated from the active layer; the gate electrode covering the contact surface between the first doped region and the second doped region; on the first dielectric material layer A first via hole is provided, a fourth electrode is provided between the first dielectric material layer and the second dielectric material layer, and the fourth electrode is connected to the gate electrode through the first via hole.

Optionally, a second via hole is provided on the second dielectric material layer, a fifth electrode is provided on a surface of the second dielectric material layer away from the first dielectric material layer, and the fourth electrode is connected to the second dielectric material layer through the second via hole. The fifth electrode is connected.

Optionally, the fourth electrode is electrically connected to the first electrode. In this alternative, since the fourth electrode is connected to the gate through the first via hole and the first electrode is disposed on the first field plate, when the fourth electrode is electrically connected to the first electrode, it means that the fourth electrode is electrically connected to the first electrode. The field plate is connected to the gate to adjust the breakdown voltage of the semiconductor device.

Optionally, the fifth electrode is electrically connected to the second electrode. In this alternative, since the fourth electrode is connected to the gate through the first via hole, the fourth electrode is connected to the fifth electrode through the second via hole, and the second electrode is disposed on the second field plate, then on the fifth When the electrode is electrically connected to the second electrode, it means that the second field plate is connected to the gate, thereby adjusting the breakdown voltage of the semiconductor device.

Optionally, the first doped region also includes a third doped region and a fourth doped region that is in contact with the third doped region. The third doped region has the same doping type as the first doped region. The fourth doped region has a different doping type from the first doped region. The fourth doped region is close to the second doped region and is not in contact with the second doped region; a third pass is also provided on the first dielectric material layer. hole and a fourth via hole, a sixth electrode is also provided between the first dielectric material layer and the second dielectric material layer, the sixth electrode is connected to the third doped region through the third via hole, and the sixth electrode passes through the third via hole. The four via holes are connected to the fourth doped region; a fifth via hole is also provided on the second dielectric material layer; a seventh electrode is provided on the surface of the second dielectric material layer away from the first dielectric material layer; The electrode is connected to the seventh electrode through the fifth via hole.

Optionally, the sixth electrode is electrically connected to the first electrode, and/or the seventh electrode is electrically connected to the second electrode. In this alternative, since the sixth electrode is connected to the fourth doped region through the fourth via hole and the first electrode is disposed on the first field plate, when the sixth electrode is electrically connected to the first electrode, that is It means that the first field plate is connected to the fourth doped region to adjust the breakdown voltage of the semiconductor device; and/or, because the sixth electrode is connected to the fourth doped region through the fourth via hole, the sixth electrode The electrode is connected to the seventh electrode through the fifth via hole, and the second electrode is disposed on the second field plate. When the seventh electrode is electrically connected to the second electrode, it means that the second field plate is connected to the fourth doped region. connection to adjust the breakdown voltage of the semiconductor device.

Optionally, the second doped region also includes a fifth doped region, the fifth doped region has the same doping type as the second doped region, and the fifth doped region is not in contact with the first doped region; A sixth via hole is provided on the first dielectric material layer, and an eighth electrode is provided between the first dielectric material layer and the second dielectric material layer. The eighth electrode passes through the sixth via hole and the fifth doped region. Connection; a seventh via hole is also provided on the second dielectric material layer, a ninth electrode is provided on the surface of the second dielectric material layer away from the first dielectric material layer, and the eighth electrode communicates with the ninth electrode through the seventh via hole. Electrode connections.

Optionally, the second doped region also includes a first isolation trench, the opening of the first isolation trench faces the first dielectric material layer, and the projection of the second field plate on the active layer overlaps with the first isolation trench. . In this alternative, since the first isolation trench is usually made of insulating material such as oxide, the presence of the first isolation trench increases the thickness of the insulating material between the second field plate and the active layer, thereby also increasing breakdown Effect of voltage BV.

Optionally, the second doped region also includes a second isolation trench, the opening of the second isolation trench faces the first dielectric material layer, and the projection of the first field plate on the active layer overlaps with the second isolation trench. , the projection of the gate on the active layer overlaps with the second isolation trench. In this alternative, since the second isolation trench is usually made of insulating material such as oxide, the presence of the second isolation trench increases the thickness of the insulating material between the first field plate and the active layer, and also increases the thickness of the insulating material between the gate and the active layer. The thickness of the insulating material between the active layers increases, which also has the effect of increasing the breakdown voltage BV.

Optionally, the first field plate is insulated from the gate.

Optionally, a first etching stop layer and an anti-reflective coating are further provided between the first electrode and the second dielectric material layer. In this alternative, the presence of the first etch stop layer facilitates fabrication of the second field plate.

Optionally, a second etching stop layer and an insulating layer are also provided on a side of the first field plate close to the active layer.

Optionally, a first spacer and a second spacer are also provided on the active layer, and the gate is located between the first spacer and the second spacer, where the first spacer is connected to the gate and the first doped region. Contact, the second spacer contacts the gate and the second doped region.

Optionally, the material of the first electrode includes one or more of the following: titanium nitride, titanium, and aluminum.

Optionally, the doping type of the first doping region is P type, and the doping type of the second doping region is N type; or, the doping type of the first doping region is N type, and the doping type of the second doping region The doping type is P type.

Optionally, the field plate material includes tungsten.

Optionally, the material of the dielectric material layer includes oxide.

Optionally, a third isolation trench and a fourth isolation trench are provided in the substrate, and the openings of the third isolation trench and the fourth isolation trench face the first dielectric material layer; the active layer is provided between the first isolation trench and the second isolation trench. between isolation tanks.

Optionally, a buried oxide layer and an epitaxial layer are also provided between the substrate and the active layer.

In a second aspect, a semiconductor device is provided, including: a substrate; an active layer provided on the substrate; the active layer includes a first doped region and a second doped region in contact with the first doped region, The first doped region and the second doped region have different doping types; at least two dielectric material layers disposed on the active layer; and a third field plate disposed in the at least two dielectric material layers, The three field plates penetrate at least two dielectric material layers, and the projection of the third field plate on the active layer overlaps with the second doped region. One end of the third field plate close to the active layer is insulated from the active layer.

In a third aspect, an integrated circuit is provided, including a packaging structure and a semiconductor device as described in any one of the above first and second aspects, where the semiconductor device is packaged inside the packaging structure.

A fourth aspect provides an electronic device, including a printed circuit board and the integrated circuit as described in the third aspect, the integrated circuit being connected to the printed circuit board.

In a fifth aspect, a method for manufacturing a semiconductor device is provided, including: making an active layer on a substrate; injecting dopants into the active layer to form a first doped region and a second doped region, the first doped region being The region is in contact with the second doped region, and the doping types of the first doped region and the second doped region are different; at least two dielectric material layers are made on the active layer; at least two dielectric material layers are made The field plate penetrates one or more dielectric material layers, and the projection of the field plate on the active layer overlaps with the second doped region. One end of the field plate close to the active layer is insulated from the active layer.

Among them, the technical effects brought about by any one of the possible implementation methods of the second aspect and the fifth aspect can be referred to the technical effects brought by any different implementation methods of the above-mentioned first aspect, and will not be described again here.

Description of the drawings

Figure 1 is a schematic structural diagram of a terminal provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a base station provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 6 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 7 is a schematic structural diagram of a PN junction provided by yet another embodiment of the present application;

Figure 8 is a schematic structural diagram of a PN junction provided by another embodiment of the present application;

Figure 9 is a schematic structural diagram of a PN junction provided by yet another embodiment of the present application;

Figure 10 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 11 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 12 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 13 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 14 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 15 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 16 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 17 is a schematic diagram of the principle of a semiconductor device provided by yet another embodiment of the present application;

Figure 18 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 19 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 20 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 21 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 22 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 23 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 24 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 25 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 26 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 27 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 28 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 29 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 30 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 31 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

Figure 32 is a schematic structural diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 33 is a simulation schematic diagram of a semiconductor device provided by another embodiment of the present application;

Figure 34 is a schematic diagram of the voltage and current characteristic curve of a semiconductor device provided by another embodiment of the present application;

Figure 35 is a simulation schematic diagram of a semiconductor device provided by yet another embodiment of the present application;

Figure 36 is a schematic diagram of the voltage and current characteristic curve of a semiconductor device provided by yet another embodiment of the present application;

Figure 37 is a schematic diagram of the voltage and current characteristic curve of a semiconductor device provided by yet another embodiment of the present application;

Figure 38 is a flow chart of a manufacturing method of a semiconductor device provided by yet another embodiment of the present application;

Figure 39 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 40 is a schematic diagram 2 of the structure of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 41 is a schematic structural diagram three of a semiconductor device in a method for manufacturing a semiconductor device provided by yet another embodiment of the present application;

Figure 42 is a schematic diagram 4 of the structure of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 43 is a schematic diagram 5 of the structure of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 44 is a schematic diagram 6 of the structure of a semiconductor device in a method for manufacturing a semiconductor device provided by yet another embodiment of the present application;

Figure 45 is a schematic diagram 7 of the structure of a semiconductor device in a method for manufacturing a semiconductor device provided by yet another embodiment of the present application;

Figure 46 is a schematic diagram 8 of the structure of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 47 is a schematic structural diagram 9 of a semiconductor device in a method for manufacturing a semiconductor device provided by yet another embodiment of the present application;

Figure 48 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 49 is a schematic structural diagram 11 of a semiconductor device in a method for manufacturing a semiconductor device provided by yet another embodiment of the present application;

Figure 50 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 51 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to another embodiment of the present application;

Figure 52 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to another embodiment of the present application;

Figure 53 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to another embodiment of the present application;

Figure 54 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 55 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to another embodiment of the present application;

Figure 56 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 57 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 58 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

Figure 59 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application;

FIG. 60 is a schematic structural diagram of a semiconductor device in a method for manufacturing a semiconductor device according to yet another embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments.

The technical terms used in the embodiments of this application are explained below:

Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; among them, semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, with equal internal electron and hole concentrations, is called an intrinsic semiconductor. Semiconductors doped with a certain amount of impurities are called impurity semiconductors or extrinsic semiconductors. Among them, impurities doped into impurity semiconductors can provide a certain concentration of carriers (such as holes or electrons). Impurity semiconductors doped with electron impurities (such as 5-valent phosphorus element) are also called electronic semiconductors or N (negative, negative)-type semiconductor, an impurity semiconductor doped with hole impurities (such as trivalent boron element) is also called a hole-type semiconductor or P (positive, positive)-type semiconductor. Doping can improve the properties of intrinsic semiconductors. Conductivity, generally the greater the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiment of the present application, the layer structure in a semiconductor device made of semiconductor (or semiconductor material) is called a semiconductor material layer.

Semiconductor devices include diodes, bipolar junction transistors (BJT) (also known as bipolar transistors, semiconductor transistors), metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistor, MOSFET, referred to as MOS) As well as double-diffused metal oxide semiconductor field effect transistor (double-diffused metal oxide semiconductor, DMOS), etc. Among them, MOS includes P-type MOS (positive channel metal oxide semiconductor, PMOS) and N-type MOS (negative channel metal oxide semiconductor, NMOS). PMOS and NMOS are integrated together to form a complementary metal oxide semiconductor (CMOS). .

BCD process: BCD process is a monolithic integration process technology, which refers to the production of different semiconductor devices such as transistors BJT, CMOS and DMOS on the same integrated circuit. Therefore, the integrated circuit produced using the BCD process not only has the characteristics of high transconductance and strong load drive of BJT, but also has the characteristics of high integration and low power consumption of CMOS, and has the high voltage resistance and fast switching speed of DMOS. specialty.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In this application, "at least one (layer)" refers to one (layer) or multiple (layers), and "multiple (layers)" refers to two (layers) or more than two (layers). "And/or" describes the association of associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b or c can mean: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can It can be single or multiple. In addition, in the embodiments of the present application, words such as “first” and “second” do not limit the number and order.

In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the schematically placed directions of the components in the drawings. It should be understood that these directional terms are relative concepts and they are used relative to each other. The descriptions and clarifications may change accordingly according to the changes in the orientation of the components in the drawings.

It should be noted that in this application, words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "such as" is not intended to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

The integrated circuits provided by the embodiments of the present application can be used in various electronic devices. The electronic devices can be different types of terminals such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices. The electronic devices can also be networks such as base stations. equipment. The embodiments of this application do not place any special restrictions on the specific form of the electronic device.

Referring to FIG. 1 , FIG. 1 shows a schematic structural diagram of a terminal 100 . The terminal 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone interface 170D, sensor module 180, camera 190 and display screen 191, etc.

It can be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the terminal 100. In other embodiments of the present application, the terminal 100 may include more or fewer components than shown in the figures, or some components may be combined, or some components may be separated, or may be arranged differently. The components illustrated may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (GPU), and an image signal processor. (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors.

The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in processor 110 is cache memory. This memory may hold instructions or data that have been recently used or recycled by processor 110 . If the processor 110 needs to use the instructions or data again, it can be called directly from the memory. Repeated access is avoided and the waiting time of the processor 110 is reduced, thus improving the efficiency of the system.

In some embodiments, processor 110 may include one or more interfaces. Interfaces may include integrated circuit (inter-integrated circuit, I2C) interface, integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, pulse code modulation (pulse code modulation, PCM) interface, universal asynchronous receiver and transmitter (universal asynchronous receiver/transmitter (UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and /or universal serial bus (USB) interface, etc.

The charging management module 140 is used to receive charging input from the charger. Among them, the charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from the wired charger through the USB interface 130 . In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through the wireless charging coil of the terminal 100 . While charging the battery 142, the charging management module 140 can also provide power to the terminal through the power management module 141.

The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 191, the camera 190, the wireless communication module 160, and the like. The power management module 141 can also be used to monitor battery capacity, battery cycle times, battery health status (leakage, impedance) and other parameters. In some other embodiments, the power management module 141 may also be provided in the processor 110 . In other embodiments, the power management module 141 and the charging management module 140 may also be provided in the same device.

The wireless communication function of the terminal 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in terminal 100 may be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example: Antenna 1 can be reused as a diversity antenna for a wireless LAN. In other embodiments, antennas may be used in conjunction with tuning switches.

The mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied to the terminal 100. The mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (LNA), etc. The mobile communication module 150 can receive electromagnetic waves through the antenna 1, perform filtering, amplification and other processing on the received electromagnetic waves, and transmit them to the modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least part of the functional modules of the mobile communication module 150 may be disposed in the processor 110 . In some embodiments, at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be provided in the same device.

A modem processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays an image or video through the display screen 191 . In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be independent of the processor 110 and may be provided in the same device as the mobile communication module 150 or other functional modules.

The wireless communication module 160 can provide applications on the terminal 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) network), Bluetooth (bluetooth, BT), and global navigation satellite system. (global navigation satellite system, GNSS), frequency modulation (FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions. The wireless communication module 160 may be one or more devices integrating one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 . The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.

In some embodiments, the antenna 1 of the terminal 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the terminal 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (code division multiple access, CDMA), broadband code Wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology, etc. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).

The terminal 100 implements the display function through the GPU, the display screen 191, and the application processor. The GPU is an image processing microprocessor and is connected to the display screen 191 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or alter display information.

The display screen 191 is used to display images, videos, etc. The display screen 191 includes a display panel. The display panel can use a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode). diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diode (quantum dot light emitting diode, QLED), etc. In some embodiments, the terminal 100 may include 1 or N display screens 191, where N is a positive integer greater than 1. The terminal 100 can implement the shooting function through the ISP, camera 190, video codec, GPU, display screen 191 and application processor.

The ISP is used to process the data fed back by the camera 190 . For example, when taking a photo, the shutter is opened, the light is transmitted to the camera sensor through the lens, the light signal is converted into an electrical signal, and the camera sensor passes the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP may be provided in the camera 190.

Camera 190 is used to capture still images or video. The object passes through the lens to produce an optical image that is projected onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to convert it into a digital image signal. ISP outputs digital image signals to DSP for processing. DSP converts digital image signals into standard RGB, YUV and other format image signals. In some embodiments, the terminal 100 may include 1 or N cameras 190, where N is a positive integer greater than 1.

The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement the data storage function. Such as saving music, videos, etc. files in external memory card.

Internal memory 121 may be used to store one or more computer programs including instructions. The processor 110 can execute the above instructions stored in the internal memory 121 to cause the terminal 100 to execute various functional applications and data processing. The internal memory 121 may include a program storage area and a data storage area. Among them, the stored program area can store the operating system; the stored program area can also store one or more application programs (such as gallery, contacts, etc.). The storage data area can store data created during use of the terminal 100 (such as photos, contacts, etc.). In addition, the internal memory 121 may include high-speed random access memory, and may also include non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (UFS), etc. In other embodiments, the processor 110 causes the terminal 100 to perform various functional applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The terminal 100 can implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone interface 170D, and the application processor. Such as music playback, recording, etc.

The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. Audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be provided in the processor 110 , or some functional modules of the audio module 170 may be provided in the processor 110 .

Speaker 170A, also called "speaker", is used to convert audio electrical signals into sound signals. The terminal 100 can listen to music through the speaker 170A, or listen to a hands-free call.

Receiver 170B, also called "earpiece", is used to convert audio electrical signals into sound signals. When the terminal 100 answers a call or a voice message, the voice can be heard by bringing the receiver 170B close to the human ear.

Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak close to the microphone 170C with the human mouth and input the sound signal to the microphone 170C. The terminal 100 may be provided with one or more microphones 170C. In other embodiments, the terminal 100 may be provided with two microphones 170C, which in addition to collecting sound signals, may also implement a noise reduction function. In other embodiments, the terminal 100 can also be equipped with three, four or more microphones 170C to collect sound signals, reduce noise, identify sound sources, and implement directional recording functions, etc.

The headphone interface 170D is used to connect wired headphones. The headphone interface 170D may be a USB interface 130, or may be a 3.5mm open mobile terminal platform (OMTP) standard interface, or a Cellular Telecommunications Industry Association of the USA (CTIA) standard interface.

The sensor module 180 may include a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

In the embodiment of the present application, the touch sensor is also called a "touch device". The touch sensor can be provided on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, which is also called a "touch screen". Touch sensors are used to detect touches on or near them. The touch sensor can pass the detected touch operation to the application processor to determine the touch event type. Visual output related to touch operations can be provided through the display screen. In other embodiments, a touch panel including a touch sensor array formed by multiple touch sensors may also be provided on the surface of the display panel in a plug-in form. In other embodiments, the touch sensor may be located at a different location than the display screen 191 . In the embodiments of the present application, the form of the touch sensor is not limited. For example, it may be a capacitor, a varistor, or other devices.

In addition, the above-mentioned terminal 100 may also include one or more components such as buttons, motors, indicators, and subscriber identification module (subscriber identification module, SIM) card interfaces. The embodiments of the present application do not impose any restrictions on this.

Referring to Figure 2, the electronic device provided by the embodiment of the present application takes a 5G base station as an example. The 5G base station can be divided into a baseband processing unit (base band unit, BBU) - an active antenna unit (active antenna unit, AAU), a centralized Unit-distributed unit (central unit-distribute unit, CU-DU)-AAU, BBU-radio remote unit (remote radio unit, RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station ( 5G node base station, gNB) and other different architectures. Taking the base station of BBU-RRU architecture as an example, as shown in Figure 2, the base station includes BBU21, RRU22 and antenna 23; BBU21 and RRU22 are connected through optical fiber, and the interface between the two is based on the open common public radio frequency interface (common public radio interface (CPRI) and open base station architecture initiative (OBSAI). Among them, the BBU21 processes the generated baseband signal through the RRU22 and sends it to the antenna 23 for transmission. The RRU 22 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier 223 (power amplifier, PA) and a filter 224. Among them, the digital intermediate frequency module 221 is used for modulation and demodulation, digital up and down conversion, digital to analog converter (D/A), etc. of the baseband signal transmitted by optical fiber to form an intermediate frequency signal; the transceiver module 222 completes the conversion of the intermediate frequency signal into a radio frequency signal. Signal transformation; the power amplifier 223 is used to amplify the low-power radio frequency signal; the filter 224 is used to filter the radio frequency signal, and then transmit the radio frequency signal through the antenna 23.

The integrated circuit provided by the embodiment of the present application can be applied to the terminal 100 shown in Figure 1 or the base station shown in Figure 2. For example, the integrated circuit provided by the embodiment of the present application can be a power management integrated circuit. , PMIC) is connected to a printed circuit board (PCB) and is used in the charging management module 140 shown in Figure 1. Alternatively, the integrated circuit provided in the embodiment of the present application can be a display driver integrated circuit (display driver integrated circuit). circuit (DDIC) is connected to the PCB and applied to the display screen 191 shown in Figure 1, or the integrated circuit provided in the embodiment of the present application can be connected to the PCB and applied to the BBU21 or RRU22 of the base station provided in Figure 2. Of course, the specific application scenarios are not limited to the terminal shown in Figure 1 and the base station shown in Figure 2.

Among them, embodiments of the present application provide an integrated circuit. As shown in FIG. 3 , the integrated circuit 30 includes a semiconductor device 31 and a packaging structure 32 , wherein the semiconductor device 31 is packaged inside the packaging structure 32 . As shown in FIG. 3 , the packaging structure 32 specifically includes: a heat dissipation substrate 321 . In order to improve the conductivity and heat dissipation of the heat dissipation substrate 321 , the heat dissipation substrate 321 can be made of a composite material, such as a stack of copper Cu/molybdenum Mo/copper Cu. Structure: The semiconductor device 31 is bonded to the heat dissipation substrate 321 through sintered silver. Some of the electrodes of the semiconductor device 31 shown in Figure 3 are connected to the heat dissipation substrate 321. In addition, some of the electrodes of the semiconductor device 31 can also be wired through gold wires. The pins are bonded and connected to the pins, which are arranged on an insulating layer (which may be insulating ceramics, for example), and the insulating layer is bonded to the heat dissipation substrate 321 through an insulating adhesive. In addition, the packaging structure 32 includes a packaging shell 322, which is bonded to the heat dissipation substrate 321 through an insulating adhesive, and one end of the pin is exposed from the packaging structure to connect to other circuits, wherein the semiconductor device 31 is disposed in the packaging shell. 322 and the heat dissipation substrate 321 in the space surrounded.

Among them, semiconductor devices include diodes, BJT transistors, DMOS, etc.

Referring to FIG. 4 , an embodiment of the present application provides a schematic structural diagram of a diode 40 . The diode 40 is composed of a doped region 41 and a doped region 42 embedded in the doped region 41 . The doped region 41 and The doping type of the doping region 42 is different, and the doping range of the doping region 42 is smaller than the doping range of the doping region 41 . In addition, an insulating layer 43 is provided above the doped region 41, and the insulating layer 43 is in contact with the doped region 42. A metal electrode 45 is provided on the doped region 41, and the metal electrode 45 penetrates the insulating layer 43, and the metal electrode 45 is connected to Lead wire; a metal electrode 44 is provided on the doped region 42, the metal electrode 44 penetrates the insulating layer 43, and the metal electrode 44 is connected to a lead wire. For example, the doping type of the doping region 41 shown in FIG. 4 is N type, and the doping type of the doping region 42 is P type, then the metal electrode 44 is the anode (anode, +) of the diode 40, and the metal electrode 45 is the cathode (cathode, -) of the diode 40. In the diode 40, the doped region 41 and the doped region 42 form a PN junction structure. When the metal electrode 44 is connected to the positive voltage and the metal electrode 45 is connected to the negative voltage, FIG. The doped region 41 and the doped region 42 shown in Figure 4 form a forward-biased PN junction, and the diode 40 is turned on; when the metal electrode 44 is connected to a negative voltage and the metal electrode 45 is connected to a positive voltage, the doped region shown in Figure 4 The region 41 and the doped region 42 form a PN junction with reverse bias, and the diode 40 is turned off, so that the diode 40 has unidirectional conductivity.

Referring to FIG. 5 , an embodiment of the present application provides a schematic structural diagram of a transistor 50 , in which the transistor 50 consists of a doped region 51 , a doped region 52 embedded in the doped region 51 , and a doped region 52 embedded in the doped region 52 . The doped region 53 in The doping range of 53 is smaller than the doping range of doped region 51 . In addition, an insulating layer 57 is provided above the doped region 51 . The insulating layer 57 is in contact with the doped region 52 , and the insulating layer 57 is also in contact with the doped region 53 . A metal electrode 56 is provided on the doped region 51. The metal electrode 56 penetrates the insulating layer 57. The metal electrode 56 is connected to a lead. The metal electrode 56 is the collector (C) of the triode; a metal electrode 56 is provided on the doped region 52. The metal electrode 55 penetrates the insulating layer 57 and is connected to a lead. The metal electrode 55 is the base electrode (B) of the triode; a metal electrode 54 is provided on the doped region 53. The metal electrode 54 Penetrating the insulating layer 57, a metal electrode 54 is connected to a lead, and the metal electrode 54 is the emitter electrode (E) of the triode. For example, in the transistor 50 shown in FIG. 5 , when the doping type of the doping region 51 and the doping region 53 is N type, and the doping type of the doping region 52 is P type, the transistor 50 is also called It is an NPN transistor. Alternatively, when the doping type of the doping region 51 and the doping region 53 is P type, and the doping type of the doping region 52 is N type, the transistor 50 is also called a PNP type transistor. Whether it is an NPN transistor or a PNP transistor, a PN junction will be formed between the doped region 51 and the doped region 52. This PN junction is called a collector junction, and the doped region 52 and the doped region 53 will also form a PN junction. A PN junction is called an emitter junction. The triode uses the forward bias or reverse bias of the emitter junction and collector junction to achieve a predetermined function.

Referring to Figure 6, an embodiment of the present application provides a schematic structural diagram of a DMOS. Specifically, the DMOS includes a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) and a lateral double diffusion Metal oxide semiconductor field effect transistor (lateral double-diffused metal oxide semiconductor, LDMOS), Figure 6 shows LDMOS. The LDMOS 60 includes a substrate 61, an active layer is provided on the substrate 61, the active layer includes a doped region 62 and a doped region 63 in contact with the doped region 62, the doped region 62 and the doped region 63 The doping types of , a doped region 66 is also provided in the doped region 63. The doped region 66 is not in contact with the doped region 62. The doped region 62 and the doped region 64 have the same doping type. The doped region 65 and the doped region 64 are not in contact with each other. The doping type of the region 63 and the doped region 66 is the same. A gate electrode 68 is also provided on the active layer. The gate electrode 68 and the active layer are insulated by an insulating layer 67. The gate electrode 68 covers the contact surface between the doped region 62 and the doped region 63. There is also a gate electrode 68 on the active layer. There are

spacers

69a and 69b, and the gate 68 is located between the

spacers

69a and 69b. The spacers 69a are in contact with the gate 68 and the doped region 62, and the spacers 69a are not in contact with the doped region 65. The spacer 69b is in contact with the gate 68 and the doped region 63, and the spacer 69b is not in contact with the doped region 66. An electrode (B) is drawn out in the doped region 64 so that the doped region 62 receives a fixed voltage value when the LDMOS is working. An electrode (B) is drawn out in the doped region 65 as the source (source, S) of the LDMOS. Usually B and S are short-circuited. . An electrode is drawn out from the gate electrode 68 as the gate electrode (G) of the LDMOS, and an electrode is drawn out from the doped region 66 as the drain electrode (drain, D) of the LDMOS. For example, when the doping type of the doping region 62 and the doping region 64 is P type, and the doping type of the

doping region

65 , 63 and 66 is N type, the LDMOS is also called It is N-type LDMOS (NLDMOS). When the doping type of the doping region 62 and the doping region 64 is N type, and the doping type of the

doping region

65 , 63 and 66 is P type, the LDMOS is also called P-type LDMOS. (PLDMOS). Whether it is NLDMOS or PLDMOS, a PN junction structure is formed between the doped region 62 and the doped region 63. When the PN junction is reverse biased, the LDMOS does not conduct, and when the PN junction is forward biased, the LDMOS conducts.

It can be seen that the above-mentioned semiconductor devices all contain PN junctions, and the performance of the PN junction also directly affects the performance of the semiconductor device. Among them, the breakdown voltage (breakdown voltage, BV) of the semiconductor device also depends on the semiconductor device to a certain extent. The breakdown voltage BV of the PN junction in the device.

Referring to FIG. 7 , an embodiment of the present application provides a schematic structural diagram of a PN junction, in which a P-type semiconductor is embedded in an N-type semiconductor. There are two contact surfaces between the N-type semiconductor and the P-type semiconductor. In an ideal state, state, the two contact surfaces are mutually perpendicular planes. At the two contact surfaces, electrons in the N-type semiconductor diffuse to the P-type semiconductor, and holes in the P-type semiconductor diffuse to the N-type semiconductor, so that the two A depletion layer is formed at the contact surface. When the PN junction is reverse biased, that is, when the P-type semiconductor is connected to a low voltage through terminal 71 and the N-type semiconductor is connected to a high voltage through terminal 72, the existence of the depletion layer allows the PN junction to withstand The reverse bias voltage is within a predetermined voltage value. When the reverse bias voltage that the PN junction withstands is greater than the predetermined voltage value, the PN junction will be broken down. Among them, the above-mentioned predetermined voltage value is the breakdown voltage BV.

However, as shown in FIG. 8 , when making a PN junction in an actual process, a P-type semiconductor window 73 is often provided above the N-type semiconductor, and then P-type semiconductor is injected from the P-type semiconductor window 73 through an ion implantation process. Dopants form a P-type semiconductor embedded in an N-type semiconductor. In the actual ion implantation process, due to the inability to control the diffusion direction of the injected P-type dopant, the contact surface between the N-type semiconductor and the P-type semiconductor often appears curved. The curved contact surface also causes the depletion layer to bend. Then, when the PN junction is reverse biased and the depletion layer bends, it is easy to concentrate the high voltage connected to the terminal 72 to form an electric field intensity. Referring to the electric field intensity polyline 74 shown in Figure 8, the concentrated electric field intensity 741, the electric field intensity 741 It is possible to break down the depletion layer of the currently bent PN junction, thereby causing the breakdown voltage BV of the PN junction to be low.

In order to solve the problem of low breakdown voltage of the PN junction produced by the existing manufacturing process, as shown in Figure 9, it is usually chosen to set a field plate (FP) on the contact surface of the PN junction shown in Figure 8 )75, the field plate 75 does not change the curvature of the contact surface between the N-type semiconductor and the P-type semiconductor, but due to the existence of the field plate 75, the curvature of the depletion layer of the PN junction will be improved, and the electric field in the PN junction also been improved. For example, when the PN junction is reverse biased, the high voltage connected to the terminal 72 will form an electric field intensity 742 at the edge of the field plate 75 close to the terminal 72, and form an electric field intensity 741 at the contact surface between the N-type semiconductor and the P-type semiconductor. The electric field strength 742 is greater than the electric field strength 741. That is to say, under the action of the field plate 75, the electric field strength concentrated in the place where the depletion layer bends will decrease, thereby increasing the breakdown voltage BV of the PN junction.

Although the silicon limit defines that the breakdown voltage BV is proportional to the specific on-state resistance (Ron,sp), setting the field plate can not only increase the breakdown voltage BV of the semiconductor device, but also will not affect the semiconductor device. The specific on-resistance Ron,sp has an impact. Therefore, field plates are usually used in the manufacturing process of semiconductor devices.

Referring to Figure 10, taking LDMOS as an example, during the production process of LDMOS, a field plate 900 is usually installed in the LDMOS 60 shown in Figure 6 to obtain a high breakdown voltage BV and a low specific on-resistance Ron,sp LDMOS, wherein the field plate 900 shown in Figure 10 is a stepped field plate, the stepped field plate is disposed on the doped region 63, the doped region 63 is connected to the high voltage through the doped region 66, and the stepped field plate 900 and the gate 68 are insulated by spacers 69b, and the projection of the stepped field plate 900 on the active layer does not overlap with the doped region 66.

Referring to Figure 11, an embodiment of the present application provides a semiconductor device 80. The semiconductor device 80 can be any semiconductor device with a PN junction structure such as a diode, a BJT transistor, or a DMOS. The semiconductor device 80 includes: a substrate 81; Active layer 82 provided on the substrate 81; the active layer 82 includes a doped region 821 and a doped region 822 in contact with the doped region 821, and the doped region 821 and the doped region 822 have different doping types. ; At least two dielectric material layers 83 provided on the active layer 82; and at least two field plates 84 provided in the dielectric material layer 83, the field plates 84 penetrating one or more dielectric material layers 83, Moreover, the projection of the field plate 84 on the active layer 82 overlaps with the doped region 822 , and one end of the field plate 84 close to the active layer 82 is insulated from the active layer 82 .

Exemplarily, the dielectric material layer in the semiconductor device 80 shown in FIG. 11 includes a dielectric material layer 83a, a dielectric material layer 83b and a dielectric material layer 83m, wherein the material of the dielectric material layer 83 is an oxide, The dielectric material layer 83 is an insulating material. The dielectric material layer 83a, the dielectric material layer 83b and the dielectric material layer 83m are sequentially arranged on the active layer 82 in a direction away from the substrate 81. The dielectric material layer 83a is used for connection. The active layer 82 of the semiconductor device and the first metal electrode layer, so the dielectric material layer 83a is also called the inter layer dielectric material layer (ILD), the dielectric material layer 83b and the dielectric material layer 83m It is mainly used to separate two metal electrode layers. Therefore, the dielectric material layer 83b and the dielectric material layer 83m are also called inter-metal dielectric material layers (inter metal dielectric, IMD). The field plate 84 in the semiconductor device 80 shown in FIG. 11 includes a field plate 84a and a field plate 84b, wherein the field plate 84a penetrates the dielectric material layer 83a, and the field plate 84b penetrates the dielectric material layer 83a and the dielectric material layer 83b, Moreover, the field plate 84a and the field plate 84b are not in contact with the active layer 82. Therefore, since the dielectric material layer 83a is an insulating material, it means that the field plate 84a is insulated from the field plate 84b and the active layer 82. The material of the field plate may be tungsten or other conductive materials, which is not limited in the embodiments of the present application.

For example, the field plate 84a and the field plate 84b shown in FIG. 11 may be in contact or not in contact, and the embodiment of the present application does not limit this.

For example, when the semiconductor device 80 includes a gate, the gate is usually provided on the active layer 82 , and the gate covers the contact surface between the doped region 821 and the doped region 822 , then the semiconductor device with the gate is A field plate is provided in the device 80. The above-mentioned field plate 84 is insulated from the gate electrode, and the projection of the field plate 84 on the active layer 82 does not overlap with the doped region 821. The field plate 84 is on the active layer 82. The projection of overlaps with the doped region 822. When the semiconductor device 80 does not include a gate, a field plate is provided in the semiconductor device 80 without a gate. The projection of the field plate 84 on the active layer 82 overlaps with the doped region 821, and the field plate 84 has The projection on the source layer 82 overlaps with the doped region 822 .

It should be noted that the semiconductor device 80 may also include more field plates, and may also include more or less dielectric material layers. The embodiments of the present application do not specify the number of dielectric material layers and the number of field plates. The number is not limited.

For example, when the doped region 822 is connected to a high voltage, if there is no field plate 84 at this time, the high voltage connected to the doped region 822 will be concentrated at the contact surface between the doped region 821 and the doped region 822 , the concentrated electric field intensity may break down the contact surface between the doped region 821 and the doped region 822 . Then when the field plate 84 exists, when the doped region 822 is connected to the same high voltage, the projection of the field plate 84 on the active layer 82 away from the doped region 821 will form a first electric field intensity, and the field plate 84 will The projection on the active layer 82 will form a second electric field intensity on the side close to the doped region 821, and the first electric field intensity is greater than the second electric field intensity. Then the current contact surface between the doped region 821 and the doped region 822 is concentrated. The intensity of the electric field received is weakened, that is to say, the field plate 84 weakens the intensity of the electric field concentrated on the contact surface between the doped region 821 and the doped region 822, thereby causing the breakdown voltage BV of the semiconductor device 80 to become higher. At the same time, the field plate 84 is insulated from the active layer 82, so when the semiconductor device 80 is turned on, that is, when the doped region 821 and the doped region 822 are turned on, the field plate 84 will not affect the current carrying capacity in the active layer 82. It affects the transmission of electrons, which in turn affects the specific on-resistance Ron,sp of the semiconductor device, so as to obtain a semiconductor device with high breakdown voltage BV and low specific on-resistance Ron,sp.

Specifically, as shown in FIGS. 12 to 14 , the semiconductor device 80 may be a diode.

Referring to FIG. 12 , when the semiconductor device 80 is a diode, the semiconductor device 80 includes: an active layer 82 on a substrate 81 ; the active layer 82 includes a doped region 821 and a doped region in contact with the doped region 821 822, wherein the doping type of the doping region 821 is P type, the doping type of the doping region 822 is N type, the doping region 821 contacts the doping region 822 to form a PN junction, the doping region 821 and the doping region 822 are in contact with each other to form a PN junction. Region 822 forms a diode. Among them, at least two layers of dielectric material layers are provided on the active layer 82. The at least two layers of dielectric material layers include a dielectric material layer 83a and a dielectric material layer 83b. On the side of the active layer 82 away from the substrate 81 A dielectric material layer 83a is provided, and a dielectric material layer 83b is provided on the side of the dielectric material layer 83a away from the substrate 81; at least two field plates are provided in the dielectric material layer, and the at least two field plates include a field plate 84a. and field plate 84b; field plate 84a penetrates dielectric material layer 83a; field plate 84b penetrates dielectric material layer 83a and dielectric material layer 83b. The field plate is insulated from the active layer. Specifically, in order to ensure the insulation between the field plate 84a and the active layer 82, an insulating layer 851 is provided on the side of the field plate 84a close to the active layer 82. The material of the insulating layer 851 It is silicon dioxide (SiO ₂ ), or it can also be other oxides. In addition, in order to ensure the range of the field plate 84a, an etching stop layer 852 of the field plate 84a is usually provided on the side of the field plate 84a close to the active layer 82, specifically, an etching stop layer 852 is provided on the side of the insulating layer 851 close to the field plate 84a. The material of the etching stop layer 852 may specifically be silicon nitride (SiN), or may be other nitrides. In order to ensure the insulation between the field plate 84b and the active layer 82, the field plate 84b is usually arranged not to contact the active layer 82, and the field plate 84b and the active layer 82 are insulated by a dielectric material layer 83a.

For example, a stacked structure such as an etching stop layer 852 - an insulating layer 851 - an etching stop layer 852 - an insulating layer 851 may also be provided on the side of the field plate 84a close to the active layer 82. This is not the case in the embodiments of the present application. Make limitations.

For example, when the field plate 84a and the field plate 84b do not have a certain voltage value, the field plate 84a and the field plate 84b will be in a floating state, which will make the stability of the semiconductor device 80 worse. Therefore, a certain voltage value needs to be given to the field plate 84a and the field plate 84b. For example, an electrode 861a is usually provided between the field plate 84a and the dielectric material layer 83b. The electrode 861a can be connected to a first predetermined voltage to To make the voltage of the field plate 84a be the first predetermined voltage, an electrode 862a is also provided on the side of the field plate 84b away from the dielectric material layer 83a. The electrode 862a can also be connected to the second predetermined voltage so that the voltage of the field plate 84b is second predetermined voltage. It should be noted that the first predetermined voltage and the second predetermined voltage may be the same or different. When the field plate 84a is in contact with the field plate 84b, any one of the

electrodes

861a and 862a can be connected to a predetermined voltage; when the field plate 84a is not in contact with the field plate 84b, the electrode 861a and the electrode 862a can be connected. Each is connected to a predetermined voltage. The materials of the electrode 861a and the electrode 862a can be any conductive material, and the materials of the electrode 861a and the electrode 862a can include titanium nitride (TiN), titanium (Ti), aluminum (Al), etc., for example, titanium nitride The sandwich structure (Ti-TiN-Al-TiN-Ti) formed of titanium, titanium and aluminum is the most commonly used, especially when the electrode 861a is set to a sandwich structure (Ti-TiN-Al-TiN-Ti), the sandwich structure can be used as an adhesive. The lamination layer can increase the direct adhesion between the electrode 861a and the oxide in the dielectric material layer 83a; it can also improve electron migration (EM) to improve the performance of the semiconductor device 80; and can also serve as an engraving for the field plate 84b. Erosion stop layer.

As shown in Figure 12, since the doping type of the doped region 821 is P type, and the doping type of the doped region 822 is N type, therefore, the doped region 821 leads to the electrode as the anode of the diode, and the doped region 822 leads to The electrode serves as the cathode of the diode. However, when the diode is connected into a circuit and used in electronic equipment, it may also happen that the cathode is connected to a high voltage. Therefore, when the cathode is connected to a high voltage, the diode is reverse biased, and in order to control the diode not to be reversed The bias voltage breaks down, and the projection of the field plate 84a on the active layer 82 overlaps with the doped region 821, and the projection of the field plate 84a on the active layer 82 overlaps with the doped region 822. The field plate The projection of 84b on the active layer 82 does not overlap with the doped region 821, and the projection of the field plate 84b on the active layer 82 overlaps with the doped region 822.

Referring to FIG. 12 , in order to facilitate the production of the field plate 84b, an etching stop layer 863a and an anti-reflective coating 864a of the field plate 84b are also provided between the electrode 861a and the dielectric material layer 83b. Specifically, the etching stop layer 863a may be a nitride, such as silicon nitride (SiN), and the anti-reflective coating 864a may be a nitride oxide, such as silicon oxynitride (SiON). For example, a stacked structure of etching stop layer 863a-anti-reflective coating 864a-etching stop layer 863a-anti-reflective coating 864a may also be provided between the electrode 861a and the dielectric material layer 83b. Implementation of the present application This example does not limit this.

Referring to Figure 13, based on the semiconductor device 80 shown in Figure 12, a gate electrode 87 can also be provided on the active layer 82, and the gate electrode 87 and the active layer 82 are insulated by an insulating layer 88; wherein the gate electrode 87 covers the doped The contact surface between the doped region 821 and the doped region 822. Spacers 89a and 89b are also provided on the active layer 82. The gate 87 is located between the

spacers

89a and 89b. The spacers 89a are in contact with the gate 87 and the doped region 821, and the spacers 89b are in contact with the gate 87 and the doped region 821. Gate 87 and doped region 822 are in contact. Furthermore, the field plate 84a is insulated from the gate electrode 87. At this time, since the gate electrode 87 covers the contact surface between the doped region 821 and the doped region 822, the field plate 84a provided at this time is on the active layer 82. There is no overlap between the projection and the doped region 821, and there is an overlap between the projection of the field plate 84a on the active layer 82 and the doped region 822, and there is no overlap between the projection of the field plate 84b on the active layer 82 and the doped region 821. overlap, and the projection of the field plate 84b on the active layer 82 overlaps with the doped region 822.

Referring to FIG. 14 , when the semiconductor device 80 is a diode, only the field plate 84 b shown in FIG. 12 may be provided. Specifically, since only the field plate 84 b exists, the field plate 84 b needs to cover the doped region 821 and the doped region 821 . The contact surface of the region 822 , that is to say, the projection of the field plate 84 b on the active layer 82 overlaps with the doped region 821 , and the projection of the field plate 84 b on the active layer 82 overlaps with the doped region 822 . And the field plate 84b penetrates the dielectric material layer 83a and the dielectric material layer 83b, and the side of the field plate 84b close to the active layer 82 is insulated from the active layer 82. Among them, the field plate 84b can also achieve the purpose of increasing the breakdown voltage BV of the diode.

Referring to FIG. 15 , the semiconductor device 80 may also be a triode BJT.

Referring to FIG. 15 , when the semiconductor device 80 is a triode, the semiconductor device 80 includes: an active layer 82 on a substrate 81 ; the active layer 82 includes a doped region 821 and a doped region in contact with the doped region 821 822, a doped region 823 is also provided on the side of the doped region 821 away from the doped region 822. Among them, the doping type of the doping region 823 and the doping region 822 can be P type, the doping type of the doping region 821 can be N type, the doping region 822 and the doping region 821 contact to form a PN junction, the doping region 823 contacts the doped region 821 to form a PN junction, and the doped region 823, the doped region 821 and the doped region 822 form a PNP transistor. It is also possible that the doping type of the doping region 823 and the doping region 822 is N type, the doping type of the doping region 821 is P type, the doping region 821 and the doping region 822 are in contact to form a PN junction, and the doping region 821 A PN junction is formed in contact with the doped region 823, and the doped region 823, the doped region 821 and the doped region 822 form an NPN transistor.

Referring to FIG. 15 , at least two dielectric material layers are provided on the active layer 82 of the semiconductor device 80 , wherein the at least two dielectric material layers include a dielectric material layer 83 a and a dielectric material layer 83 b. A dielectric material layer 83a is provided on the side of the layer 82 away from the substrate 81, and a dielectric material layer 83b is provided on the side of the dielectric material layer 83a away from the substrate 81; at least two field plates are provided in the dielectric material layer. , the at least two field plates include a field plate 84a and a field plate 84b; the field plate 84a penetrates the dielectric material layer 83a; the field plate 84b penetrates the dielectric material layer 83a and the dielectric material layer 83b. The field plate is insulated from the active layer. Specifically, in order to ensure the insulation between the field plate 84a and the active layer 82, an insulating layer 851 is provided on the side of the field plate 84a close to the active layer 82. The material of the insulating layer 851 It is silicon dioxide (SiO ₂ ), or it can also be other oxides. In addition, in order to ensure the range of the field plate 84a, an etching stop layer 852 of the field plate 84a is usually provided on the side of the field plate 84a close to the active layer 82, specifically, an etching stop layer 852 is provided on the side of the insulating layer 851 close to the field plate 84a. The material of the etching stop layer 852 may specifically be silicon nitride (SiN), or may be other nitrides. In order to ensure the insulation between the field plate 84b and the active layer 82, the field plate 84b is usually arranged not to contact the active layer 82, and the field plate 84b and the active layer 82 are insulated by a dielectric material layer 83a.

electrodes

Referring to Figure 15, whether it is a PNP type transistor or an NPN type transistor, the electrode extracted from the doped region 822 is used as the emitter electrode (E) of the triode; the electrode extracted from the doped region 821 is used as the base electrode (B) of the triode. ); the doped region 823 leads the electrode as the collector (C) of the triode. As an example, the field plate provided when the semiconductor device 80 is a triode is described. In the semiconductor device 80 shown in FIG. 15, whether it is an NPN type In a transistor or a PNP transistor, the emitter E is usually connected to a high voltage. Therefore, in the semiconductor device 80 shown in FIG. 15, the projection of the field plate 84a on the active layer 82 overlaps with the doped region 821, and the field plate 84a The projection of the field plate 84a on the active layer 82 overlaps with the doped region 822. The projection of the field plate 84a on the active layer 82 does not overlap with the doped region 823. The projection of the field plate 84b on the active layer 82 does not overlap with the doped region 823. The doped region 821 does not overlap, and the projection of the field plate 84b on the active layer 82 overlaps with the doped region 822. The projection of the field plate 84b on the active layer 82 does not overlap with the doped region 823. .

Referring to FIG. 15 , in order to facilitate the production of the field plate 84b, an etching stop layer 863a and an anti-reflective coating 864a of the field plate 84b are also provided between the electrode 861a and the dielectric material layer 83b. Specifically, the etching stop layer 863a may be a nitride, such as silicon nitride (SiN), and the anti-reflective coating 864a may be a nitride oxide, such as silicon oxynitride (SiON). For example, a stacked structure of etching stop layer 863a-anti-reflective coating 864a-etching stop layer 863a-anti-reflective coating 864a may also be provided between the electrode 861a and the dielectric material layer 83b. Implementation of the present application This example does not limit this.

It should be noted that when the semiconductor device 80 is a triode, only the field plate 84b shown in FIG. 15 may be provided. Specifically, since only the field plate 84b exists, the field plate 84b needs to cover the doped region 821 and the doped region. 822 , that is to say, the projection of the field plate 84 b on the active layer 82 overlaps with the doped region 821 , and the projection of the field plate 84 b on the active layer 82 overlaps with the doped region 822 . And the field plate 84b penetrates the dielectric material layer 83a and the dielectric material layer 83b, and the side of the field plate 84b close to the active layer 82 is insulated from the active layer 82. Among them, the field plate 84b can also achieve the purpose of increasing the breakdown voltage BV of the triode.

Referring to FIGS. 16 to 32 , the semiconductor device 80 may also be a DMOS. Specifically, FIGS. 16 to 32 take LDMOS as an example for explanation.

Referring to FIG. 16 , when the semiconductor device 80 is an LDMOS, the semiconductor device 80 includes: an active layer 82 on a substrate 81 ; the active layer 82 includes a doped region 821 and a doped region in contact with the doped region 821 822, wherein at least two dielectric material layers are provided on the active layer 82, and the at least two dielectric material layers include a dielectric material layer 83a and a dielectric material layer 83b, and a part of the active layer 82 away from the substrate 81 A dielectric material layer 83a is provided on one side, and a dielectric material layer 83b is provided on the side of the dielectric material layer 83a away from the substrate 81; at least two field plates are provided in the dielectric material layer, and the at least two field plates include field The field plate 84a and the field plate 84b; the field plate 84a penetrates the dielectric material layer 83a; the field plate 84b penetrates the dielectric material layer 83a and the dielectric material layer 83b. The field plate is insulated from the active layer. Specifically, in order to ensure the insulation between the field plate 84a and the active layer 82, an insulating layer 851 is provided on the side of the field plate 84a close to the active layer 82. The material of the insulating layer 851 It is silicon dioxide (SiO ₂ ), or it can also be other oxides. In addition, in order to ensure the range of the field plate 84a, an etching stop layer 852 of the field plate 84a is usually provided on the side of the field plate 84a close to the active layer 82, specifically, an etching stop layer 852 is provided on the side of the insulating layer 851 close to the field plate 84a. The material of the etching stop layer 852 may specifically be silicon nitride (SiN), or may be other nitrides. In order to ensure the insulation between the field plate 84b and the active layer 82, the field plate 84b is usually arranged not to contact the active layer 82, and the field plate 84b and the active layer 82 are insulated by a dielectric material layer 83a.

A stacked structure such as an etching stop layer 852 - an insulating layer 851 - an etching stop layer 852 - an insulating layer 851 may also be provided on the side of the field plate 84 a close to the active layer 82 , which is not limited in the embodiments of the present application.

electrodes

For example, when the semiconductor device 80 is an LDMOS, it also includes: a gate 87 provided on the active layer 82 , and the gate 87 and the active layer 82 are insulated by an insulating layer 88 ; wherein the gate 87 covers the doped region. The contact surface between 821 and doped region 822. Spacers 89a and 89b are also provided on the active layer 82. The gate 87 is located between the

spacers

When the semiconductor device 80 is an LDMOS, the gate 87 needs to be drawn out so that when the LDMOS is subsequently made into a circuit, a voltage can be applied to the gate 87 to control the LDMOS to be conductive or non-conductive. Specifically, as shown in FIG. 16 , a via hole 831a may be provided on the dielectric material layer 83a. The material of the via hole 831a specifically includes tungsten (W), and a via hole 831a may be provided between the dielectric material layer 83a and the dielectric material layer 83b. There is an electrode 861b, which is connected to the gate 87 through a via hole 831a; a via hole 832a is also provided on the dielectric material layer 83b. The material of the via hole 832a specifically includes tungsten (W), and the dielectric material layer 83b is away from the dielectric material. An electrode 862b is provided on the surface of the layer 83a, and the electrode 861b is connected to the electrode 862b through a via hole 832a. Then, when the electrode 862b or the electrode 861b is connected to the predetermined voltage, it means that the predetermined voltage is applied to the gate 87. When other electrodes are connected to the electrode 862b or the electrode 861b, it can also be said that the other electrodes are connected to the gate.

For example, referring to FIG. 16 , when the semiconductor device 80 is an LDMOS, the doped region 821 also includes a doped region 824 and a doped region 825 in contact with the doped region 824 . The doped region 824 and the doped region The doping type of the doping region 821 is the same, and the doping type of the doping region 825 is different from that of the doping region 821. The doping region 825 is close to the doping region 822 and is not in contact with the doping region 822. The doped region 822 also includes a doped region 826 , the doped region 826 has the same doping type as the doped region 822 , and the doped region 826 is not in contact with the doped region 821 . Among them, the doping concentration of the doping region 824, the doping region 825 and the doping region 826 is relatively high. Specifically, the doping concentration of the doping region 824, the doping region 825 and the doping region 826 is greater than or equal to 1e15 atoms/cubic. centimeters, the doping concentration of the doped region 821 and the doped region 822 is lower than the doping concentration of the doped region 824 , the doped region 825 and the doped region 826 . Specifically, when the doping type of the doping region 821 and the doping region 824 is P type, and the doping type of the doping region 822, the doping region 825 and the doping region 826 is N type, the LDMOS is also called NLDMOS; when the doping type of the doping region 821 and the doping region 824 is N type, and the doping type of the doping region 822, the doping region 825 and the doping region 826 is P type, the LDMOS is also called PLDMOS .

When the semiconductor device 80 is an LDMOS, the doped region 821 is also called the well region of the LDMOS, the doped region 822 is also called the drift region of the LDMOS, and the doped region 825 is also called the source region of the LDMOS. The doped region 826 is also called the drain area of LDMOS. Among them, the doped region 825 (source region) requires an extraction electrode as the source electrode (S) of the LDMOS, and the doping region 826 (drain region) requires an extraction electrode as the drain electrode (drain, D) of the LDMOS. At the same time, in order to ensure the stability of the device, the doped region 821 (well region) will also be led out of the electrode (body, B) through the doped region 824, so that a fixed voltage can be input to the doped region 821 when the LDMOS is operating normally. value, thereby preventing the doped region 821 from being in a floating state.

More specifically, in LDMOS, B and S are usually short-circuited. Referring to FIG. 16 , a via hole 831 b and a via hole 831 c may be provided on the dielectric material layer 83 a. The materials of the via hole 831 b and the via hole 831 c specifically include tungsten (W). The dielectric material layer 83 a and the dielectric material layer An electrode 861c is also provided between 83b. The electrode 861c is connected to the doped region 824 through a via hole 831b. The electrode 861c is connected to the doped region 825 through a via hole 831c. A via hole 832b is also provided on the dielectric material layer 83b. The material of 832b specifically includes tungsten (W). An electrode 862c is provided on the surface of the dielectric material layer 83b away from the dielectric material layer 83a. The electrode 861c is connected to the electrode 862c through the via hole 832b. Then when the electrode 862c or the electrode 861c is connected to the predetermined voltage, it means that the predetermined voltage is applied to the doped region 821 (well region), the doped region 824 and the doped region 825 (source region). When other electrodes and the electrode 862c or the electrode When the 861c is connected, it can also be said that the other electrodes are connected to the source.

In LDMOS, D usually needs to be connected to a high voltage. For example, a via 831d can be provided on the dielectric material layer 83a. The material of the via 831d specifically includes tungsten (W). The dielectric material layer 83a and the dielectric material An electrode 861d is also provided between the layers 83b, and the electrode 861d is connected to the doped region 826 through a via hole 831d; a via hole 832c is also provided on the dielectric material layer 83b, and the material of the via hole 832c specifically includes tungsten (W), dielectric An electrode 862d is provided on the surface of the material layer 83b away from the dielectric material layer 83a, and the electrode 861d is connected to the electrode 862d through a via hole 832c. Then, when the electrode 862d or the electrode 861d is connected to a predetermined voltage, it means that the predetermined voltage is applied to the doped region 822 (drift region) and the doped region 826 (drain region).

Specifically, referring to FIG. 16 , in order to facilitate the production of the field plate 84b, an etching stop layer 863a and an anti-reflective coating 864a of the field plate 84b are also provided between the electrode 861a and the dielectric material layer 83b. Specifically, the material of the etching stop layer 863a may be a nitride, such as silicon nitride (SiN), and the material of the anti-reflective coating 864a may be a oxynitride, such as silicon oxynitride (SiON). For example, a stacked structure such as an etching stop layer 863a - an anti-reflective coating 864a - an etching stop layer 863a - an anti-reflective coating 864a can also be provided on the electrode 861a and the dielectric material layer 83b. The embodiment of the present application is suitable for This is not limited.

Among them, the manufacturing process of the semiconductor device 80 is often to make a whole layer of semiconductor material and then etching. Therefore, the electrode 861a, the electrode 861b, the electrode 861c and the electrode 861d are made at the same time, and the semiconductor material layer on any electrode is also made at the same time. Then, an etching stop layer 863b and an anti-reflective coating 864b are also provided between the electrode 861b and the dielectric material layer 83b, wherein the via hole 832a passes through the etching stop layer 863b and the anti-reflective coating 864b and the electrode. 861b contacts; an etching stop layer 863c and an anti-reflective coating 864c are also provided between the electrode 861c and the dielectric material layer 83b, wherein the via hole 832b passes through the etching stop layer 863c and the anti-reflective coating 864c and contacts the electrode 861c ; An etching stop layer 863d and an anti-reflective coating 864d are also provided between the electrode 861d and the dielectric material layer 83b, wherein the via hole 832c passes through the etching stop layer 863d and the anti-reflective coating 864d to contact the electrode 861d.

Referring to FIG. 17 , an embodiment of the present application provides a schematic diagram of the principle of setting a field plate in LDMOS to increase the breakdown voltage. Wherein, when only the gate electrode 78 exists in the LDMOS, the gate electrode 78 covers the doped region 821 and the contact surface of the doped region 822, wherein the projection of a part of the gate electrode 78 on the active layer 82 exists with the doped region 822. Overlapping, this part of the gate 78 is also called the gate protection layer (poly shielding) 781. When the drain D of the LDMOS is connected to a high voltage, an electric field will also be formed on the edge of the gate protection layer 781 close to the drain D. Strength E11, however, the electric field strength E11 here is relatively large, and the dielectric layer here (that is, the insulating layer 88 between the gate electrode 78 and the active layer 82) is relatively thin, so that a large electric field strength E11 is possible The dielectric layer is broken down, so the gate protection layer 781 has limited improvement in the breakdown voltage BV of the LDMOS.

It should be noted that the breakdown voltage BV of the LDMOS is related to the maximum voltage that the depletion layer of the PN junction formed by the doped region 821 and the doped region 822 can withstand, and is also related to the dielectric layer of the gate 78 (that is, the gate electrode 78 and the It is related to the withstand voltage of the insulating layer 88) between the active layers 82. Generally, the withstand voltage of the dielectric layer of the gate 78 will be smaller. Therefore, in LDMOS, the breakdown voltage BV mainly depends on the dielectric layer of the gate 78. Withstand voltage.

Referring to Figure 17, a field plate 84a is provided on the side of the gate 78 close to the drain D. When the drain D of the LDMOS is connected to a high voltage, an electric field intensity E12 will also be formed on the edge of the field plate 84a close to the drain D. An electric field intensity E11 will also be formed at the edge of the gate protection layer 781 close to the drain D. The electric field intensity E12 is greater than the electric field intensity E11. At this time, the dielectric layer at the electric field intensity E12 (that is, between the field plate 84a and the active layer 82 The insulating layer (the insulating layer 851) shown in Figure 16 is thicker, so the larger electric field intensity E12 may not be enough to break down the dielectric layer here, so the gate protection layer 781 and the field plate 84a have no impact on the LDMOS. The increase in breakdown voltage BV has a certain effect.

A field plate 84b is provided on the side of the field plate 84a close to the drain D. When the drain D of the LDMOS is connected to a high voltage, an electric field intensity E13 will also be formed on the edge of the field plate 84b close to the drain D. The field plate 84a is close to the drain D. An electric field strength E12 will also be formed at the edge of the gate protection layer 781 away from the source (s). An electric field strength E11 will also be formed at the edge of the gate protective layer 781 away from the source (s). The electric field strength E13 is greater than the electric field strength E12 and is greater than the electric field strength E11. At this time, the electric field strength E13 The dielectric layer (that is, the insulating layer between the field plate 84b and the active layer 82, the dielectric material layer 83a between the field plate 84b and the active layer 82 as shown in Figure 16) is very thick, and the electric field intensity E13 may It is not enough to break down the dielectric layer here, so the gate protection layer 781 and the

field plates

84a and 84b play a key role in increasing the breakdown voltage BV of the LDMOS.

For example, as shown in FIG. 16 , the field plate 84a is in contact with the field plate 84b. Therefore, when the field plate needs to be connected to a predetermined voltage, the field plate 84a can be connected to the field plate 84b and the gate, which is equivalent to giving the field The same voltage value is applied to plate 84a and field plate 84b. At this time, since the gate is usually connected to a dynamic voltage, the current voltages of the field plate 84a and the field plate 84b change with the gate voltage. At this time, the breakdown voltage of the field plate 84a and the field plate 84b to the semiconductor device 80 The increase in BV is relatively good, and at the same time, the specific on-resistance Ron,sp of the semiconductor device 80 is reduced. However, the connection between the field plate 84a and the field plate 84b and the gate is equivalent to increasing the gate equivalent of the semiconductor device 80 Capacitance, the increase in the gate equivalent capacitance of the semiconductor device 80 will affect the operating efficiency of the semiconductor device 80. In some semiconductor devices that have high requirements for breakdown voltage BV and low operating efficiency, the field plate can be connected to the gate. . The specific connection method is shown in Figure 18, wherein the electrode 861a and the electrode 861b shown in Figure 16 can be electrically connected to form the electrode 861ab, wherein the electrode 861ab is disposed between the field plate 84a and the dielectric material layer 83b, and the electrode 861ab passes through The via hole 831a is connected to the gate electrode 87, and the etching stop layer 863a and the etching stop layer 863b shown in Figure 16 are also merged into the etching stop layer 863ab (because it is an etching stop layer provided on the electrode 861ab), and The anti-reflective coating 864a and the anti-reflective coating 864b shown in Figure 16 are also combined into the anti-reflective coating 864ab (it should be noted that the etching stop layer and the anti-reflective coating can also be provided on different layers in the manner of Figure 16 The area in contact between the via hole and the electrode is not merged, and the embodiments of the present application are not limited to this); and/or, referring to FIG. 19, the electrode 862a and the electrode 862b shown in FIG. 16 can be electrically connected to form an electrode. 862ab, wherein the electrode 862ab is disposed on the side of the field plate 84b away from the dielectric material layer 83a, and the electrode 862ab is also connected to the electrode 861b through the via hole 832a.

Alternatively, the field plate 84a and the field plate 84b may be connected to the source, which is equivalent to applying the same voltage value to the field plate 84a and the field plate 84b. At this time, since the source is usually connected to zero voltage, the current field plate 84a and field plate 84b can best improve the breakdown voltage BV of the semiconductor device 80. However, this situation will also affect the breakdown voltage BV of the semiconductor device 80. Compared with the on-resistance Ron,sp, the field plate can be connected to the source in some semiconductor devices that have high requirements on the breakdown voltage BV and do not have high requirements on the specific on-resistance Ron,sp. The specific connection method is shown in Figure 20, in which the electrode 861a and the electrode 861c shown in Figure 16 can be electrically connected to form the electrode 861ac, wherein the electrode 861ac is disposed between the field plate 84a and the dielectric material layer 83b, and the electrode 861ac passes through The via hole 831b is connected to the doped region 824, the electrode 861ac is connected to the doped region 825 through the via hole 831c, and the electrode 861b and the electrode 861ac need to be insulated by an insulating material, wherein the etching stop layer 863a shown in Figure 16 The etching stop layer 863c can also be combined into the etching stop layer 863ac shown in Figure 20 (because it is an etching stop layer provided on the electrode 861ac). The anti-reflective coating 864a shown in Figure 16 and the anti-reflective coating 864c is also merged into the anti-reflective coating 864ac shown in Figure 20. Insulation is required between the etching stop layer 863b and the etching stop layer 863ac, and insulation is required between the anti-reflective coating 864ac and the anti-reflective coating 864b. Specifically, According to the position shown in FIG. 20 , the electrode 861b and the electrode 861ac may be arranged at a predetermined distance in the direction perpendicular to the paper surface, so that the insulation between the electrode 861b and the electrode 861ac is achieved through the dielectric material layer 83a (it should be noted that , the etching stop layer and the anti-reflective coating can also be arranged in the contact areas between different via holes and electrodes in the manner of Figure 16 without merging, and the embodiments of the present application do not limit this); and/or, refer to As shown in Figure 21, the electrode 862a and the electrode 862c shown in Figure 16 can be electrically connected to form an electrode 862ac, wherein the electrode 862ac is disposed on the side of the field plate 84b away from the dielectric material layer 83a, and the electrode 862ac is also connected to the field plate 862ac through the via hole 832b. The electrode 861c is connected, and the electrode 862b and the electrode 862ac need to be insulated by an insulating material. Specifically, according to the position shown in Figure 21, the electrode 862b and the electrode 862ac can be set at a predetermined distance in the direction perpendicular to the paper surface. So that the insulation between the electrode 862b and the electrode 862ac is achieved through the dielectric material layer 83b.

In another embodiment, referring to FIG. 22 , based on the semiconductor device 80 shown in FIG. 16 , an electrode 861 e may also be provided between the dielectric material layer 83 a and the dielectric material layer 83 b. The electrode 861 a and the electrode 861e is located on both sides of the field plate 84b, and the electrode 861e is in contact with the field plate 84b. The existence of the electrode 861e can not only determine the position of the field plate 84b, but also achieve the effect of increasing the breakdown voltage BV of the semiconductor device 80. Among them, the etching stop layer 863e and the anti-reflective coating 864e of the field plate 84b are also disposed between the electrode 861e and the dielectric material layer 83b.

In yet another embodiment, as shown in FIG. 23 , the field plate 84a and the field plate 84b are not in contact with each other. Therefore, when the field plate needs to be connected to a predetermined voltage, the field plate 84a and the field plate 84b can be connected to the gate together. The connection is equivalent to applying the same voltage value to the field plate 84a and the field plate 84b. Specifically, the electrode 861a and the electrode 861b can be electrically connected to form the electrode 861ab shown in Figure 18 to realize the connection between the field plate 84a and the gate electrode, and the electrode 862a and the electrode 862b can be electrically connected to form the electrode 862ab shown in Figure 19 to realize the field plate 84b and the gate electrode. connect.

Or the field plate 84 and the field plate 84b are connected to the source at the same time, which is equivalent to applying the same voltage value to the field plate 84a and the field plate 84b. Specifically, the electrode 861a and the electrode 861c can be electrically connected to form the electrode 861ac shown in Figure 20 to realize the connection between the field plate 84a and the source electrode, and the electrode 862a and the electrode 862c can be electrically connected to form the electrode 862ac shown in Figure 21 to realize the field plate 84b and the source electrode. connect.

Alternatively, since the field plate 84a and the field plate 84b are not in contact at this time, the field plate 84a can be connected to the gate and the field plate 84b can be connected to the source, which is equivalent to applying different voltages to the field plate 84a and the field plate 84b. Voltage value. The specific connection method is shown in Figure 24, in which the electrode 861a and the electrode 861b shown in Figure 23 can be electrically connected to form an electrode 861ab, wherein the electrode 861ab is disposed between the field plate 84a and the dielectric material layer 83b, and the electrode 861ab passes through The via hole 831a is connected to the gate electrode 87, and the etching stop layer 863a and the etching stop layer 863b shown in Figure 23 are also merged into the etching stop layer 863ab shown in Figure 24 (because the etching stop layer 863ab is provided on the electrode 861ab stop layer), and the anti-reflective coating 864a and the anti-reflective coating 864b shown in Figure 23 are also merged into the anti-reflective coating 864ab shown in Figure 24 (it should be noted that the etching stop layer and the anti-reflective coating are also They can be arranged in the areas where different via holes contact the electrodes in the manner of Figure 23 without merging, and the embodiments of the present application do not limit this). The electrode 862a and the electrode 862c shown in Figure 23 can be electrically connected to form the electrode 862ac shown in Figure 24, wherein the electrode 862ac is disposed on a side of the field plate 84b away from the dielectric material layer 83a, and the electrode 862ac is also connected to the electrode 862ac through the via hole 832b. The electrode 861c is connected, and the electrode 862b and the electrode 862ac need to be insulated by an insulating material. Specifically, according to the position shown in Figure 24, the electrode 862b and the electrode 862ac can be arranged at a predetermined distance in the direction perpendicular to the paper surface, So that the insulation between the electrode 862b and the electrode 862ac is achieved through the dielectric material layer 83b.

Alternatively, since the field plate 84a and the field plate 84b are not in contact at this time, the field plate 84a can be connected to the source and the field plate 84b can be connected to the gate, which is equivalent to applying different voltages to the field plate 84a and the field plate 84b. Voltage value. The specific connection method is shown in Figure 25. The electrode 861a and the electrode 861c shown in Figure 23 can be electrically connected to form the electrode 861ac, wherein the electrode 861ac is disposed between the field plate 84a and the dielectric material layer 83b, and the electrode 861ac passes through the via hole. 831b is connected to the doped region 824, the electrode 861ac is connected to the doped region 825 through the via hole 831c, and the electrode 861b and the electrode 861ac need to be insulated by an insulating material, wherein the etching stop layer 863a shown in FIG. The etching stop layer 863c can also be combined into the etching stop layer 863ac shown in Figure 25 (because it is an etching stop layer provided on the electrode 861ac), and the anti-reflective coating 864a and anti-reflective coating 864c shown in Figure 16 can also be combined. When combined into the anti-reflective coating 864ac shown in Figure 25, the etching stop layer 863b needs to be insulated from the etching stop layer 863ac, and the anti-reflective coating 864ac and the anti-reflective coating 864b need to be insulated. Specifically, as shown in Figure 20 The position shown can be that the electrode 861b and the electrode 861ac are arranged at a predetermined distance in the direction perpendicular to the paper surface, so that the insulation between the electrode 861b and the electrode 861ac is achieved through the dielectric material layer 83a (it should be noted that the etching stops The layer and the anti-reflective coating can also be arranged in the contact areas between different via holes and electrodes in the manner of Figure 23 without merging, and the embodiments of the present application do not limit this). Referring to Figure 25, the electrode 862a and the electrode 862b shown in Figure 23 can be electrically connected to form an electrode 862ab, wherein the electrode 862ab is disposed on a side of the field plate 84b away from the dielectric material layer 83a, and the electrode 862ab also passes through the via hole 832a. Connected to electrode 861b.

For example, referring to FIG. 26, in order to facilitate the connection between the field plate 84a and the gate or source, a via 832d can also be provided on the dielectric material layer 83b. The material of the via 832d specifically includes tungsten (W). An electrode 862e is provided on the surface of the dielectric material layer 83b away from the dielectric material layer 83a, and the electrode 861a is connected to the electrode 862e through a via hole 832d. Among them, the via hole 832d passes through the etching stop layer 863a and the anti-reflective coating 864a to contact the electrode 861a. Then, when the field plate 84a needs to be connected to the gate, the electrode 862e can be set to be connected to the electrode 862b. When the field plate 84a needs to be connected to the source, the electrode 862e can be set to be connected to the electrode 862c.

Exemplarily, referring to FIG. 27 , the doped region 822 also includes an isolation trench 91 , the opening of the isolation trench 91 faces the dielectric material layer 83 a , and the projection of the field plate 84 b on the active layer 82 is aligned with the isolation trench 91 Overlap, at this time, due to the existence of the isolation trench 91, the material filled in the isolation trench 91 is an oxide, that is, an insulating material, so the dielectric layer between the field plate 84b and the active layer 82 of the current semiconductor device 80 ( That is, the thickness of the insulating layer between the field plate 84b and the active layer 82) will increase, so that the breakdown voltage BV of the semiconductor device 80 increases again. However, the isolation trench 91 is disposed in the doped region 822, and the isolation trench 91 is made of insulating material. When the semiconductor device 80 is turned on, the presence of the isolation trench 91 will sacrifice a certain specific on-resistance Ron,sp of the semiconductor device, so as to This makes the specific on-resistance Ron,sp increase.

Exemplarily, referring to Figures 28 and 29, the doped region 822 also includes an isolation trench 92, the opening of the isolation trench 92 faces the dielectric material layer 83a, and the projection and isolation of the field plate 84a on the active layer 82 The trenches 92 overlap, and the projection of the gate 87 on the active layer 82 overlaps with the isolation trench 92 . Among them, the field plate 84a shown in Figure 28 is in contact with the sidewalls 89b of the gate 87, and the field plate 84a shown in Figure 29 is not in contact with the sidewalls 89b of the gate 87. In the embodiment of the present application, the field plate 84a and the gate Whether the side wall 89b of the pole 87 contacts is not limited. At this time, due to the existence of the isolation trench 92 and the material filled in the isolation trench 92 is an oxide, that is, an insulating material, then the dielectric layer (that is, the field plate) between the field plate 84 and the active layer 82 of the current semiconductor device 80 The thickness of the dielectric layer between the gate electrode 87 and the active layer 82 (that is, the insulating layer between the gate electrode 87 and the active layer 82) will increase. The thickness will increase so that the breakdown voltage BV of the semiconductor device 80 increases again. However, the isolation trench 92 is disposed in the doped region 822, and the isolation trench 92 is made of insulating material. When the semiconductor device 80 is turned on, the presence of the isolation trench 92 will sacrifice a certain specific on-resistance Ron,sp of the semiconductor device, so that This makes the specific on-resistance Ron,sp increase.

For example, referring to FIG. 30 , in order to maximize the breakdown voltage BV of the semiconductor device 80 , an isolation trench 91 may be provided in the doped region 822 , with the opening of the isolation trench 91 facing the dielectric material layer 83 a and the field plate. The projection of 84b on the active layer 82 overlaps with the isolation trench 91; an isolation trench 92 is also provided in the doped region 822, the opening of the isolation trench 92 faces the dielectric material layer 83a, and the field plate 84a is on the active layer 82 The projection of the gate electrode 87 on the active layer 82 overlaps with the isolation trench 92 . That is to say, when both the isolation trench 91 and the isolation trench 92 are provided in the semiconductor device 80 , the breakdown voltage BV of the semiconductor device 80 will be maximum, but at the same time, a certain specific on-resistance Ron of the semiconductor device 80 will be sacrificed. ,sp, so that the specific on-resistance Ron,sp increases.

Among them, isolation trench 91, isolation trench 92, field plate 84a is electrically connected to the gate, field plate 84a is electrically connected to the source, field plate 84b is electrically connected to the gate, field plate 84b is electrically connected to the source, and other different semiconductor devices. The arrangement modes of can be combined with each other, and the above-mentioned arrangement mode of the semiconductor device does not limit whether the field plate 84a and the field plate 84b in the semiconductor device 80 are in contact or not. Among them, combining one or more different arrangement modes requires The selection is made according to the application performance requirements of the specific semiconductor device 80. Those skilled in the art can make any combination based on the content disclosed in the embodiments of the present application. This application intends to include all the above combinations.

Referring to FIG. 31 , in the semiconductor device 80 , a buried oxide layer 90 and an epitaxial layer 91 are further provided between the substrate 81 and the active layer 82 . Among them, a buried oxide layer 90 is usually formed on a wafer substrate, and then an epitaxial layer 91 is formed. The doping types of the buried oxide layer 90 and the epitaxial layer 91 are different, and then an active layer is disposed on the epitaxial layer 91 Layer 82. The embodiments of the present application do not limit this.

Referring to FIG. 32 , when manufacturing the semiconductor device 80 , the semiconductor device 80 and other semiconductor devices are usually manufactured on the same wafer. Therefore, in the semiconductor device 80 , the substrate 81 is provided with isolation trenches 93 and The openings of the isolation trench 94, the isolation trench 93 and the isolation trench 94 face the dielectric material layer 83a; the active layer 82 is disposed between the isolation trench 92 and the isolation trench 94. Then, the semiconductor device 80 fabricated on the same wafer can be isolated from other semiconductor devices through the isolation trench 93 and the isolation trench 94, so that the active layers of different semiconductor devices will not be connected.

For example, as shown in Figure 33, a semiconductor process simulation and device simulation tool (technology computer aided design, TCAD) is used to simulate an LDMOS using only one field plate. Since there is only one field plate c1, the field plate A strong electric field intensity is formed between c1 and the active layer, and the dielectric layer between the field plate c1 and the active layer is thin. Refer to the voltage and current characteristic curve of the LDMOS with field plate c1 shown in Figure 34, Among them, the abscissa represents the voltage Vd in volts (V), and the ordinate represents the current Id in ampere (A). As shown in Figure 34, the breakdown voltage BV of LDMOS with only one field plate c1 is 31 Volt (V).

For example, as shown in FIG. 35 , TCAD is used to simulate an LDMOS using a field plate 84 a and a field plate 84 b , where an electric field intensity is formed between the field plate 84 a and the active layer, and an electric field intensity is formed between the field plate 84 a and the active layer. The dielectric layer between the field plate 84b and the active layer is thin, and another electric field intensity is formed between the field plate 84b and the active layer, and the dielectric layer between the field plate 84b and the active layer is thicker. Referring to the arrangement of the field plate 84a and the field plate 84a shown in FIG. 36 The voltage and current characteristic curve of the LDMOS of the field plate 84b, where the abscissa represents the voltage Vd in volts (V), the ordinate represents the current Id in amperes (A), where, as can be seen from Figure 36, the field setting The LDMOS breakdown voltage BV of plate 84a and field plate 84b is 42 volts (V).

In addition, refer to the characteristic curve of voltage and current shown in Figure 37, in which the abscissa represents the voltage Vd in volts (V), and the ordinate represents the current Id in amperes (A), where, for a field plate using The voltages applied to the gates of the LDMOS c1 (LDMOS shown in FIG. 33) and the LDMOS (LDMOS shown in FIG. 35) provided with

field plates

84a and 84b are both 5V. As can be seen from FIG. 37, in FIG. 33, only The on-current of the LDMOS with one field plate c1 is almost the same as that of the LDMOS with field plate 84a and field plate 84b in Figure 35, which means that the LDMOS with one field plate c1 in Figure 33 is different from the LDMOS with field plate 84a and field plate 84 in Figure 35. The specific on-resistance Ron,sp of the LDMOS of the plate 84b is close to the same. The breakdown voltage BV of the LDMOS with the field plate 84a and the field plate 84b in FIG. 35 is 42V as shown in FIG. 36. In FIG. 33, one field plate is used. The breakdown voltage BV of the LDMOS of c1 is 31V as shown in Figure 34. It can be seen that the breakdown voltage BV of the LDMOS provided with

field plates

84a and 84b is increased by 35% compared to the breakdown voltage BV of the LDMOS using one field plate c1. %above.

Illustratively, with reference to FIG. 38 , embodiments of the present application provide a method for manufacturing a semiconductor device, wherein the method includes:

S10. Make an active layer on the substrate.

For example, as shown in (a) of FIG. 39 , a generally obtained wafer only has a substrate 81 , and the active layer can be directly produced on the substrate 81 . Alternatively, as shown in (b) of FIG. 39 , in other cases, the buried oxide layer 90 is first formed on the wafer substrate, and then the epitaxial layer 91 is formed. The doping of the buried oxide layer 90 and the epitaxial layer 91 is The impurity types are different. For example, the doping type of the buried oxide layer 90 is N type, and the doping type of the epitaxial layer 91 is P type. Then, an active layer is disposed on the epitaxial layer 91 .

For clarity, subsequent manufacturing processes are represented by (a) in Figure 39 .

For example, in order to isolate semiconductor devices fabricated on the same wafer from other semiconductor devices, as shown in FIG. 40 , isolation trenches usually need to be formed on the substrate 81 . Specifically, photoresist can be coated on the substrate 81, and then photolithography is performed through a light shielding plate on top of the photoresist to form the isolation trench window p1 and the isolation trench window p2, and the isolation trench window p2 is formed through an etching process. The area of isolation trench 1 is formed below the isolation trench window p1, and the area of isolation trench 2 is formed below the isolation trench window p2. Then, high density plasma (high density plus, HDP) deposition (DEP) is used to form the area of isolation trench 2. The area of trench 1 is filled with oxide, and the area of isolation trench 2 is filled with oxide. Then, an isolation trench 93 is formed in the area of isolation trench 1, and an isolation trench 94 is formed in the area of isolation trench 2. Finally, chemical mechanical polishing (CMP, also called chemical mechanical polishing) is used to remove excess oxide in the opening direction of

isolation grooves

93 and 94 to form isolation grooves 93 and isolation grooves 94 as shown in FIG. 40 , the area between the isolation trench 93 and the isolation trench 94 is the active layer.

For example, when the isolation trench 91 and the isolation trench 92 shown in FIG. 30 need to be formed in the semiconductor device, the isolation trench 91 and the isolation trench 92 can also be made simultaneously when the isolation trench 93 and the isolation trench 94 are made. The isolation trench 91 And the manufacturing steps of the isolation trench 92 are similar to the manufacturing steps of the isolation trench 93 and the isolation trench 94 .

S11. Inject dopants into the active layer to form a first doped region and a second doped region.

Referring to Figure 41, a photoresist is coated on the active layer between the isolation trench 93 and the isolation trench 94, and then photolithography is performed through a light shield above the photoresist to form a window p3 in the doped area. The dopant of the first doping type is injected into the window p3 of the doped region through ion implantation (IMP) to form the doped region 822 (that is, the second doped region).

Referring to Figure 42, a photoresist is coated on the active layer between the isolation trench 93 and the isolation trench 94, and then photolithography is performed on the photoresist through a light shield to form a window p4 in the doped area. A dopant of the second doping type is injected into the window p4 of the doped region through ion implantation (IMP) to form a doped region 821 (that is, the first doped region).

That is to say, the doped region 821 and the doped region 822 are provided in the active layer, and the doped region 821 and the doped region 822 are in contact to form a contact surface.

For example, in diodes and DMOS tubes. It is enough to form the above two doped regions. In the triode, another ion implantation is required to form the doped region 823 shown in Figure 15, or the doped region 823 is formed at the same time when the doped region 822 is formed, where, The doping region 822 and the doping region 823 have the same doping type, and the doping region 822 and the doping region 821 have different doping types. The doping region 823 and the doping region 822 are located on both sides of the doping region 821 .

The first doping type of dopant may be an N-type dopant, so that the doping type of the doped region 822 is N-type, and the second type of dopant may be a P-type doping region, so that The doping type of the doped region 821 is P type. Alternatively, the first doping type of dopant may be a P-type dopant, such that the doping type of the doped region 822 is P type, and the second type of dopant may be an N-type doping region, such that The doping type of the doped region 821 is N type.

For example, the manufacturing process of semiconductor devices often involves forming many semiconductor devices on the same wafer at the same time. For example, based on the BCD process flow, after forming the doped region 821 and the doped region 822, it is also necessary to Well regions of other different semiconductor devices are formed through photolithography and ion implantation.

It should be noted that based on the BCD process flow, after injecting dopants into the active layer to form the first doped region and the second doped region, it is necessary to completely set the different doped regions and semiconductor material layers of different semiconductor devices. , and then make at least two layers of dielectric material on the active layer.

Taking the production of LDMOS as an example, the process is described after injecting dopants into the active layer to form a first doped region and a second doped region, and before forming at least two dielectric material layers on the active layer.

Referring to FIG. 43 , after forming the doped region 821 and the doped region 822 in the active layer, an insulating layer needs to be grown above the active layer. The insulating layer is also called a gate oxide layer. Specifically, the insulating layer 88 can be grown on the surface of the active layer through a furnace tube. When other semiconductor devices other than LDMOS need to be produced at the same time, the thickness of the insulating layer 88 grown at this time is the same on each semiconductor device. However, some semiconductor devices do not require a thick insulating layer, so in In areas where a thick insulating layer is not required, the insulating layer is thinned through photolithography and etching processes.

Referring to FIG. 44 , polysilicon (poly) is deposited (DEP) through a furnace tube to form a gate 87 on top of the insulating layer 88 . Usually, the polysilicon formed covers the entire active layer like the insulating layer 88 shown in FIG. 43 . layer, then it is necessary to form a gate electrode 87 and an insulating layer 88 of a predetermined shape as shown in Figure 44 through photolithography and etching processes. The gate electrode 87 and the active layer are insulated by the insulating layer 88. The gate electrode 87 The contact surface between the doped region 821 and the doped region 822 is covered.

Referring to FIG. 45 , spacer structures are formed on both sides of the gate 87 . For example, spacers 89 a and 89 b are formed on the active layer by depositing spacer materials. The gate 87 is located between the spacers 89 a and the side walls. Between the wall 89b, the spacer 89a is in contact with the gate electrode 87 and the doped region 821, and the spacer 89b is in contact with the gate electrode 87 and the doped region 822.

Referring to FIG. 46 , a doped region 825 and a doped region 826 are formed. For example, photoresist is coated on the active layer, and then photolithography is performed on the photoresist through a light shield to form the doped region. The window p5 of the doped region and the window p6 of the doped region are injected with a dopant of the first doping type into the window p5 of the doped region and the window p6 of the doped region through ion implantation (IMP), forming a doped Doping region 825 and doping region 825, wherein the doping type of doping region 825 and doping region 826 is the same as the doping type of doping region 822, and the doping type of doping region 825 and doping region 826 is the same as that of doping region 822. The doping type of the impurity region 821 is opposite.

Referring to Figure 47, a doped region 824 is formed. For example, photoresist is coated on the active layer, and then photolithography is performed through a light shielding plate above the photoresist to form a window p7 in the doped region. A dopant of the second doping type is injected into the window p7 of the doping region through ion implantation (IMP) to form a doping region 824, where the doping type of the doping region 824 is the same as that of the doping region 821. The doping type is the same, and the doping type of the doped region 824 is opposite to that of the doped region 822 .

Referring to Figure 48, an insulating layer 851 and an etching stop layer 852 are formed. For example, the insulating layer 851 and the etching stop layer 852 can be formed above the doped region 822. The insulating layer 851 can be in contact with the gate electrode 87, It may also be in contact with the sidewalls 89b of the gate 87, which is not limited in the embodiments of the present application. More specifically, this step can be implemented using the SAB process. The SAB process has been widely used in the manufacturing process of semiconductor devices, and the embodiments of the present application will not be described in detail here.

At this point, the doped region of LDMOS and the basic semiconductor material layer have been produced. Of course, based on the BCD process, the above steps may also include other ion implantation and semiconductor material layer setting processes. The embodiments of the present application are not limited to this. .

S12. Make at least two dielectric material layers on the active layer, and make at least two field plates in the dielectric material layer.

Referring to Figure 49, a dielectric material 83a is produced. For example, an oxide is deposited by chemical vapor deposition (CVD) to form a dielectric material layer 83a. Specifically, the dielectric material layer 83a covers the active layer, gate electrode 87, isolation trench 93 and isolation trench 94, use chemical mechanical polishing (CMP, also called chemical mechanical polishing) to smooth the surface of the side of the dielectric material layer 83a away from the active layer, and then , apply photoresist on the dielectric material layer 83a, and then perform photolithography through a light shielding plate on top of the photoresist to form the opening p8 of the via hole 831b, the opening p9 of the via hole 831c, and the opening of the via hole 831a. The window p10, the window p11 of the field plate 84a, and the window p12 of the via 831d are formed through an etching process to form the area of the via 831b below the window p8 of the via 831b, and the area of the via 831b is formed under the window p9 of the via 831c. The via hole 831c is formed below, the via hole 831a is formed below the window p10 of the via hole 831a, the field plate 84a is formed below the window p11 of the field plate 84a, and the via hole 831d is formed below the window p12. Area of hole 831d. Among them, the area of the etching field plate 84a is etched just until the insulating layer 851 stops etching, and a part of the etching stop layer 852 is etched away. The etching of the via hole is directly etched to the silicon (which can be the gate 87 of polysilicon, or doped regions in the active layer).

It should be noted that when etching the area of the field plate 84a as described above, two-step etching is often performed, namely main etching and over-etching. During the main etching, the area of the field plate 84a is etched within the etching process. In the area of the stop layer 852, when over-etching, the etching stop layer 852 may be etched through so that the area of the field plate 84a is in contact with the insulating layer 851, or the etching stop layer 852 may not be etched through so that the field plate 84a is in contact with the insulating layer 851. A portion of the etching stop layer 852 remains between the area 84a and the insulating layer 851.

Then, high density plasma (HDP) is used to deposit (DEP) the area of the via hole 831b, the area of the via hole 831c, the area of the via hole 831a, the area of the field plate 84a and the area of the via hole 831d. The area is filled with conductive material, specifically, tungsten (W) may be deposited, thereby forming via holes 831b, via holes 831c, via holes 831a, field plates 84a, and via holes 831d. The surfaces of the via hole 831b, the via hole 831c, the via hole 831a, the field plate 84a, and the side of the via hole 831d away from the active layer are polished by chemical mechanical polishing (CMP, also called chemical mechanical polishing).

Next, as shown in FIG. 50 , a layer of electrode 861 is deposited on the side of the dielectric material layer 83a away from the active layer through a metal sputtering process. The electrode 861 serves as the first electrode layer of the semiconductor device.

Then, as shown in FIG. 51 , an etching stop layer 863 and an anti-reflective coating 864 are deposited on the electrode 861 . For example, nitride, specifically silicon nitride (SiN), can be deposited on the side of the electrode 861 away from the dielectric material layer 83a to form the etching stop layer 863. Then, an oxynitride, specifically silicon oxynitride (SiON), can be deposited on the side of the etching stop layer 863 away from the dielectric material layer 83a to form an anti-reflective coating 864.

It should be noted that the functions of photoresist and anti-reflective coating are the same. They both block a part of the semiconductor material layer and expose another part of the semiconductor material layer, thereby realizing subsequent manufacturing steps in the exposed part of the semiconductor material layer. . In some embodiments, the photoresist and the anti-reflective coating use the same material. In other embodiments, the photoresist and the anti-reflective coating use different materials. This is not limited in the embodiments of the present application.

Then, as shown in Figure 52, photolithography is performed on the anti-reflective coating 864 to form a window, and the anti-reflective coating 864, etching stop layer 863 and electrode 861 under the window are etched away to form an electrode 861c. The etch stop layer 863c on the etch stop layer 863c and the anti-reflective coating 864c on the etch stop layer 863c; the electrode 861b, the etch stop layer 863b on the electrode 861b and the anti-reflective coating 864b on the etch stop layer 863b; the electrode 861a, The etch stop layer 863a on the electrode 861a and the anti-reflective coating 864a on the etch stop layer 863a; the electrode 861d, the etch stop layer 863d on the electrode 861d and the anti-reflective coating 864d on the etch stop layer 863d. Among them, the electrode 861c is connected to the doped region 824 through the via hole 831b, the electrode 861c is connected to the doped region 825 through the via hole 831c, the electrode 861b is connected to the gate electrode 87 through the via hole 831a, the electrode 861a is in contact with the field plate 84a, and the electrode 861d It is connected to the doped region 826 through the via hole 831d.

Referring to Figure 53, a dielectric material 83b is produced. For example, an oxide is deposited by chemical vapor deposition (CVD) to form a dielectric material layer 83b. Specifically, the dielectric material layer 83b covers anti-reflection The coating and dielectric material layer 83a are polished by chemical mechanical polishing (CMP, also called chemical mechanical polishing) on the surface of the side of the dielectric material layer 83b away from the dielectric material layer 83a. An anti-reflective coating 865 is provided on the side of the electrical material layer 83b away from the dielectric material layer 83a.

Referring to FIG. 54 , photolithography is performed on the anti-reflective coating 865 to form the windows p13 , p14 , p15 , p16 and p17 .

Referring to FIG. 55 , the dielectric material layer 84b (oxide) and the anti-reflective coating under the windows p13, p14, p15, p16 and p17 are removed through an etching process. 864 (oxynitride) (that is, anti-reflective coating 864c, anti-reflective coating 864b, anti-reflective coating 864a, anti-reflective coating 864d), that is, etching to the etching stop layer 863 (that is, etching The etching stop layer 863c, the etching stop layer 863b, the etching stop layer 863a, and the etching stop layer 863d) stop this etching. It should be noted that this etching step may be called main etching, and the etching stop layer 863 is the etching stop layer for the main etching.

Referring to Figure 56, adjust the gas used for etching to etch the oxide. Referring to Figure 56, on the basis of the etching shown in Figure 55, etching is performed again, and only the oxide is etched. Since there is only oxide below the window p16, therefore, at this time, the oxide below the window p16 The oxide will be etched down to the dielectric material layer 83a, but the etching time needs to be controlled, it cannot be etched to the doped region 822, and it needs to maintain a predetermined distance from the doped region 822. In this etching, the etching stop layer 863 (that is, the etching stop layer 863c, the etching stop layer 863b, the etching stop layer 863a, the etching stop layer 863a, the etching stop layer 863 under the window p13, the window p14, the window p15, and the window p17 The thickness of the etch stop layer 863d) has little change or is etched away little.

Referring to Figure 57, the gas used for etching is adjusted to etch the nitride. Referring to Figure 57, etching is performed on the basis of the etching shown in Figure 56, and only the nitride is etched. Due to the etching under the window p13, the window p14, the window p15 and the window p17 The etching stop layer 863 is a nitride. Therefore, at this time, the etching stop layer 863 (that is, the etching stop layer 863c, the etching stop layer 863b, the etching stop layer 863b, the etching stop layer 863 under the window p13, the window p14, the window p15, and the window p17 The etching stop layer 863a, the etching stop layer 863d) will be etched downward to the electrode 861 (that is, the electrode 861c, the electrode 861b, the electrode 861a, the electrode 861d), and the dielectric material layer 83a (oxide) under the window p16 There is little change in thickness or little is etched away.

Referring to Figure 58, adjust the gas used for etching, and then etching based on the etching shown in Figure 57. In this etching, open the window p13, the window p14, and the window p15. , the electrode 861 (that is, the electrode 861c, the electrode 861b, the electrode 861a, and the electrode 861d) under the window p16 and the window p17 is etched so that the bottom of the window p16 is etched until it is in complete contact with the electrode 861a. At this time, and the electrode 861 is opened. The electrode 861c below the window p13, the electrode 861b below the window p14, the electrode 861a below the window p15, and the electrode 861d below the window p17 will also be partially etched away. It should be noted that this step of etching can be called For over etching,.

Ideally, the electrode 861 is a sandwich structure (Ti-TiN-Al-TiN-Ti) formed by titanium nitride, titanium, and aluminum. Therefore, the etching shown in Figure 58 above ensures that titanium nitride, titanium, and aluminum are formed. The sandwich structure (Ti-TiN-Al-TiN-Ti) does not etch aluminum, and it is best to only etch away part of titanium nitride or titanium.

Subsequently, as shown in Figure 59, within the range etched in Figure 58, conductive material is filled using high density plasma (HDP) deposition (DEP). Specifically, tungsten (W) can be deposited , and then form the via hole 832b, the via hole 832a, the via hole 832c, the field plate 84b and the via hole 832d, and polish the via hole 832b, the via hole 832a, and the via hole 832d through chemical mechanical polishing (CMP, also called chemical mechanical polishing). The surfaces of the hole 832d, the field plate 84b and the via hole 832c on the side away from the dielectric material layer 83a are smoothed.

Referring to Figure 60, based on Figure 59, a layer of electrode 862 is deposited on the etched area of the dielectric material layer 83b again through a metal sputtering process (metal sputtering). This electrode 862 serves as the second electrode layer of the semiconductor device. . Referring to Figure 60, the electrode 861c is finally connected to the electrode 862c through the via hole 832b, the electrode 861b is connected to the electrode 862b through the via hole 832a, the electrode 862e is connected to the electrode 862a through the via hole 832d, the field plate 84b is in contact with the electrode 832a, and the electrode 861c is finally formed. 861d is connected to the electrode 862d through the via hole 832c.

For example, in the semiconductor device shown in FIG. 60, when the field plate 84b is connected to the field plate 84a, the electrode 862e and the via hole 832b may not be provided, and the embodiment of the present application does not limit this.

Illustratively, there is no strict sequence of the above-mentioned manufacturing steps. As long as the semiconductor device shown in FIG. 12 to FIG. 32 can be produced, the above-mentioned manufacturing steps can be adjusted arbitrarily, and certain steps can be added or deleted. For example, the gate electrode may be formed first and then the doped region 821 may be formed. The embodiments of the present application do not limit the order of the steps. Moreover, the content produced in the above steps can be more or less, and the embodiments of the present application are not limited to this. For example, more via holes can be produced at one time.

Among them, according to the manufacturing method of the semiconductor device shown in Figure 38, since in the semiconductor device, the field plate penetrates the dielectric material layer, and the dielectric material layer needs to be provided with via holes to connect the metal electrodes on both sides of the dielectric material layer or Metal electrodes and semiconductor material layers, then when the field plate penetrates the dielectric material, the field plate in the semiconductor device can be made while making the via hole, so that the field plate in the manufactured semiconductor device does not require additional photolithography and etching step, thereby saving the cost of providing field plates in semiconductor devices.

For example, after the electrodes 862 (that is, the

electrodes

862a, 862b, 862c, 862d, and 862e) are produced, the above-mentioned anti-reflective coating 865 can be washed away. This is not done in the embodiment of the present application. limited. The above-mentioned photoresist and/or anti-reflective coating 864 can also be cleaned after use, which is not limited in the embodiments of the present application.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are intended to be merely illustrative of the application as defined by the appended claims and are to be construed to cover any and all modifications, variations, combinations or equivalents within the scope of the application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A semiconductor device, characterized by including:

substrate;

An active layer provided on the substrate; the active layer includes a first doped region and a second doped region in contact with the first doped region, the first doped region and the The doping type of the second doped region is different;

At least two layers of dielectric material disposed on the active layer;

and at least two field plates disposed in the dielectric material layer, the field plates penetrating one or more layers of the dielectric material layer, and the projection of the field plate on the active layer is consistent with the The second doped regions overlap, and one end of the field plate close to the active layer is insulated from the active layer.
The semiconductor device according to claim 1, characterized in that

The at least two dielectric material layers include a first dielectric material layer and a second dielectric material layer;

The first dielectric material layer is disposed on a side of the active layer away from the substrate;

The second dielectric material layer is disposed on a side of the first dielectric material layer away from the substrate;

The at least two field plates include a first field plate and a second field plate;

The first field plate penetrates the first dielectric material layer, and a first electrode is provided between the first field plate and the second dielectric material layer;

The second field plate penetrates the first dielectric material layer and the second dielectric material layer, and a second electrode is disposed on a surface of the second field plate away from the active layer.
The semiconductor device according to claim 2, characterized in that a third electrode is further disposed between the first dielectric material layer and the second dielectric material layer, and the first electrode and the third Electrodes are located on both sides of the second field plate.
The semiconductor device according to claim 2 or 3, wherein the first field plate is in contact or not in contact with the second field plate.
The semiconductor device according to any one of claims 2 to 4, further comprising: a gate electrode disposed on the active layer, the gate electrode being insulated from the active layer;

The gate electrode covers the contact surface between the first doped region and the second doped region;

A first via hole is provided on the first dielectric material layer, a fourth electrode is provided between the first dielectric material layer and the second dielectric material layer, and the fourth electrode passes through the first dielectric material layer. A via hole is connected to the gate.
The semiconductor device according to claim 5, characterized in that

A second via hole is provided on the second dielectric material layer, a fifth electrode is provided on a surface of the second dielectric material layer away from the first dielectric material layer, and the fourth electrode passes through the The second via hole is connected to the fifth electrode.
The semiconductor device according to claim 5, characterized in that

The fourth electrode is electrically connected to the first electrode.
The semiconductor device according to claim 6, characterized in that

The fifth electrode is electrically connected to the second electrode.
The semiconductor device according to any one of claims 2 to 8, characterized in that:

The first doped region also includes a third doped region and a fourth doped region in contact with the third doped region. The doping of the third doped region and the first doped region The fourth doped region is of the same type as the first doped region. The fourth doped region is close to the second doped region and is not in contact with the second doped region. ;

A third via hole and a fourth via hole are also provided on the first dielectric material layer, and a sixth electrode is provided between the first dielectric material layer and the second dielectric material layer. The sixth electrode is connected to the third doped region through the third via hole, and the sixth electrode is connected to the fourth doped region through the fourth via hole;

A fifth via hole is also provided on the second dielectric material layer. A seventh electrode is provided on a surface of the second dielectric material layer away from the first dielectric material layer. The sixth electrode passes through the first dielectric material layer. The fifth via hole is connected to the seventh electrode.
The semiconductor device according to claim 9, characterized in that

The sixth electrode is electrically connected to the first electrode, and/or the seventh electrode is electrically connected to the second electrode.
The semiconductor device according to any one of claims 2-10, characterized in that:

The second doped region also includes a fifth doped region, the fifth doped region has the same doping type as the second doped region, and the fifth doped region is not the same as the third doped region. a doped area contact;

A sixth via hole is provided on the first dielectric material layer, and an eighth electrode is provided between the first dielectric material layer and the second dielectric material layer. The eighth electrode passes through the The sixth via hole is connected to the fifth doped region;

A seventh via hole is also provided on the second dielectric material layer. A ninth electrode is provided on a surface of the second dielectric material layer away from the first dielectric material layer. The eighth electrode passes through the first dielectric material layer. The seventh via hole is connected to the ninth electrode.
The semiconductor device according to any one of claims 2-11, characterized in that:

The second doped region also includes a first isolation trench, the opening of the first isolation trench faces the first dielectric material layer, and the projection of the second field plate on the active layer is consistent with the The first isolation grooves overlap.
The semiconductor device according to any one of claims 5-12, characterized in that:

The second doped region also includes a second isolation trench, the opening of the second isolation trench faces the first dielectric material layer, and the projection of the first field plate on the active layer is consistent with the The second isolation trench overlaps, and the projection of the gate on the active layer overlaps with the second isolation trench.
The semiconductor device according to any one of claims 2 to 13, wherein the first field plate is insulated from the gate electrode.
The semiconductor device according to any one of claims 2-14, characterized in that:

A first etching stop layer and an anti-reflective coating are also disposed between the first electrode and the second dielectric material layer.
The semiconductor device according to any one of claims 2-15, characterized in that:

A second etching stop layer and an insulating layer are also provided on a side of the first field plate close to the active layer.
The semiconductor device according to claim 5, wherein a first spacer and a second spacer are further provided on the active layer, and the gate is located between the first spacer and the second sidewall. Between the walls, the first spacer is in contact with the gate electrode and the first doped region, and the second spacer is in contact with the gate electrode and the second doped region.
The semiconductor device according to any one of claims 2-17, characterized in that:

The material of the first electrode includes one or more of the following: titanium nitride, titanium, and aluminum.
The semiconductor device according to any one of claims 1-18, characterized in that:

The doping type of the first doped region is P type, and the doping type of the second doped region is N type;

Alternatively, the doping type of the first doped region is N-type, and the doping type of the second doped region is P-type.
The semiconductor device according to any one of claims 1-19, characterized in that:

The field plate material includes tungsten.
The semiconductor device according to any one of claims 1-20, characterized in that:

The material of the dielectric material layer includes oxide.
The semiconductor device according to any one of claims 1-21, characterized in that:

A third isolation trench and a fourth isolation trench are provided in the substrate, with openings of the third isolation trench and the fourth isolation trench facing the first dielectric material layer; the active layer is disposed on the between the first isolation groove and the second isolation groove.
The semiconductor device according to any one of claims 1-22, characterized in that:

A buried oxide layer and an epitaxial layer are also provided on the substrate and between the active layer.
A semiconductor device, characterized by including:

substrate;

An active layer provided on the substrate; the active layer includes a first doped region and a second doped region in contact with the first doped region, the first doped region and the The doping type of the second doped region is different;

At least two layers of dielectric material disposed on the active layer;

and a third field plate disposed in the at least two dielectric material layers, the third field plate penetrates the at least two dielectric material layers, and the third field plate is on the active layer The projection overlaps with the second doped region, and one end of the third field plate close to the active layer is insulated from the active layer.
An integrated circuit, characterized in that it includes a packaging structure and the semiconductor device according to any one of claims 1 to 24, and the semiconductor device is packaged inside the packaging structure.
An electronic device, characterized by comprising a printed circuit board and the integrated circuit according to claim 25, the integrated circuit being connected to the printed circuit board.
A method for manufacturing a semiconductor device, characterized by including:

Producing an active layer on the substrate;

Dopants are injected into the active layer to form a first doped region and a second doped region. The first doped region is in contact with the second doped region. The first doped region is in contact with the second doped region. The doping type of the second doped region is different;

producing at least two layers of dielectric material on the active layer;

At least two field plates are made in the dielectric material layer, the field plates penetrate one or more layers of the dielectric material layer, and the projection of the field plate on the active layer is consistent with the third The two doped regions overlap, and one end of the field plate close to the active layer is insulated from the active layer.