WO2023010583A1

WO2023010583A1 - Integrated circuit, power amplification circuit and electronic device

Info

Publication number: WO2023010583A1
Application number: PCT/CN2021/111359
Authority: WO
Inventors: 宁开明
Original assignee: 华为技术有限公司
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2023-02-09
Also published as: CN117751434A

Abstract

Th embodiments of the present application relate to the technical field of semiconductors. Provided are an integrated circuit, a power amplification circuit and an electronic device, which can reduce the resistivity in a path between an active region and an electrode, thereby improving the efficiency of a device. The integrated circuit comprises: a substrate, which is covered with a transistor, wherein the transistor includes a channel layer and a barrier layer which are arranged on the substrate in a stacked manner, and a source electrode, a drain electrode and a gate electrode which are arranged on the barrier layer; and the transistor further comprises a first heavily doped region and/or a second heavily doped region, the first heavily doped region penetrating the barrier layer and the channel layer and the first heavily doped region being in contact with the source electrode, and not being in contact with the substrate, the second heavily doped region penetrating the barrier layer and the channel layer and the second heavily doped region being in contact with the drain electrode, and not being in contact with the substrate, and dopants for providing carriers being arranged in the first heavily doped region and the second heavily doped region.

Description

Integrated circuits, power amplifier circuits and electronic equipment

technical field

The present application relates to the technical field of semiconductors, in particular to an integrated circuit, a power amplifier circuit and electronic equipment.

Background technique

At present, in the processing of radio frequency signals, devices such as high electron mobility transistors (high electron mobility transistors, HEMTs) are usually used as power amplification circuits in power amplifiers of electronic equipment. For example, the power of the radio frequency signal generated in the radio frequency modulation circuit of the electronic device is very small, and it needs to go through a series of amplifications to obtain enough radio frequency power before it can be fed to the antenna for radiation. In order to obtain sufficient radio frequency power, a radio frequency power amplifier must be used to amplify the power of the radio frequency signal. RF power amplifiers are widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasures and other systems, and are key components of modern wireless communication.

Generally, the above-mentioned transistor includes a channel layer and electrodes fabricated on the substrate, for example, the electrodes include a source, a drain, and a gate, wherein the gate faces the active region of the channel layer. In addition, in order to realize the device characteristics of the transistor, other semiconductor material layers are usually arranged between the electrode and the channel layer. ), barrier layers, one or more buffer layers and other semiconductor material layers.

When the above-mentioned transistor is working, when the two-dimensional electron gas generated in the active region of the channel layer is transported to the corresponding electrode (such as the source or drain) through these semiconductor material layers, the resistance on the path of current transmission is inconsistent, when When the resistivity of certain semiconductor material layers or the above-mentioned ohmic contact resistance is high, the performance of the device will be seriously affected, resulting in low efficiency of the device.

Contents of the invention

The embodiments of the present application provide an integrated circuit, a power amplifying circuit and an electronic device, which can reduce the resistivity on the path from the active region of the channel layer to the electrodes, thereby improving the efficiency of the device.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

In a first aspect, an integrated circuit is provided. The integrated circuit includes a substrate, wherein the substrate is covered with a transistor; the transistor includes a channel layer stacked on the substrate, a barrier layer, and a source, a drain, and a gate arranged on the barrier layer; the transistor It also includes a first heavily doped region and/or a second heavily doped region; wherein, the first heavily doped region penetrates through the barrier layer and the channel layer, and the first heavily doped region is in contact with the source; the second heavily doped region The doped region runs through the barrier layer and the channel layer, and the second heavily doped region is in contact with the drain; dopants providing carriers are arranged in the first heavily doped region and the second heavily doped region. It should be noted that, considering the material of the substrate, the first heavily doped region may or may not be in contact with the substrate, and the second heavily doped region may or may not be in contact with the substrate. , in order to prevent the substrate from directly short-circuiting the first heavily doped region and the second heavily doped region, the first heavily doped region may not be in contact with the substrate, and the second heavily doped region may not be in contact with the substrate. Of course, when the substrate is made of an insulating material, the first heavily doped region may or may not be in contact with the substrate, and the second heavily doped region may or may not be in contact with the substrate. Since the first heavily doped region and the second heavily doped region are provided with dopants providing carriers, and the first heavily doped region is in contact with the source and the second heavily doped region is in contact with the drain, then When a voltage is applied to the gate to generate a two-dimensional electron gas in the active region of the channel layer, the two-dimensional electron gas can be transported between the active region of the channel layer and the source through the first heavily doped region, And the two-dimensional electron gas can be transported between the active region and the drain of the channel layer through the second heavily doped region, because the dopant can provide carriers, thus reducing the current transmission of the two-dimensional electron gas in the above-mentioned The resistance on the path, that is, the carriers provided by the dopant can reduce the resistivity on the path from the active region in the channel layer to the source and drain, thereby improving the efficiency of the device.

In a possible implementation manner, the transistor at least includes a high electron mobility transistor HEMT, a metal-semiconductor field effect transistor (metal-semiconductor field effect transistor, MESFET); the transistor is N-type, and the dopant provides an N-type carriers; alternatively, the transistor is P-type, and the dopant provides P-type carriers. If the transistor is N-type, then the carriers in the active region of the channel layer are N-type (ie electronic) carriers, or if the transistor is P-type, then the carriers in the active region of the channel layer are P-type (that is, hole-type) carriers, so in order to avoid the recombination of carriers in the active region of the channel layer and the carriers provided by the dopant (electron-type carriers and hole-type carriers Recombination) affects the concentration of the two-dimensional electron gas, so in the embodiments of the present application, the type of carriers provided by the dopant is the same as the type of carriers in the active region of the channel layer, that is, the transistor is N-type, The dopant provides N-type carriers; or, the transistor is P-type, and the dopant provides P-type carriers.

In a possible implementation manner, there is no limitation on the type of dopant in the embodiment of the present application, for example, the above dopant may include one or more impurity elements.

In a possible implementation manner, the dopant that provides N-type carriers includes at least one or more impurity elements in silicon Si, germanium Ge, or tin Sn; the dopant that provides P-type carriers The material includes at least one or more impurity elements in beryllium Be or carbon C.

In a possible implementation manner, the dopant in the first heavily doped region and the second heavily doped region can only provide carriers that can truly achieve the requirement of reducing the resistivity when the dopant reaches a certain concentration. The concentration is greater than or equal to the predetermined concentration.

In a possible implementation manner, the predetermined concentration of the dopant in the first heavily doped region and the second heavily doped region is 1e18 atoms/cubic centimeter.

In a possible implementation manner, a first risk layer is arranged between the source and the barrier layer, and a second risk layer is arranged between the drain and the barrier layer; the first heavily doped region runs through the first risk layer ; The second heavily doped region runs through the second risky layer. In this possible implementation, the existence of the first risk layer is to form a good ohmic contact between the barrier layer and the source, and the existence of the second risk layer is to form a good contact between the barrier layer and the drain. ohmic contact. Of course, since the first sinking layer is also located on the path between the active region and the source of the channel layer, and the second sinking layer is also positioned on the path between the active region and the drain of the channel layer, so by The first heavily doped region runs through the first risk layer, and the second heavily doped region runs through the second risk layer, which can also reduce the resistivity of the path between the active region in the channel layer and the source electrode and the drain electrode.

In a possible implementation manner, at least one buffer layer is further provided between the channel layer and the barrier layer; the first heavily doped region penetrates at least one buffer layer; the second heavily doped region penetrates at least one layer The buffer layer. In this kind of possible implementation, the existence of at least one buffer layer is to further improve the performance of the device (such as increasing the concentration of two-dimensional electron gas, reducing the leakage current or improving the response speed of the device, etc.), and at the same time due to the at least one buffer layer It is also located on the channel between the active region of the channel layer and the source electrode and the drain electrode, so the first heavily doped region penetrates at least one buffer layer, and the second heavily doped region penetrates at least one buffer layer, also The resistivity on the path from the active region to the source and drain in the channel layer can be reduced.

In a possible implementation manner, at least one buffer layer is further provided with a doped layer between any two adjacent buffer layers; the first heavily doped region penetrates the doped layer; the second heavily doped region penetrates doped layer. In this possible implementation mode, the existence of the doped layer between any adjacent two buffer layers in at least one buffer layer is to further improve the performance of the device (such as increasing the concentration of two-dimensional electron gas, reducing the leakage current Or improve the response speed of the device, etc.), and because the doped layer is also located on the path between the active region of the channel layer and the source and drain, the doped layer is penetrated through the first heavily doped region, and the second heavily doped region The doped region runs through the doped layer and can also reduce the resistivity on the path from the active region in the channel layer to the source and drain.

In a possible implementation manner, the embodiment of the present application further provides a specific material used for the substrate. For example, the substrate material of a transistor in an integrated circuit may include any of the following: gallium arsenide GaAs, indium phosphide InP, and gallium nitride GaN.

In a second aspect, a method for manufacturing an integrated circuit is provided. It specifically includes the following steps: the first step: sequentially fabricating channel layers and barrier layers stacked on the substrate; the second step: fabricating a photoresist covering the barrier layer; the third step: photoresisting the photoresist At the same time, a source opening is formed in the source area, and a drain opening is formed in the drain area; then: the dopant that provides carriers is injected through the source opening and the drain opening to form the first layer A doped region and a second heavily doped region; wherein, the first heavily doped region runs through the barrier layer and the channel layer, and the second heavily doped region runs through the barrier layer and the channel layer; finally: on the barrier layer A source, a drain and a gate are fabricated, wherein a first heavily doped region is in contact with the source and a second heavily doped region is in contact with the drain.

In a possible implementation manner, before the second step above, it also includes: making a first risk layer and a second risk layer on the barrier layer; then the second step specifically includes: making a layer covering the first risk layer and the second The photoresist of the second risk layer; the third step specifically includes: performing photolithography on the photoresist, forming a source opening in the region of the source on the first risk layer, and forming a drain in the region of the drain on the second risk layer Extremely open window; wherein, the first heavily doped region runs through the first risk layer; the second heavily doped region runs through the second risk layer.

In a possible implementation manner, the first step specifically includes, sequentially manufacturing a stacked channel layer, at least one buffer layer, and a barrier layer on the substrate; wherein, the first heavily doped region runs through at least one layer buffer layer; the second heavily doped region runs through at least one buffer layer.

In a possible implementation manner, a doped layer is formed between any two adjacent buffer layers in at least one buffer layer; the first heavily doped region runs through the doped layer; the second heavily doped region through the doped layer.

In a possible implementation manner, after the first heavily doped region and the second heavily doped region are formed by injecting dopants that provide carriers by opening the source window and the drain window, it further includes: performing annealing The process anneals the dopant.

In a possible implementation manner, after the first heavily doped region and the second heavily doped region are formed by injecting the dopant that provides carriers through the source opening and the drain opening, further includes: through the source The dopant is annealed in the annealing process of the electrode, the drain and the gate.

In a possible implementation manner, the transistor includes at least HEMT and MESFET; the transistor is N-type, and the dopant provides N-type carriers; or, the transistor is P-type, and the dopant provides P-type carriers.

In one possible implementation, the dopant includes one or more impurity elements.

In a possible implementation manner, the concentration of dopants in the first heavily doped region and the second heavily doped region is greater than or equal to a predetermined concentration.

Wherein, the technical effects brought about by any possible implementation manner in the second aspect may refer to the technical effects brought about by the different implementation manners of the above-mentioned first aspect, which will not be repeated here.

In a third aspect, an integrated circuit is provided. The integrated circuit includes a substrate, wherein the substrate is covered with a transistor; the transistor includes a plurality of semiconductor material layers stacked on the substrate, and the plurality of semiconductor material layers include: a sub-collector layer, a collector layer, a base layer , emitter layer, emitter capping layer, and on the sub-collector layer are also provided with a first collector and a second collector located on both sides of the collector layer, and on the base layer are also provided with a collector located on both sides of the emitter layer The first base and the second base on the side, and an emitter is also arranged on the emitter risk layer; the transistor also includes a first heavily doped region; wherein, the first heavily doped region runs through the emitter risk layer and In the emitter layer, the first heavily doped region is in contact with the emitter, and the first heavily doped region is not in contact with the base layer; and dopants providing carriers are arranged in the first heavily doped region. Wherein, since the dopant providing carriers is provided in the first heavily doped region, the carriers provided by the dopant can reduce the resistivity of the ohmic contact resistance between the emitter and the emitter capping layer, because the first A heavily doped region extending through the emitter layer also reduces the resistivity of the emitter layer, thereby reducing the resistivity on the path from the emitter to the active region of the base layer, thereby improving device efficiency.

In a possible implementation manner, the transistor in the above integrated circuit further includes one or more of the following heavily doped regions: a second heavily doped region, a third heavily doped region, a fourth heavily doped region, and a fifth heavily doped region. The heavily doped region; the second heavily doped region runs through the base layer, the second heavily doped region is in contact with the first base, and the second heavily doped region is not in contact with the collector layer; the third heavily doped region runs through The base layer, the third heavily doped region is in contact with the second base, and the third heavily doped region is not in contact with the collector layer; the fourth heavily doped region runs through the sub-collector layer, and the fourth heavily doped region is in contact with the second base The first collector contacts; the fifth heavily doped region runs through the sub-collector layer, the fifth heavily doped region is in contact with the second collector; and the second heavily doped region, the third heavily doped region, the fourth heavily doped region The impurity region and the fifth heavily doped region are provided with dopants providing carriers. It should be noted that, considering the material of the substrate, the fourth heavily doped region may or may not be in contact with the substrate, and the fifth heavily doped region may or may not be in contact with the substrate. , in order to avoid direct conduction between the substrate and the fourth heavily doped region or the fifth heavily doped region, the fourth heavily doped region may not be in contact with the substrate, and the fifth heavily doped region may not be in contact with the substrate. Contact; of course, when the substrate is made of an insulating material, the fourth heavily doped region may or may not be in contact with the substrate, and the fifth heavily doped region may or may not be in contact with the substrate. Wherein, the second heavily doped region and the third heavily doped region are provided with dopants providing carriers, because the carriers provided by the dopants can reduce the base (the first base and the second base ) and the resistivity of the ohmic contact resistance of the base layer; the fourth heavily doped region and the fifth heavily doped region are provided with dopants that provide carriers, because the carriers provided by the dopants can reduce the collection The resistivity of the ohmic contact resistance of the electrodes (first collector and second collector) to the sub-collector layer, thus reducing the resistivity on the path between the base and collector electrodes and the active region of the base layer, thereby improve device efficiency.

In a possible implementation manner, the transistor includes at least a heterojunction bipolar transistor (heterojunction bipolar transistor, HBT), the transistor is of NPN type, and the dopant in the first heavily doped region provides N-type carriers; The dopant in the second heavily doped region and the third heavily doped region provides P-type carriers; the dopant in the fourth heavily doped region and the fifth heavily doped region provides N-type carriers. Generally, at least one semiconductor material layer between the emitter of the NPN transistor and the active region of the base layer usually uses a material with N-type carriers, so in order to avoid the The carriers recombine with the carriers in at least one semiconductor material layer, so the dopant in the first heavily doped region also provides N-type carriers. Similarly, materials with P-type carriers are usually used in at least one semiconductor material layer on the path between the base and the active region of the base layer, so the second heavily doped region and the third heavily doped region The dopant in the heterogeneous region provides P-type carriers; at least one semiconductor material layer on the path between the collector and the active region of the base layer usually uses a material with N-type carriers, so The dopants in the fourth heavily doped region and the fifth heavily doped region provide N-type carriers. Similarly, the transistor is of PNP type, and the dopant in the first heavily doped region provides P-type carriers; the dopant in the second heavily doped region and the third heavily doped region provides N-type carriers ; The dopants in the fourth heavily doped region and the fifth heavily doped region provide P-type carriers.

In a possible implementation mode, since the dopant reaches a certain concentration, it can provide the carriers that can really realize the requirement of reducing the resistivity. Therefore, the first heavily doped region, the second heavily doped region, and the third heavily doped region Concentrations of dopants in the doped region, the fourth heavily doped region and the fifth heavily doped region are greater than or equal to a predetermined concentration.

In a possible implementation manner, the predetermined concentrations of dopants in the first heavily doped region, the second heavily doped region, the third heavily doped region, the fourth heavily doped region, and the fifth heavily doped region It is 1e18 atoms/cubic centimeter.

In a fourth aspect, there is provided a method for manufacturing an integrated circuit, which specifically includes the following steps: sequentially forming a plurality of semiconductor material layers stacked on a substrate, the plurality of semiconductor material layers including: a sub-collector layer, a collector layer, The base layer, the emitter layer, and the emitter capping layer; the regions on both sides of the emitter layer above the base layer and the emitter capping layer are etched by an etching process to form a first stepped surface and a second stepped surface; through The etching process etches the collector layer above the sub-collector layer and the regions on both sides of the base layer to form a third stepped surface and a fourth stepped surface. Making a photoresist covering multiple semiconductor material layers, and performing photolithography on the emitter area on the emitter capping layer to form an emitter opening. The first heavily doped region is formed by implanting the dopant that provides carriers through the emitter window; wherein, the first heavily doped region runs through the emitter capping layer and the emitter layer, and the first heavily doped region is connected to the base region The layers do not touch. The emitter is fabricated in the emitter opening, wherein the first heavily doped region is in contact with the emitter. making a photoresist covering multiple semiconductor material layers, and performing photolithography on the base layer to form a first base opening and a second base opening; making a first base in the first base opening, Fabricate the second base in the second base opening; fabricate a photoresist covering multiple layers of semiconductor material and perform photolithography on the sub-collector layer to form the first collector opening and the second collector opening ; Make the first collector in the first collector opening and the second collector in the second collector opening.

In a possible implementation manner, the first base is formed in the first base opening, and before the second base is formed in the second base opening, it also includes: implanting through the first base opening to provide Carrier dopant to form a second heavily doped region, wherein the second heavily doped region runs through the base layer, and the second heavily doped region is not in contact with the collector layer; provided by the second base window implantation The carrier dopant forms a third heavily doped region, the third heavily doped region runs through the base layer, and the third heavily doped region is not in contact with the collector layer. Wherein, the second heavily doped region is in contact with the first base, and the third heavily doped region is in contact with the second base. Fabricate the first collector in the first collector opening, and before fabricating the second collector in the second collector opening, further include: injecting dopants that provide carriers through the first collector opening to form The fourth heavily doped region, wherein the fourth heavily doped region runs through the sub-collector layer; the dopant that provides carriers is injected through the second collector opening to form a fifth heavily doped region, wherein the fifth A heavily doped region extends through the sub-collector layer. The fourth heavily doped region is in contact with the first collector, and the fifth heavily doped region is in contact with the second collector. It should be noted that, considering the material of the substrate, the fourth heavily doped region may or may not be in contact with the substrate, and the fifth heavily doped region may or may not be in contact with the substrate. , in order to avoid direct conduction between the substrate and the fourth heavily doped region or the fifth heavily doped region, the fourth heavily doped region may not be in contact with the substrate, and the fifth heavily doped region may not be in contact with the substrate. Contact; of course, when the substrate is made of an insulating material, the fourth heavily doped region may or may not be in contact with the substrate, and the fifth heavily doped region may or may not be in contact with the substrate.

In a possible implementation manner, the transistor includes at least HBT, the transistor is NPN type, and the dopant in the first heavily doped region provides N-type carriers; the second heavily doped region and the third heavily doped region The dopant in the region provides P-type carriers; the dopant in the fourth heavily doped region and the fifth heavily doped region provides N-type carriers; the transistor is PNP type, and the first heavily doped region The dopant provides P-type carriers; the dopant in the second heavily doped region and the third heavily doped region provides N-type carriers; the fourth heavily doped region and the fifth heavily doped region The dopant provides P-type carriers.

In a possible implementation manner, the concentrations of dopants in the first heavily doped region, the second heavily doped region, the third heavily doped region, the fourth heavily doped region, and the fifth heavily doped region are greater than equal to the predetermined concentration.

In a possible implementation manner, the material of the substrate includes any of the following: gallium arsenide GaAs, indium phosphide InP, and gallium nitride GaN.

Wherein, for the technical effects brought about by any possible implementation manner in the fourth aspect, refer to the technical effects brought about by the different implementation manners of the above third aspect, which will not be repeated here.

A fifth aspect provides a power amplifying circuit, including a package structure and any integrated circuit as described in the first aspect and/or the third aspect, wherein the integrated circuit is packaged inside the package structure.

A sixth aspect provides an electronic device, including a power amplifier and an antenna. The power amplifier is used to amplify a radio frequency signal and output it to the antenna for external radiation. The power amplifier includes the power amplifying circuit as described in the fifth aspect.

In a possible implementation manner, the electronic device includes a base station or a terminal.

Wherein, the technical effects brought about by any one of the possible implementations of the fifth aspect and the sixth aspect can refer to the technical effects brought about by any of the different implementations of the first aspect and/or the third aspect above, here I won't repeat them here.

Description of drawings

FIG. 1 is a schematic structural diagram of a terminal provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a base station provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a power amplifier circuit provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of an integrated circuit provided by another embodiment of the present application;

FIG. 6 is a schematic structural diagram of an integrated circuit provided by another embodiment of the present application;

FIG. 7 is a schematic structural diagram of an integrated circuit provided by another embodiment of the present application;

FIG. 8 is a schematic flowchart of a method for manufacturing an integrated circuit provided by an embodiment of the present application;

FIG. 9 is a first structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 10 is a second structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 11 is a third structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 12 is a fourth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 13 is a schematic diagram of the fifth structure of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 14 is a sixth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 15 is a schematic structural diagram VII of an integrated circuit in a manufacturing method of an integrated circuit provided by another embodiment of the present application;

FIG. 16 is a schematic eighth structural diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 17 is a structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit according to another embodiment of the present application;

FIG. 18 is a tenth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 19 is a schematic structural diagram eleventh of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 20 is a schematic structural diagram twelve of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 21 is a schematic structural diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

Fig. 22 is a first structural schematic diagram of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

Fig. 23 is a second structural schematic diagram of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

FIG. 24 is a third structural schematic diagram of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

Fig. 25 is a fourth structural schematic diagram of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

Fig. 26 is a schematic diagram of the fifth structure of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

FIG. 27 is a sixth structural schematic diagram of an integrated circuit in another manufacturing method of an integrated circuit provided by another embodiment of the present application;

Fig. 28 is a first structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 29 is a second structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 30 is a third structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

Fig. 31 is a fourth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 32 is a schematic diagram of the fifth structure of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 33 is a sixth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

Fig. 34 is a structural schematic diagram VII of an integrated circuit in a manufacturing method of an integrated circuit provided by another embodiment of the present application;

FIG. 35 is a schematic eighth structural diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 36 is a structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided in another embodiment of the present application;

FIG. 37 is a first structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 38 is a second structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 39 is a third structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 40 is a fourth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

Fig. 41 is a schematic diagram of the fifth structure of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 42 is a sixth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

Fig. 43 is a structural schematic diagram VII of an integrated circuit in a manufacturing method of an integrated circuit provided by another embodiment of the present application;

FIG. 44 is a schematic eighth structural diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by another embodiment of the present application;

FIG. 45 is a structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided in yet another embodiment of the present application;

FIG. 46 is a tenth structural schematic diagram of an integrated circuit in a method for manufacturing an integrated circuit provided by yet another embodiment of the present application.

Detailed ways

The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them.

The technical term in the embodiment of the application is explained as follows below:

Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; among them, a semiconductor includes intrinsic semiconductors and impurity semiconductors. A pure semiconductor free of impurities and defects, whose internal electron and hole concentrations are equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor. Among them, the impurity doped in the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons), and the impurity semiconductor that provides electron impurities (such as pentavalent phosphorus) is also called an electronic semiconductor or N (negative, negative) type semiconductors, doping impurity semiconductors that provide hole impurities (such as trivalent boron elements) are also called hole type semiconductors or P (positive, positive) type semiconductors, doping can improve the intrinsic semiconductor Conductivity, generally the higher the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of the present application, a layer structure in a device made of a semiconductor (or semiconductor material) is referred to as a semiconductor material layer.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art. In this application, "at least one (layer)" means one (layer) or multiple (layers), and "multiple (layers)" means two (layers) or more than two (layers). "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be It can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and order.

In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the schematic placement of components in the drawings. It should be understood that these directional terms are relative concepts, and they are used for relative For descriptions and clarifications, it may vary accordingly according to changes in the orientation of parts placed in the drawings.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

The technical solution of the present application can be applied to electronic devices, which are different types of terminals such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic devices can also be network devices such as base stations. The electronic device may also be a device such as a power amplifier used in the above-mentioned electronic device. The embodiment of the present application does not specifically limit the specific form of the foregoing electronic device.

FIG. 1 shows a schematic structural diagram of a terminal 100 . The terminal 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, Mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, camera 190 and display screen 191, etc.

It can be understood that, the structure shown in the embodiment of the present application does not constitute a specific limitation on the terminal 100 . In other embodiments of the present application, the terminal 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components. The illustrated components can be realized in hardware, software or a combination of software and hardware.

The processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be directly recalled from the memory. Repeated access is avoided, and the waiting time of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, processor 110 may include one or more interfaces. The interface may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous transmitter (universal asynchronous receiver/transmitter, UART) interface, mobile industry processor interface (mobile industry processor interface, MIPI), general-purpose input and output (general-purpose input/output, GPIO) interface, subscriber identity module (subscriber identity module, SIM) interface, and /or universal serial bus (universal serial bus, USB) interface, etc.

The charging management module 140 is configured to receive a charging input from a charger. Wherein, the charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger through the USB interface 130 . In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through the wireless charging coil of the terminal 100 . While the charging management module 140 is charging the battery 142 , it can also supply power to the terminal through the power management module 141 .

The power management module 141 is used for connecting the battery 142 , the charging management module 140 and the processor 110 . The power management module 141 receives the input from the battery 142 and/or the charging management module 140 to provide power for the processor 110 , the internal memory 121 , the display screen 191 , the camera 190 , and the wireless communication module 160 . The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 may also be disposed in the processor 110 . In some other embodiments, the power management module 141 and the charging management module 140 may also be set in the same device.

The wireless communication function of the terminal 100 can be realized by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor and the baseband processor.

Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in terminal 100 may be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example: Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the terminal 100 . The mobile communication module 150 may include one or more filters, switches, power amplifiers, low noise amplifiers (low noise amplifier, LNA) and the like. The mobile communication module 150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation. The mobile communication module 150 can also amplify the signals modulated by the modem processor, and convert them into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least part of the functional modules of the mobile communication module 150 may be set in the processor 110 . In some embodiments, at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be set in the same device.

A modem processor may include a modulator and a demodulator. Wherein, the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing. The low-frequency baseband signal is passed to the application processor after being processed by the baseband processor. The application processor outputs sound signals through audio equipment (not limited to speaker 170A, receiver 170B, etc.), or displays images or videos through display screen 191 . In some embodiments, the modem processor may be a stand-alone device. In some other embodiments, the modem processor may be independent from the processor 110, and be set in the same device as the mobile communication module 150 or other functional modules.

The wireless communication module 160 can provide wireless local area networks (wireless local area networks, WLAN) (such as wireless fidelity (Wireless Fidelity, Wi-Fi) network), bluetooth (bluetooth, BT), global navigation satellite system, etc. (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field communication technology (near field communication, NFC), infrared technology (infrared, IR) and other wireless communication solutions. The wireless communication module 160 may be one or more devices integrating one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110 . The wireless communication module 160 can also receive the signal to be sent from the processor 110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 for radiation.

In some embodiments, the antenna 1 of the terminal 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the terminal 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology, etc. The GNSS can include global positioning system (global positioning system, GPS), global navigation satellite system (global navigation satellite system, GLONASS), Beidou satellite navigation system (beidou navigation satellite system, BDS), quasi-zenith satellite system (quasi- zenith satellite system (QZSS) and/or satellite based augmentation systems (SBAS).

The terminal 100 realizes the display function through the GPU, the display screen 191 , and the application processor. The GPU is a microprocessor for image processing, and is connected to the display screen 191 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 191 is used to display images, videos and the like. The display screen 191 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (active-matrix organic light emitting diode, AMOLED), flexible light-emitting diode (flex light-emitting diode, FLED), Miniled, MicroLed, Micro-oLed, quantum dot light emitting diodes (quantum dot light emitting diodes, QLED), etc. In some embodiments, the terminal 100 may include 1 or N display screens 191, where N is a positive integer greater than 1. The terminal 100 can realize the shooting function through the ISP, the camera 190 , the video codec, the GPU, the display screen 191 and the application processor.

The ISP is used for processing data fed back by the camera 190 . For example, when taking a picture, open the shutter, the light is transmitted to the photosensitive element of the camera through the lens, and the optical signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image visible to the naked eye. ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP may be located in the camera 190 .

Camera 190 is used to capture still images or video. The object generates an optical image through the lens and projects it to the photosensitive element. The photosensitive element may be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP to convert it into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. DSP converts digital image signals into standard RGB, YUV and other image signals. In some embodiments, the terminal 100 may include 1 or N cameras 190, where N is a positive integer greater than 1.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the terminal 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. Such as saving music, video and other files in the external memory card.

The internal memory 121 may be used to store one or more computer programs including instructions. The processor 110 may execute the above-mentioned instructions stored in the internal memory 121, so that the terminal 100 executes various functional applications, data processing, and the like. The internal memory 121 may include an area for storing programs and an area for storing data. Wherein, the stored program area can store an operating system; the stored program area can also store one or more application programs (such as a gallery, contacts, etc.) and the like. The data storage area can store data created during the use of the terminal 100 (such as photos, contacts, etc.) and the like. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (universal flash storage, UFS) and the like. In other embodiments, the processor 110 enables the terminal 100 to execute various functional applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The terminal 100 may implement an audio function through an audio module 170 , a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, and an application processor. Such as music playback, recording, etc.

The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signal. The audio module 170 may also be used to encode and decode audio signals. In some embodiments, the audio module 170 may be set in the processor 110 , or some functional modules of the audio module 170 may be set in the processor 110 .

Speaker 170A, also referred to as a "horn", is used to convert audio electrical signals into sound signals. Terminal 100 can listen to music through speaker 170A, or listen to hands-free calls.

Receiver 170B, also called "earpiece", is used to convert audio electrical signals into sound signals. When the terminal 100 answers a phone call or voice information, the receiver 170B can be placed close to the human ear to listen to the voice.

The microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can put his mouth close to the microphone 170C to make a sound, and input the sound signal to the microphone 170C. The terminal 100 may be provided with one or more microphones 170C. In some other embodiments, the terminal 100 may be provided with two microphones 170C, which may also implement a noise reduction function in addition to collecting sound signals. In some other embodiments, the terminal 100 can also be equipped with three, four or more microphones 170C to realize sound signal collection, noise reduction, identify sound sources, realize directional recording functions, and the like.

The earphone interface 170D is used for connecting wired earphones. The earphone interface 170D can be a USB interface 130, or a 3.5mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

The sensor module 180 may include a pressure sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, and the like.

In the embodiments of the present application, a touch sensor is also referred to as a "touch device". The touch sensor can be arranged on the display screen 191, and the touch sensor and the display screen 191 form a touch screen, also called “touch screen”. The touch sensor is used to detect a touch operation on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation may be provided through the display screen. In some other embodiments, a touch panel with a touch sensor array formed by a plurality of touch sensors may also be installed on the surface of the display panel in a hanging form. In some other embodiments, the location of the touch sensor and the display screen 191 may also be different. In the embodiment of the present application, the form of the touch sensor is not limited, for example, it may be a capacitor or a piezoresistor.

In addition, the above-mentioned terminal 100 may further include one or more components such as keys, motors, indicators, and a subscriber identification module (subscriber identification module, SIM) card interface, which is not limited in this embodiment of the present application. The electronic equipment provided in the embodiments of the present application takes a 5G base station as an example. The 5G base station can be divided into a base band unit (base band unit, BBU)-active antenna unit (active antenna unit, AAU), a centralized unit-distribution unit (central unit-distribute unit, CU-DU)-AAU, BBU-remote radio unit (RRU)-antenna, CU-DU-RRU-Antenna, integrated 5G base station (5G node base station, gNB ) and other different architectures. Taking the base station of the BBU-RRU architecture as an example, as shown in Figure 2, the base station: includes BBU21, RRU22 and antenna 23; wherein BBU21 and RRU22 are connected through optical fibers, and the interface between the two is based on an open general public radio frequency interface (common public radio interface (CPRI) and open base station architecture initiative (OBSAI). Wherein, the BBU21 sends the generated baseband signal to the antenna 23 for transmission after being processed by the RRU22. The RRU 22 includes a digital intermediate frequency module 221 , a transceiver module 222 , a power amplifier 223 (power amplifier, PA) and a filter 224 . Among them, the digital intermediate frequency module 221 is used for the modulation and demodulation of the baseband signal transmitted by optical fiber, digital up-down conversion, digital to analog converter (digital to analog converter, D/A), etc. to form an intermediate frequency signal; the transceiver module 222 completes the conversion of the intermediate frequency signal to the radio frequency Signal conversion; the power amplifier 223 is used to amplify the power of the low-power radio frequency signal; the filter 224 is used to filter the radio frequency signal, and then transmit the radio frequency signal through the antenna 23 .

Of course, the power amplification circuit provided by the embodiment of the present application can be applied to the power amplifier of the mobile communication module 150 or the wireless communication module 160 in the terminal 100 provided in FIG. 1 , or the power amplifier of the RRU 22 in the base station provided in FIG. 2 . Of course, the specific application scenarios are not limited to the terminal shown in FIG. 1 and the base station shown in FIG. 2. It can be understood that any of the above-mentioned electronic devices that need to use the power amplifier circuit in the power amplifier to amplify the signal belongs to the implementation of this application. Example application scenarios.

Wherein, the embodiment of the present application provides a power amplifier circuit 30 including an integrated circuit 31 and a package structure 32 , wherein the integrated circuit 31 is packaged inside the package structure 32 . As shown in FIG. 3 , a specific package structure of a power amplifier circuit 30 is provided, wherein an integrated circuit 31 is packaged in a package structure 32 of the power amplifier circuit 30. As shown in FIG. 3 , the package structure 32 specifically includes: a heat dissipation substrate 321 , wherein in order to improve the conductivity and heat dissipation of the heat dissipation substrate 321, the heat dissipation substrate 321 can adopt a composite material, such as a stacked structure formed by copper Cu/molybdenum Mo/copper Cu; the integrated circuit 31 is bonded on the heat dissipation substrate 321 by sintering silver , wherein the integrated circuit as shown in Figure 3, part of the electrodes (such as the source) of the integrated circuit transistor and heat dissipation substrate 321 conduction; in addition, part of the electrodes (such as the drain and gate) of the transistor through the The wire bonding is connected to the pins, and the pins are disposed on an insulating layer (such as insulating ceramics), and the insulating layer is bonded to the heat dissipation substrate 321 by an insulating adhesive. In addition, the package structure 32 includes a package package 322, the package package 322 is bonded to the heat dissipation substrate 321 through an insulating adhesive, and one end of the pin is exposed from the package structure to connect to other circuits, wherein the integrated circuit 31 is arranged on the package package 322 and the space surrounded by the heat dissipation substrate 321.

Currently, a practical integrated circuit may include one or more transistors fabricated on a substrate. The transistors may be typical HEMTs on a gallium arsenide (GaAs) substrate. With reference to shown in Figure 4, a kind of typical HEMT structure, comprises the nucleation layer 42 that is arranged on the substrate 41, channel layer 43, barrier layer 44 (for example can be Schottky barrier layer); The first risky layer 45a, the gate 46a, and the second risky layer 45b on the barrier layer 44, wherein the gate 46a is arranged between the first risky layer 45a and the second risky layer 45b, and is arranged on the first risky layer The source 46b on 45a, and the drain 46c on the second sink layer 45b. There is an active area in the channel layer 43, and the active area is the area in the channel layer 43 directly below the gate 46a. The potential well depth of the heterojunction formed by the barrier layer 44 and the channel layer 43 can control the concentration of the two-dimensional electron gas generated above the active region of the channel layer 43 (refer to the channel shown in FIG. 4 layer 43) to control the operating current of the device. In addition, in order to further improve the performance of the device (such as increasing the concentration of two-dimensional electron gas, reducing the leakage current or increasing the response speed of the device, etc.), it is also possible between the nucleation layer 42 and the channel layer 43, and between the channel layer 43 and the Other semiconductor material layers are arranged between the barrier layers 44 , for example, one or more buffer layers, and a doped layer may also be arranged between the buffer layers. As shown in FIG. 4, a first buffer layer 47a, a first doped layer 48a, and a second buffer layer 47b are arranged from bottom to top between the nucleation layer 42 and the channel layer 43; between the channel layer 43 and the potential A third buffer layer 47c, a second doped layer 48b and a fourth buffer layer 47d are disposed between the barrier layers 44 from bottom to top. Of course, the above only describes a typical HEMT layer structure, and in other embodiments, more material layers or fewer material layers may be included in order to improve device performance.

Wherein, the substrate 41 includes undoped gallium arsenide GaAs, and the superlattice layer 42 includes undoped aluminum arsenide-gallium arsenide (AlAs-GaAs, for example, aluminum arsenide and gallium arsenide can be alternately stacked. superlattice structure), the first buffer layer 47a, the second buffer layer 47b, the third buffer layer 47c and the fourth buffer layer 47d respectively contain undoped aluminum gallium arsenide AlGaAs, the first doped layer 48a and the second buffer layer The two doped layers 48b respectively contain silicon Si, the channel layer 43 contains indium gallium arsenide InGaAs, wherein the composition of indium In in the channel layer 43 will vary with the design of different products, and the barrier layer 44 contains undoped Aluminum gallium arsenide AlGaAs, the first capping layer 45a and the second capping layer 45b respectively contain gallium arsenide GaAs doped with N-type impurities (electronic impurity), usually a barrier layer 44 and the capping layer 45 can also be provided The etch stop layer is made of materials such as aluminum arsenide AlAs or indium arsenide InAs.

Among them, the function of the nucleation layer 42 is to match the lattice structure of the substrate 41 with the lattice structure of the channel layer 43, for example, a layer with a smaller difference from the lattice structure of the substrate 41 can be placed on the substrate 41 first. The nucleation layer 42 is formed on the nucleation layer 42, and then the channel layer 43 with a smaller lattice structure difference from the nucleation layer 42 is fabricated, wherein the nucleation layer 42 may adopt a superlattice structure. A repeating unit of a superlattice structure is composed of two different semiconductor material layers. When the thickness and period length of the two semiconductor material layers are smaller than the mean free path of electrons, quantum size effects can be generated in the superlattice structure. At this point, the wells sandwiched between the two semiconductor material layers of the superlattice structure are quantum wells. Using the binding effect of the energy potential well generated by the quantum well on the electrons, the electrons move in the direction parallel to the interface of the nucleation layer, and the lateral migration of the electrons is improved, thereby avoiding or reducing the direct vertical entry of electrons into the substrate parallel to the interface41 probability, thereby reducing the leakage of the substrate 41. Wherein, the barrier layer 44 is usually not doped, and the barrier layer 44 with unidirectional current flow capability is formed under the grid 46a by utilizing the work function difference between it and the gate 46a (usually a metal material). While improving the ability of the gate 46a to control the channel layer 43, it can also effectively reduce the leakage problem of the gate 46a. The risk layer 45 on the surface of the barrier layer 44 (namely the first risk layer 45a and the second risk layer 45b) can ensure good ohmic contact between the barrier layer 44 and the source electrode 46b and the drain electrode 46c. The first buffer layer 47a, the second buffer layer 47b, the third buffer layer 47c, and the fourth buffer layer 47d have different band gaps from the channel layer 43, which can make the heterojunction formed by the barrier layer 44 and the channel layer 43 The potential well depth is deeper, so as to ensure that the electrons doped in the first doped layer 48a and the second doped layer 48b can increase the concentration of the two-dimensional electron gas. Meanwhile, in order to reduce the decrease in mobility caused by electron scattering, the first buffer layer 47 a , the second buffer layer 47 b , the third buffer layer 47 c and the fourth buffer layer 47 d generally adopt an undoped structure.

Since there are one or more semiconductor material layers between the active region of the channel layer 43 and the source 46b (or drain 46c), such as the capping layer 45, the barrier layer 44, the third buffer layer 47c, the second doped The impurity layer 48b, the fourth buffer layer 47d, and other regions in the channel layer 43 other than the active region, and the like. The above-mentioned semiconductor material layers can achieve positive effects on improving device performance (such as increasing the concentration of two-dimensional electron gas, reducing leakage current or improving device response speed, etc.), but they will also affect the channel layer 43 from the active region to the source. The resistivity on the path between pole 46b (or drain 46c), for example: there is ohmic contact between source 46b (or drain 46c) and take-off layer 45, and when the doping concentration requirement of take-off layer 45 is different , showing different resistivities; in addition, the barrier layer 44, the third buffer layer 47c, the second doped layer 48b, the fourth buffer layer 47d, and the semiconductor material layers in other regions than the active region in the channel layer 43 It also has different resistivities due to doping or non-doping or different doping concentrations, and these factors may lead to The resistivity increases, which affects the efficiency of the device.

In order to solve the above problems, an embodiment of the present application provides an integrated circuit, as shown in FIG. 5 (wherein FIG. 5 is illustrated with a HEMT transistor as an example), including: a substrate 51, wherein the substrate 51 is covered with a transistor 52 The transistor 52 comprises a channel layer 521 stacked on the substrate 51, a barrier layer 5233, and a source 522b, a drain 522c, and a gate 522a arranged on the barrier layer 5233, and there is an active layer in the channel layer 521 The active region is the region where the gate 522 a faces the channel layer 521 . The transistor also includes a first heavily doped region 527a and/or a second heavily doped region 527b, wherein the first heavily doped region 527a penetrates through the barrier layer 5233 and the channel layer 521, and the first heavily doped region 527a and The source electrode 522b contacts; wherein, the second heavily doped region 527b penetrates through the barrier layer 5233 and the channel layer 521, and the second heavily doped region 527b contacts the drain electrode 522c; the first heavily doped region 527a and the second heavily doped region Dopants providing carriers are provided in the impurity region 527b. It should be noted that, considering the material of the substrate 51, the first heavily doped region 527a may or may not be in contact with the substrate 51, and the second heavily doped region 527b may or may not be in contact with the substrate 51, for example: When the substrate 51 is made of a conductive material, in order to prevent the substrate 51 from directly short-circuiting the first heavily doped region 527a and the second heavily doped region 527b, the first heavily doped region 527a may not be in contact with the substrate 51, and the second heavily doped region 527a may not be in contact with the substrate 51. The double doped region 527b may not be in contact with the substrate 51; of course, when the substrate 51 is made of an insulating material, the first heavily doped region 527a may or may not be in contact with the substrate 51, and the second heavily doped region 527b It may or may not be in contact with the substrate 51 . Since the first heavily doped region 527a and the second heavily doped region 527b are provided with dopants providing carriers, and the first heavily doped region 527a is in contact with the source 522b and the second heavily doped region 527b is in contact with the If the drain 522c is in contact, when a voltage is applied to the gate 522a to generate two-dimensional electron gas in the active region of the channel layer 521, the two-dimensional electron gas can pass through the first heavily doped region 527a in the channel layer 521 The active region and the source 522b are transported, and the two-dimensional electron gas can be transported between the active region of the channel layer 521 and the drain 522c through the second heavily doped region 527b, because the dopant can provide the current carrier Therefore, the resistance of the two-dimensional electron gas on the above-mentioned current transmission path is reduced, that is, the carriers provided by the dopant can reduce the distance between the active region in the channel layer 521 and the source electrode 522b and the drain electrode 522c. The resistivity on the path between them improves the efficiency of the device.

Secondly, the transistor includes at least HEMT and MESFET; the transistor is N-type, and the dopant provides N-type carriers; or, the transistor is P-type, and the dopant provides P-type carriers. If the transistor is N-type, then the carriers in the active region of the channel layer 521 are N-type (i.e. electron-type) carriers, or if the transistor is P-type, then the carriers in the active region of the channel layer 521 Carriers are P-type (that is, hole-type) carriers, so in order to prevent the carriers in the active region of the channel layer 521 from recombining with the carriers provided by the dopant (electron-type carriers and hole-type Carrier recombination) affects the concentration of two-dimensional electron gas, so in the embodiment of the present application, the carrier type provided by the dopant is the same as the carrier type in the channel layer 521 active region, that is, the transistor is N-type, the dopant provides N-type carriers; or, the transistor is P-type, and the dopant provides P-type carriers.

In addition, the embodiments of the present application do not limit the types of impurity elements included in the dopant, that is, the dopant may include one or more impurity elements. For example: the dopant that provides N-type carriers includes at least one or more impurity elements in silicon Si, germanium Ge or tin Sn; the dopant that provides P-type carriers includes at least beryllium Be or carbon One or more impurity elements in C.

Referring to FIG. 5 , in order to ensure that the dopant reaches a certain concentration, a current carrying current that reduces the resistivity of the path between the active region of the channel layer 521 and the electrode 522 (such as the source 522b, the drain 522c) can be provided. In other words, the dopant concentration of the first heavily doped region 527a and the second heavily doped region 527b is greater than or equal to a predetermined concentration, and the predetermined concentration is 1e18 atoms/cm3, for example, 1e18˜1e21 atoms/cm3.

Wherein, as shown in FIG. 5 , a first sinking layer 5234a is provided between the source 522b and the barrier layer 5233, and a second sinking layer 5234b is provided between the drain 522c and the barrier layer 5233; the first heavily doped region 527a runs through the first sinking layer 5234a; the second heavily doped region 527b runs through the second sinking layer 5234b. In this possible implementation, the existence of the first risk layer 5234a is to form a good ohmic contact between the barrier layer 5233 and the source 522b, and the existence of the second risk layer 5234b is to make the barrier layer 5233 and the drain A good ohmic contact is formed between poles 522c. Of course, since the first risk layer 5234a is also located on the path between the active region of the channel layer 521 and the source electrode 522b, and the second risk layer 5234b is also located between the active region of the channel layer 521 and the drain electrode 522c Therefore, the first heavily doped region 527a penetrates the first risk layer 5234a, and the second heavily doped region 527b penetrates the second risk layer 5234b, which can also reduce the active region in the channel layer 521 to the source electrode 522b and the resistivity on the path between the drain 522c.

Wherein, as shown in FIG. 5 , at least one buffer layer 5231 (the third buffer layer 5231 a and the fourth buffer layer 5231 b shown in FIG. 5 ) is further arranged between the channel layer 521 and the barrier layer 5233; the first The heavily doped region 527a penetrates at least one buffer layer 5231 ; the second heavily doped region 527b penetrates at least one buffer layer 5231 . The existence of at least one buffer layer 5231 is to further improve the performance of the device (such as increasing the concentration of two-dimensional electron gas, reducing leakage current or improving device response speed, etc.), and at least one buffer layer 5231 is also located in the channel layer 521 On the path between the active region and the source electrode 522b and the drain electrode 522c, therefore, the first heavily doped region 527a penetrates at least one buffer layer 5231, and the second heavily doped region 527b penetrates at least one buffer layer 5231, It is also possible to reduce the resistivity on the path from the active region in the channel layer 521 to the source electrode 522b and the drain electrode 522c.

Wherein, as shown in FIG. 5, a second doped layer 5232 (the third buffer layer 5231a and the fourth buffer layer 5231a shown in FIG. A second doped layer 5232 is disposed between the layers 5231b); the first heavily doped region 527a penetrates the second doped layer 5232; the second heavily doped region 527b penetrates the second doped layer 5232. The existence of the second doped layer 5232 between any two adjacent buffer layers in at least one buffer layer 5231 is to further improve the performance of the device (such as increasing the concentration of two-dimensional electron gas, reducing leakage current or improving device response. speed, etc.), and because the second doped layer 5232 is also located on the path between the active region of the channel layer 521 and the source electrode 522b and the drain electrode 522c, it penetrates the second doped layer 5232 through the first heavily doped region 527a Layer 5232, the second heavily doped region 527b runs through the second doped layer 5232, and can also reduce the resistivity of the path from the active region in the channel layer 521 to the source 522b and the drain 522c. In addition, the substrate material of the integrated circuit includes any of the following: gallium arsenide GaAs, indium phosphide InP, and gallium nitride GaN, and the substrate material can be adjusted according to specific applications, so the embodiments of the present application will not repeat them.

In addition, the transistor may be one or more of HEMT and MESFET.

Referring to FIG. 5, taking the transistor as an example of a HEMT, the transistor may further include at least one layer of semiconductor material layer 523 disposed between the electrode (source 522b or drain 522c) and the channel layer 521, for example at least One layer of semiconductor material layer 523 includes a buffer layer 5231, such as the third buffer layer 5231a and the fourth buffer layer 5231b shown in FIG. layer 5231a and the second doped layer 5232 between the fourth buffer layer 5231b); at least one layer of semiconductor material layer 523 also includes a potential barrier arranged between the electrode (source electrode 522b or drain electrode 522c) and the channel layer 521 Layer 5233; at least one layer of semiconductor material layer 523 also includes a risk layer 5234 disposed between the electrode (source electrode 522b or drain electrode 522c) and the channel layer 521, for example, the first layer between the source electrode 522b and the barrier layer 5233 The second risk layer 5234b between the risk layer 5234a, the drain electrode 522c and the barrier layer 5233. The positional relationship of these semiconductor material layers is shown in FIG. 5. The third buffer layer 5231a covers the channel layer 521, and the second doped layer 5232, the fourth buffer layer 5231b, The barrier layer 5233 , and the first capping layer 5234 a and the second capping layer 5234 b covering the barrier layer 5233 . The aforementioned at least one semiconductor material layer 523 disposed between the electrode (source 522b or drain 522c) and the channel layer 521 is not limited to the structure shown in FIG. 5 , in order to improve device performance or provide devices with other structures, There may be more or less semiconductor material layers between the electrode (the source electrode 522b or the drain electrode 522c ) and the channel layer 521 , which also belongs to the protection scope of the embodiments of the present application.

The transistor 52 also includes a first heavily doped region 527a and/or a second heavily doped region 527b, wherein the first heavily doped region 527a penetrates through the channel layer 521, the third buffer layer 5231a, the second doped layer 5232, the fourth buffer layer 5231b, the barrier layer 5233 and the first buffer layer 5234a, the first heavily doped region 527a is in contact with the source 522b; the second heavily doped region 527b runs through the channel layer 521, the third buffer layer layer 5231a, the second doped layer 5232, the fourth buffer layer 5231b, the barrier layer 5233 and the second risk layer 5234b, the second heavily doped region 527b is in contact with the drain 522c; the first heavily doped region 527a and the second Dopants providing carriers are disposed in the heavily doped region 527b.

Wherein, the materials and functions of the first buffer layer 5234a and the second buffer layer 5234b, the barrier layer 5233, the third buffer layer 5231a, the fourth buffer layer 5231b, and the second doped layer 5232 can refer to the buffer layer 45 in FIG. , the barrier layer 44, the third buffer layer 47c, the fourth buffer layer 47d, and the second doped layer 48b, which will not be repeated here. In addition, in order to improve device performance, as shown in FIG. 5 , other semiconductor material layers may be provided between the channel layer 521 and the substrate 51. The structures of other semiconductor material layers in FIG. The core layer 524, the first buffer layer 525a, the first doped layer 526 and the second buffer layer 525b and other semiconductor material layers, their functions and materials can refer to the nucleation layer 42, the first buffer layer 47a, the first The doped layer 48a and the second buffer layer 47b will not be repeated here.

Wherein, the HEMT may include a pseudomorphic high electron mobility transistor (pseudomorphic high electron mobility transistor, pHEMT); or a metamorphic high electron mobility transistor (metamorphic high electron mobility transistor, mHEMT), which is specifically selected in the end product to include Which kind of transistor integrated circuit is determined by the performance of the end product design, so I won't go into details here.

This transistor is MESFET, as shown in Figure 6, is covered with transistor 62 on the substrate 61, and this transistor 62 comprises the channel layer 621 that is stacked on the substrate 61, barrier layer 622; The source electrode 623 a , the insulating layer 624 , and the drain electrode 623 c are covered from left to right; and a gate 623 b is disposed on the insulating layer 624 . The transistor 62 also includes a first heavily doped region 63a and/or a second heavily doped region 63b, wherein the first heavily doped region 63a penetrates through the barrier layer 622 and the channel layer 621, and the first heavily doped region 63a It is in contact with the source electrode 623a; wherein, the second heavily doped region 63b penetrates through the barrier layer 622 and the channel layer 621, and the second heavily doped region 63b is in contact with the drain electrode 623c; the first heavily doped region 63a and the second heavily doped region A dopant providing carriers is provided in the doped region 63b.

As shown in FIG. 6, in MESFET, the substrate 61 includes silicon Si (for example, the substrate 61 can use a silicon wafer), the channel layer 621 includes gallium nitride GaN, and the barrier layer 622 includes aluminum gallium nitride AlGaN, wherein GaN in the channel layer 621 and AlGaN in the barrier layer 622 form a two-dimensional electron gas at the interface due to the polarization phenomenon. Wherein, under the channel layer 621, semiconductor material layers such as a buffer layer and a nucleation layer are often provided, which are not marked in this embodiment. In order to improve device performance or provide devices with other structures, there may also be more or less semiconductor material layers between the active region of the electrode (source 623a or drain 623c) and the channel layer 621, and in the channel layer There may also be more or less semiconductor material layers between 621 and the substrate 61 , all of which belong to the protection scope of the embodiments of the present application.

When the transistor can also be an HBT, as shown in FIG. 7, the electrodes of the transistor include an emitter (such as the emitter 707a in FIG. 7), a base (such as the first base 707b1 and the second base 707b2 in FIG. 7). ), collectors (such as the first collector 707c1 and the second collector 707c2 in Figure 7). A typical HBT structure as shown in FIG. 7, wherein the substrate 701 is covered with transistors, and the transistors include multiple semiconductor material layers stacked on the substrate 701. As shown in FIG. 7, multiple semiconductor material layers are sequentially arranged from bottom to top It is the sub-collector layer 702, the collector layer 703, the base layer 704, the emitter layer 705, and the emitter capping layer 706; wherein, the sub-collector layer 702 also includes: the first on both sides of the collector layer 703 The collector electrode 707c1 and the second collector electrode 707c2; the base layer 704 also includes: the first base electrode 707b1 and the second base electrode 707b2 located on both sides of the emitter layer 705; the emitter layer 706 also includes: the emitter Pole 707a. Wherein, an active region exists in the base region layer 704 .

The transistor also includes a first heavily doped region 708a; wherein, the first heavily doped region 708a runs through the emitter capping layer 706 and the emitter layer 705, the first heavily doped region 708a is in contact with the emitter 707a, and the first heavily doped region The doped region 708a is not in contact with the base layer 704 . In addition, dopants providing carriers are provided in the first heavily doped region 708a. Wherein, since the dopant providing carriers is provided in the first heavily doped region 708a, the carriers provided by the dopant can reduce the resistivity of the ohmic contact resistance between the emitter 707a and the emitter capping layer 706 , since the first heavily doped region 708a penetrates the emitter layer 705, the resistivity of the emitter layer 705 can also be reduced, so the resistivity of the path between the emitter 707a and the active region of the base layer 704 can be reduced, Thereby improving the efficiency of the device.

As shown in FIG. 7, the transistor may further include one or more of the following heavily doped regions: a second heavily doped region 708b1, a third heavily doped region 708b2, a fourth heavily doped region 708c1, and a fifth heavily doped region region 708c2; the second heavily doped region 708b1 runs through the base layer 704, the second heavily doped region 708b1 is in contact with the first base electrode 707b1, and the second heavily doped region 708b1 is not in contact with the collector layer 703; the third heavily doped region 708b1 is in contact with the collector layer 703; The doped region 708b2 runs through the base layer 704, the third heavily doped region 708b2 is in contact with the second base electrode 707b2, and the third heavily doped region 708b2 is not in contact with the collector layer 703; the fourth heavily doped region 708c1 runs through the secondary The collector layer 702, the fourth heavily doped region 708c1 is in contact with the first collector electrode 707c1; the fifth heavily doped region 708c2 runs through the sub-collector layer 702, and the fifth heavily doped region 708c2 is in contact with the second collector electrode 707c2; and Dopants providing carriers are disposed in the second heavily doped region 708b1 , the third heavily doped region 708b2 , the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 . It should be noted that, considering the material of the substrate 701, the fourth heavily doped region 708c1 may or may not be in contact with the substrate 701, and the fifth heavily doped region 708c2 may or may not be in contact with the substrate 701, for example: When the substrate 701 is made of a conductive material, in order to avoid direct conduction between the substrate 701 and the fourth heavily doped region 708c1 or the fifth heavily doped region 708c2, the fourth heavily doped region 708c1 may not be in contact with the substrate 701, and The fifth heavily doped region 708c2 may not be in contact with the substrate 701; of course, when the substrate 701 is made of an insulating material, the fourth heavily doped region 708c1 may or may not be in contact with the substrate 701, and the fifth heavily doped region 708c2 may or may not be in contact with the substrate 701 . Wherein, the second heavily doped region 708b1 and the third heavily doped region 708b2 are provided with dopants that provide carriers, because the carriers provided by the dopants can reduce the base (the first base 707b1 and the second base 707b1 The resistivity of the ohmic contact resistance between the second base electrode 707b2) and the base layer 704; the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 are provided with dopants that provide carriers, because the dopants provide The carriers can reduce the resistivity of the ohmic contact resistance between the collector (the first collector 707c1 and the second collector 707c2) and the sub-collector layer 702, thus reducing the contact between the base 707b and the collector 707c and the base layer 704 resistivity on the pathways between the active regions, thereby increasing the efficiency of the device.

For HBT, as shown in Figure 7, take GaAs HBT as an example, and this HBT is NPN type, and wherein substrate 701 comprises undoped gallium arsenide GaAs; type impurities, such as gallium arsenide GaAs with at least 1e18 impurity atoms per cubic centimeter); the collector layer 703 contains gallium arsenide GaAs doped with N-type impurities (electronic impurities), and its doping concentration and concentration change The gradient can be changed according to the requirements of different products; the base layer 704 contains gallium arsenide GaAs doped with P-type (hole-type) impurities, the emitter layer 705 contains indium gallium phosphide InGaP doped with N-type impurities, and the emitter The risk layer 706 includes indium gallium arsenide InGaAs heavily doped with N-type impurities (electronic impurities, such as at least 1e18 impurity atoms per cubic centimeter); sometimes for different device requirements, the emitter layer 705 and the emitter layer Between 706, gallium arsenide GaAs material doped with N-type impurity (electronic impurity) can also be set as a transition layer to form rectification capability, and the doping concentration varies according to different product performance requirements.

When the transistor is HBT, and the transistor is NPN type, the dopant of the first heavily doped region 708a provides N-type carriers; the dopant of the second heavily doped region 708b1 and the third heavily doped region 708b2 provide P-type carriers; dopants in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 provide N-type carriers. Usually, at least one semiconductor material layer between the emitter 707a of the NPN transistor and the active region of the base layer 704 is usually made of a material with N-type carriers, so in order to avoid the dopant The provided carriers recombine with the carriers in at least one semiconductor material layer, so the dopant in the first heavily doped region 708a provides N-type carriers. Similarly, at least one semiconductor material layer on the path between the base 707b (the first base 707b1 or the second base 707b2 shown in FIG. 7 ) and the active region usually adopts a P-type current-carrying material layer. Therefore, the dopant in the second heavily doped region 708b1 and the third heavily doped region 708b2 provides P-type carriers; the collector 707c (the first collector 707c1 or the second collector shown in FIG. 7 At least one layer of semiconductor material layer on the path between the collector electrode 707c2) and the active region usually uses a material with N-type carriers, so the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 The dopant provides N-type carriers. Similarly, if the transistor is of PNP type, the dopant of the first heavily doped region 708a provides P-type carriers; the dopant of the second heavily doped region 708b1 and the third heavily doped region 708b2 provide N-type carriers; the dopants in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 provide P-type carriers.

The types of dopants are not limited in the embodiments of the present application, for example, the above dopants may include one or more impurity elements. Wherein, the dopant that provides N-type carriers includes at least one or more impurity elements in silicon Si, germanium Ge or tin Sn; the dopant that provides P-type carriers includes at least beryllium Be or carbon One or more impurity elements in C.

Since the dopant reaches a certain concentration, it can provide the carriers that can actually reduce the resistivity. Therefore, the first heavily doped region 708a, the second heavily doped region 708b1, the third heavily doped region 708b2, and the fourth Concentrations of dopants in the heavily doped region 708c1 and the fifth heavily doped region 708c2 are greater than or equal to a predetermined concentration.

The predetermined concentration of the dopant in the first heavily doped region 708a, the second heavily doped region 708b1, the third heavily doped region 708b2, the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 is 1e18 atoms/ A cubic centimeter may be, for example, 1e18 to 1e21 atoms/cubic centimeter.

In addition, the embodiments of the present application also provide specific materials used for the substrate. For example, the substrate material of a transistor in an integrated circuit may include any of the following: gallium arsenide GaAs, indium phosphide InP, and gallium nitride GaN.

In one implementation, an embodiment of the present application provides a method for manufacturing an integrated circuit, as shown in FIG. 8 , including the following steps:

801. Fabricate a stacked channel layer and a barrier layer sequentially on a substrate.

Wherein, the materials that can be used for the substrate include any of the following: gallium arsenide GaAs, indium phosphide InP, and gallium nitride GaN. Wherein, depending on the material of the substrate, the manufacturing process of the substrate may be produced by chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD), vapor deposition (CVD) and other processes. Of course, according to the material properties of the channel layer and barrier layer stacked above the substrate provided in the above examples, the channel layer and barrier layer stacked on the substrate can also be fabricated by a process similar or identical to that of the substrate. Where there is an active region in the channel layer, the active region may be a region facing the gate in the channel layer. Among them, as described in the above product embodiments, taking HEMT as an example, the semiconductor material layer between the substrate and the channel layer can be made of a nucleation layer and one or more buffer layers, and can also include a multi-layer buffer layer The doped layer between; of course at least one buffer layer can be made on the channel layer, the doped layer can be made between any adjacent two buffer layers in the at least one buffer layer, and the barrier layer can also be Make the first risk layer and the second risk layer.

802. Fabricate a photoresist covering the barrier layer.

For example, a layer of photoresist is coated on the uppermost semiconductor material layer, which can be a positive photoresist or a negative photoresist. For example, if the uppermost semiconductor material layer is a barrier layer, it can be Make the photoresist that covers the barrier layer; or if the uppermost semiconductor material layer is a risk layer (the first risk layer and the second risk layer), you can make the photoresist that covers the first risk layer and the second risk layer .

803. Perform photolithography on the photoresist, form a source window in the source region, and form a drain window in the drain region.

For example, photolithography may be performed on the photoresist made on the covering barrier layer, a source opening is formed in the region of the source, and a drain opening is formed in the region of the drain; or it may be made on the covering first The photoresist of the risk layer and the second risk layer is subjected to photolithography to form a source opening in the region of the source on the first risk layer, and to form a drain opening in the region of the drain on the second risk layer.

804. Inject the dopant providing carriers by opening the source window and the drain window to form a first heavily doped region and a second heavily doped region.

Wherein, the first heavily doped region runs through the barrier layer and the channel layer, or the first heavily doped region runs through the first buffer layer, at least one buffer layer, and any adjacent two buffer layers in the at least one buffer layer The doped layer between; the second heavily doped region runs through the barrier layer and the channel layer, or the second heavily doped region runs through the second buffer layer, at least one buffer layer, and any phase in the at least one buffer layer A doped layer between adjacent two buffer layers.

Wherein, the dopant may include one or more impurity elements. The embodiment of the present application does not limit the type of impurity elements contained in the dopant, for example: the dopant providing N-type carriers includes at least one or more impurities in silicon Si, germanium Ge or tin Sn element; the dopant providing P-type carriers includes at least one or more impurity elements in beryllium Be or carbon C. In addition, in order to ensure that the carriers provided by the dopant can reduce the resistivity on the path between the electrode and the active region, the surface density of the dopant injected into the first heavily doped region and the second heavily doped region ( That is, the dose per unit area (per square centimeter) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14~1e17 atoms/square centimeter; the energy of ion implantation is determined according to the thickness of the semiconductor material layer that needs to penetrate, and the final ion implantation After completion, the dopant concentration in the first heavily doped region and the second heavily doped region is greater than or equal to 1e18 atoms/cm 3 , for example, 1e18˜1e21 atoms/cm 3 .

In some examples, the transistor includes at least HEMT and MESFET; the transistor is N-type, and the dopant provides N-type carriers; or, the transistor is P-type, and the dopant provides P-type carriers. If the transistor is N-type, the carriers in the active region are N-type (that is, electron-type) carriers, or if the transistor is P-type, the carriers in the active region are P-type (that is, hole-type) Carriers, so in order to avoid the recombination of carriers in the active region and the carriers provided by the dopant (recombination of electron-type carriers and hole-type carriers), affecting the concentration of the two-dimensional electron gas, therefore In the embodiment of the present application, the type of carriers provided by the dopant is the same as that of the carriers in the active region, that is, the transistor is N-type, and the dopant provides N-type carriers; or, the transistor is P Type, the dopant provides P-type carriers.

Among them, the dopant that provides the carrier is implanted through the source opening and the drain opening. After the first heavily doped region and the second heavily doped region are formed, the dopant that provides the carrier for the injection is also required. An annealing process is performed to activate the carriers of the implanted dopants, so that the carriers are uniformly distributed in the first heavily doped region and the second heavily doped region. Of course, the carriers of the implanted dopant can also be activated by the annealing process in the fabrication of subsequent electrodes (source, drain and gate).

805. Fabricate a source, a drain, and a gate on the barrier layer.

Exemplarily, a layer of photoresist can be coated on the uppermost semiconductor material layer, and the photoresist can be a positive photoresist or a negative photoresist, for example, a photoresist can be coated on the barrier layer The glue can alternatively be a photoresist coated on the masking layer. Photolithography is performed on the photoresist and a gate opening is formed in the area of the gate. Then make the source in the source opening, make the drain in the drain opening, and make the gate in the gate opening. Wherein the first heavily doped region is in contact with the source, and the second heavily doped region is in contact with the drain.

It should be noted that, considering the material of the substrate, the dopant that provides carriers is implanted through the source opening and the drain opening, and when the first heavily doped region and the second heavily doped region are formed, the first heavily doped region The doped region may or may not be in contact with the substrate, and the second heavily doped region may or may not be in contact with the substrate. Short circuit with the second heavily doped region, then the first heavily doped region may not be in contact with the substrate, and the second heavily doped region may not be in contact with the substrate; of course, when the substrate is made of insulating material, the first heavily doped region The doped region may or may not be in contact with the substrate, and the second heavily doped region may or may not be in contact with the substrate. Since the first heavily doped region and the second heavily doped region are provided with dopants providing carriers, and the first heavily doped region is in contact with the source and the second heavily doped region is in contact with the drain, then When a voltage is applied to the gate to generate a two-dimensional electron gas in the active region of the channel layer, the two-dimensional electron gas can be transported between the active region of the channel layer and the source through the first heavily doped region, And the two-dimensional electron gas can be transported between the active region and the drain of the channel layer through the second heavily doped region, because the dopant can provide carriers, thus reducing the current transmission of the two-dimensional electron gas in the above-mentioned The resistance on the path, that is, the carriers provided by the dopant can reduce the resistivity on the path from the active region in the channel layer to the source and drain, thereby improving the efficiency of the device.

Specifically, taking HEMT as an example for transistors, referring to FIG. 9 to FIG. 21 , the method for manufacturing an integrated circuit provided by the embodiment of the present application includes the following steps:

901. Fabricate a plurality of stacked semiconductor material layers sequentially on a substrate.

Wherein, as shown in FIG. 9 , in order to make the performance of the HEMT device better (such as increasing the concentration of two-dimensional electron gas, reducing the leakage current or improving the response speed of the device, etc.), for example, stacking layers can be sequentially formed on the substrate 51 A plurality of semiconductor material layers are provided, and the plurality of semiconductor material layers sequentially include a nucleation layer 524, a first buffer layer 525a, a first doped layer 526, a second buffer layer 525b, a channel layer 521, a third The buffer layer 5231 a , the second doped layer 5232 , the fourth buffer layer 5231 b , the barrier layer 5233 and the capping layer 5234 . Wherein, an active region exists in the channel layer 521 . Of course, depending on the specific materials used in each of the above semiconductor material layers, multiple semiconductor material layers can be formed on the substrate by using processes such as deposition process and coating process.

902. Fabricate a photoresist covering the capping layer 5234, and perform photolithography to form a first gate opening.

Referring to Fig. 10, the photoresist can be shielded by a shading plate (reticle mask). The shape of the shading plate is as shown in FIG. area, the area where the electrode (such as the grid) is formed is set as the light-transmitting area. As shown in FIG. 10 , the two sides above the masking layer 5234 are opaque areas, and the middle is a light-transmitting area. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a first gate opening, as shown in Figure 11 shown.

903. Etching the risk layer by opening a first gate window to form a gate fabrication region.

Specifically, as shown in FIG. 12, in step 903, dry etching or wet etching can be used to etch the capping layer 5234 exposed under the first gate opening, and the capping layer 5234 is divided into first capping layers 5234a. and the structure of distributed left and right of the second risk layer 5234b, forming a gate fabrication region between the first risk layer 5234a and the second risk layer 5234b.

904. Fabricate a gate in the gate fabrication area.

Specifically, as shown in FIG. 13 , a photoresist may be firstly coated on the capping layer 5234 and the gate fabrication area, and a second gate opening for making the gate is formed on the photoresist by a process similar to step 902. For the window, for example, as shown in FIG. 14 , the photoresist can be shielded by a light-shielding plate. The shape of the light-shielding plate is shown in FIG. 14 , the two sides of the light-shielding plate above the capping layer 5234 are opaque areas, and the middle is a light-transmitting area. It should be noted that the light-shielding plate at this time is similar in structure to the light-shielding plate in FIG. 10 , but the light-transmitting area is smaller than that in FIG. 10 . Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a second grid opening, as shown in Figure 15 shown. Then, as shown in FIG. 16 , the gate 522a is formed in the second gate opening. Specifically, the second gate opening above the barrier layer 5233 can be formed by using a metal deposition process, an evaporation process, or an electroplating process. The gate 522a, generally, the gate 522a can be made of copper, aluminum, manganese and other metal simple substances or alloys.

905. Fabricate a photoresist covering the first capping layer 5234a and the second capping layer 5234b, and perform photolithography to form a source opening in the source area and a drain opening in the drain area.

Specifically, as shown in FIG. 17 , a photoresist can be first coated on the capping layer 5234 (the first capping layer 5234a and the second capping layer 5234b ) and the gate 522a, and a process similar to step 902 is used to coat the photoresist The source window for making the source and the drain window for making the drain are formed on the glue. For example, as shown in FIG. 18, the photoresist can be blocked by a light shield. The region where electrodes (such as source and drain) are formed is set as a light-transmitting area, and other areas are set as light-impermeable areas. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a source opening and a drain opening, As shown in Figure 19.

906 . Inject the dopant providing carriers by opening the source window and the drain window to form a first heavily doped region and a second heavily doped region.

As shown in FIG. 20 , in step 906, ion implantation can be used to implant carrier dopants through source opening and drain opening to form a first heavily doped region and a second heavily doped region. Regions, specifically as shown in FIG. 21 , the first heavily doped region 527a below the source opening and the second heavily doped region 527b below the drain opening. The ion implantation region shown in FIG. 21 (that is, the first heavily doped region 527a and the second heavily doped region 527b) penetrates the capping layer 5234, the barrier layer 5233, the fourth buffer layer 5231b, the second doped layer 5232 and the second Three buffer layers 5231a to the channel layer 521. Wherein, the concentration of dopants implanted in the first heavily doped region 527a and the second heavily doped region 527b is used to reduce the ohmic contact between the source (or drain) and the first risk layer 5234a (or second risk layer 5234b). The resistivity of the resistor, the resistivity of the semiconductor material layer on the channel between the electrode (source and/or drain) and the active region; the type and effectiveness of the carriers provided by the ion-implanted dopant The type of carriers in the source region is consistent; the dopant for ion implantation can be a single element or a mixture of multiple elements; the surface density of the dopant for ion implantation (ie, the dose per unit area (per square centimeter) ) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14～1e17 atoms/square centimeter; the energy of ion implantation depends on the risk layer 5234, the barrier layer 5233, the fourth buffer layer 5231b, the second doped layer 5232, the third The thickness of the buffer layer 5231 a and the channel layer 521 is determined; the range of the final ion implantation should reach the channel layer 521 , but cannot pass through the nucleation layer 524 . After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopants, so that the carriers are evenly distributed in the first heavily doped region 527a and the second heavily doped region 527b. Wherein, the annealing process in the fabrication of the subsequent electrodes (source and drain) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the first heavily doped region 527 a and the second heavily doped region 527 b is greater than or equal to 1e18 atoms/cm 3 , for example, 1e18˜1e21 atoms/cm 3 . It should be noted that, when the dopant concentration in the first heavily doped region 527a and the second heavily doped region 527b is higher, the dopant concentration in the first heavily doped region 527a and the second heavily doped region 527b The carrier concentration provided is also higher.

907. Fabricate a source in source opening, and fabricate a drain in drain opening.

As shown in FIG. 21, the source electrode 522b is formed by opening the source electrode. Specifically, the source electrode 522b can be formed by opening the source electrode by using a metal deposition process, an evaporation process, or an electroplating process. Usually, the source electrode 522b can be made of copper, Aluminum, manganese and other metals or alloys; the drain 522c is fabricated in the drain opening, and the same or similar process and materials as the source 522b can be used to fabricate the drain. The manufacturing processes of the source electrode 522b and the drain electrode 522c can be performed simultaneously. The first heavily doped region 527a is in contact with the source 522b, and the second heavily doped region 527b is in contact with the drain 522c.

In this way, an integrated circuit including HEMTs as shown in FIG. 5 can be manufactured. In the above scheme, the fabrication of the gate is performed first, followed by the fabrication of the source and the drain. Of course, the source, the drain, and the gate can also be fabricated in the same step at the same time. Specifically, refer to FIG. 22 to FIG. 27 for the implementation of the present application. Another kind of manufacturing method of the integrated circuit that example provides, comprises the following steps:

1001. Fabricate multiple semiconductor material layers stacked in sequence on a substrate.

1002. Fabricate a photoresist covering the capping layer 5234, and perform photolithography to form a first gate opening.

1003. Etching the risk layer by opening a first gate window to form a gate fabrication region.

The specific process of steps 1001-1003 can refer to the description of steps 901-903, and will not be repeated here. The following steps are continued at 903 to form the structure in FIG. 12 .

1004. Fabricate a photoresist covering the first risk layer and the second risk layer, and perform photolithography to form a source opening in the source area and a drain opening in the drain area.

Specifically, as shown in FIG. 22, a photoresist may be firstly coated on the capping layer 5234 and the gate fabrication region, and a source opening and a drain opening are formed on the photoresist by a process similar to step 1002. For example, as shown in FIG. 22, the photoresist can be shielded by a light-shielding plate. The shape of the light-shielding plate is as shown in FIG. Set to opaque area. As shown in FIG. 22 , the two sides of the light-shielding plate above the capping layer 5234 are light-transmitting areas, and the others are light-impermeable areas. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a source opening and a drain opening, As shown in Figure 23.

1005. Inject the dopant providing carriers by opening the source window and the drain window to form a first heavily doped region and a second heavily doped region.

As shown in FIG. 24 , in step 1005, ion implantation can be used to implant carrier dopants through source opening and drain opening to form a first heavily doped region and a second heavily doped region. area. The ion implantation region shown in FIG. 25 (that is, the first heavily doped region 527a and the second heavily doped region 527b) penetrates the capping layer 5234, the barrier layer 5233, the fourth buffer layer 5231b, the second doped layer 5232, the second The three buffer layers 5231 a and the channel layer 521 , specifically as shown in FIG. 25 , are the first heavily doped region 527 a under the source opening and the second heavily doped region 527 b under the drain opening. Wherein, the dopant concentration implanted in the first heavily doped region 527a and the second heavily doped region 527b is used to reduce the ohmic contact resistance between the source (or drain) and the first risk layer 5234a (or second risk layer 5234b). The resistivity of the resistivity, the resistivity of the semiconductor material layer on the channel between the electrode and the active region; the type of carriers provided by the ion-implanted dopant is consistent with the type of carriers in the active region; The ion-implanted dopant can be a single element or a mixture of multiple elements; the surface density (that is, the dose per unit area (per square centimeter)) of the ion-implanted dopant can be greater than or equal to 1e14 atoms/square centimeter, For example, it can be 1e14-1e17 atoms/square centimeter; the energy of ion implantation depends on the thicknesses of the impingement layer 5234, the barrier layer 5233, the fourth buffer layer 5231b, the second doped layer 5232, the third buffer layer 5231a, and the channel layer 521 Decision; the range of the final ion implantation should reach the channel layer 521 , but not pass through the nucleation layer 524 . After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopants, so that the carriers are evenly distributed in the first heavily doped region 527a and the second heavily doped region 527b. Wherein, the annealing process in the fabrication of the subsequent electrodes (source and drain) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the first heavily doped region 527 a and the second heavily doped region 527 b is greater than or equal to 1e18 atoms/cm 3 , for example, 1e18˜1e21 atoms/cm 3 . It should be noted that, when the dopant concentration in the first heavily doped region 527a and the second heavily doped region 527b is higher, the dopant concentration in the first heavily doped region 527a and the second heavily doped region 527b The carrier concentration provided is also higher.

1006, forming a second gate opening by photolithography.

Specifically, as shown in FIG. 26 , a process similar to step 1002 is used to form a second gate opening for making a gate on the photoresist. For example, as shown in FIG. 26 , the photoresist can be blocked by a light shielding plate. , the shape of the light-shielding plate is shown in FIG. 26 , that is, the area where the grid is formed is set as a light-transmitting area, and the other areas are set as light-impermeable areas. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a second grid opening, as shown in Figure 27 shown.

1007 . Fabricate a source in the source window, fabricate a drain in the drain window, and fabricate a gate in the second gate window.

Specifically, as shown in FIG. 27, the source electrode 522b is formed by opening the source electrode. Specifically, the source electrode 522b can be formed by opening the source electrode by using a metal deposition process, an evaporation process, or an electroplating process. Usually, the source electrode 522b can be Metal simple substance or alloy such as copper, aluminum, manganese, etc. are used; the drain 522c is formed in the drain opening; the gate 522a is formed in the second gate opening. The drain 522c and the gate 522a can be fabricated using the same or similar processes and materials as the source 522b. The manufacturing process of the source 522b, the drain 522c and the gate 522a can be performed simultaneously. In this way, an integrated circuit including HEMTs as shown in FIG. 5 can also be produced. The first heavily doped region 527a is in contact with the source 522b, and the second heavily doped region 527b is in contact with the drain 522c.

Specifically taking MESFET as an example, referring to FIG. 28 to FIG. 36, a method for manufacturing an integrated circuit provided by the embodiment of the present application includes the following steps:

1101. Fabricate a stacked channel layer and a barrier layer sequentially on a substrate.

Wherein, as shown in FIG. 28 , a channel layer 621 and a barrier layer 622 are fabricated on a substrate 61 . Of course, depending on the specific materials used in the above material layers, the channel layer 621 and the barrier layer 622 can be formed on the substrate by using processes such as deposition process and coating process. Wherein, an active region exists in the channel layer 621 .

1102. Make an insulating layer.

Wherein, as shown in FIG. 29 , an insulating layer 624 may be formed on the barrier layer 622 . Depending on the specific material of the insulating layer 624, the insulating layer 624 may be fabricated by a deposition process, a coating process, and the like.

1103 . Fabricate a photoresist covering the insulating layer, and perform photolithography to form source openings and drain openings.

Specifically, a photoresist may be coated on the insulating layer 624, and then photolithography is performed on the photoresist. Referring to Figure 30, the photoresist can be shielded by a shading plate. The shape of the shading plate is as shown in Figure 30, that is, the area where electrodes (such as source and drain electrodes) will be formed is set as a light-transmitting area, and other areas are set as Opaque area. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a source opening and a drain opening, As shown in Figure 31.

1104. Etch the insulating layer by opening the source window and the drain window, and remove the insulating layer region below the source window and the drain window.

Specifically, as shown in FIG. 32 , in step 1104, dry etching or wet etching can be used to etch the insulating layer 624 exposed under the source opening and the drain opening, and the left and right sides of the insulating layer 624 Etching away to form the structure of the insulating layer 624 shown in FIG. 32 , the etched area on the left side of the insulating layer 624 is the source opening, and the etched area on the right side of the insulating layer 624 is the drain opening.

1105 , inject dopant providing carriers by opening a source window and a drain window to form a first heavily doped region and a second heavily doped region.

As shown in FIG. 33 , in step 1105, ion implantation can be used to implant carrier dopants through source opening and drain opening to form the first heavily doped region and the second heavily doped region. region, as shown in FIG. 34, a first heavily doped region 63a is formed under the source opening, and a second heavily doped region 63b is formed under the drain opening, wherein the first heavily doped region 63a penetrates the barrier layer 622 and the channel layer 621 , the second heavily doped region 63 b penetrates through the barrier layer 622 and the channel layer 621 . Wherein, the concentration of the dopant implanted in the first heavily doped region 63a and the second heavily doped region 63b is to reduce the resistivity and source ( Or drain) to the purpose of the resistivity on the path between the active region; the type of carriers provided by the ion-implanted dopant is consistent with the carrier type in the active region; the ion-implanted dopant It can be a single element or a mixture of multiple elements; the surface density of the ion-implanted dopant (that is, the dose per unit area (per square centimeter)) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14～1e17 atoms/cm2; the energy of ion implantation is determined according to the thicknesses of the barrier layer 622 and the channel layer 621; the final implantation range must reach the channel layer 621. After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopants, so that the carriers are evenly distributed in the first heavily doped region 63a and the second heavily doped region 63b. Wherein, the annealing process in the fabrication of the subsequent electrodes (source, drain and gate) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the first heavily doped region 63 a and the second heavily doped region 63 b is greater than or equal to 1e18 atoms/cm 3 , for example, 1e18˜1e21 atoms/cm 3 . It should be noted that, when the dopant concentration in the first heavily doped region 63a and the second heavily doped region 63b is higher, the dopant concentration in the first heavily doped region 63a and the second heavily doped region 63b The carrier concentration provided is also higher.

It should be noted that, considering the material of the substrate 61, when the first heavily doped region 63a and the second heavily doped region 63b are formed by injecting dopants that provide carriers through source opening and drain opening, The first heavily doped region 63a may or may not be in contact with the substrate 61, and the second heavily doped region 63b may or may not be in contact with the substrate 61, for example: when the substrate 61 uses a conductive material, in order to avoid the substrate 61 directly short-circuits the first heavily doped region 63a and the second heavily doped region 63b, then the first heavily doped region 63a may not be in contact with the substrate 61, and the second heavily doped region 63b may not be in contact with the substrate 61. Contact; of course, when the substrate 61 is made of an insulating material, the first heavily doped region 63a may or may not be in contact with the substrate 61 , and the second heavily doped region 63b may or may not be in contact with the substrate 61 .

1106 , forming gate openings by photolithography.

Specifically, as shown in FIG. 35, the photoresist can be shielded by a light-shielding plate. The shape of the light-shielding plate is shown in FIG. 35, that is, the area where the grid is formed is set as a light-transmitting area, and other areas are set as light-impermeable areas. . Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form a gate opening, as shown in FIG. 36 .

1106 . Fabricate a source electrode by opening a source window, fabricate a drain electrode by opening a drain electrode, and fabricate a gate electrode by opening a gate window.

Specifically, as shown in FIG. 36 , the source electrode 623a is formed in the source window. Specifically, the source electrode 623a can be formed in the source window by using a metal deposition process, an evaporation process, or an electroplating process. Usually, the source electrode 623a can use copper, aluminum, manganese and other metal simple substances or alloys; the drain 623c is made in the drain opening, and the gate 623b is made in the gate opening, and the same or similar process and materials as the source 623a can be used to make the drain. pole 623c and gate 623b. The manufacturing processes of the source 623a, the drain 623c and the gate 623b can be performed simultaneously. The first heavily doped region 63a is in contact with the source 623a, and the second heavily doped region 63b is in contact with the drain 623c.

In some cases, in order to better improve the performance of the device, the region of part of the insulating layer 624 under the gate will be etched away first when making the gate (for example, using a thinner insulating layer under the gate can improve the response of the device. speed), and then make the grid. In this way, an integrated circuit including MESFETs as shown in FIG. 6 can be produced.

Of course, in the manufacture of MESFET, it is also possible to make the gate first, and then make the source and drain, so I won't go into details here.

Specifically taking HBT as an example, referring to FIG. 37 to FIG. 46, a method for manufacturing an integrated circuit provided by the embodiment of the present application includes the following steps:

1201. Form a plurality of stacked semiconductor material layers covering the substrate sequentially on the substrate.

Wherein, as shown in FIG. 37 , according to the specific materials used in each of the above semiconductor material layers, multiple semiconductor material layers stacked on the substrate can be formed on the substrate by using processes such as deposition process and coating process. A plurality of stacked semiconductor material layers are arranged on the substrate 701, and the plurality of semiconductor material layers sequentially include a sub-collector layer 702, a collector layer 703, a base layer 704, an emitter layer 705, and an emitter capping layer from bottom to top. 706. The regions on both sides of the emitter layer 705 above the base layer 704 and the emitter capping layer 706 are etched by an etching process to form a first stepped surface F1 and a second stepped surface F2, so that the first stepped surface F2 can be formed in the subsequent process. The first base is formed on the stepped surface F1, and the second base is formed on the second stepped surface F2. The regions on both sides of the collector layer 703 above the sub-collector layer 702 and the base layer 704 are etched by an etching process to form a third stepped surface F3 and a fourth stepped surface F4, so that in the subsequent process, the third stepped surface The first collector is made on the face F3, and the second collector is made on the fourth stepped face F4.

1202 . Fabricate photoresist covering multiple semiconductor material layers, and perform photolithography to form emitter openings.

Specifically, as shown in FIG. 38, a photoresist can be coated on the emitter capping layer 706, the exposed surface of the base layer 704 and the exposed surface of the sub-collector layer 702, and then the photoresist Photolithography is performed above. Referring to Figure 39, the photoresist can be shielded by a light-shielding plate, the shape of the light-shielding plate is shown in Figure 39, that is, the area where an electrode (such as an emitter) is to be formed is set as a light-transmitting area, and other areas are set as an opaque area area. Then, after the coated photoresist is cured, the photoresist in the light-transmitting area is activated by irradiating the light-shielding plate with light, and the photoresist in the light-transmitting area is removed to form an emitter opening as shown in FIG. 40 .

1203 , inject dopant providing carriers by opening an emitter window to form a first heavily doped region.

As shown in FIG. 41 , the first heavily doped region is formed by implanting the dopant that provides carriers through the emitter opening, such as the first heavily doped region 708 a formed under the emitter shown in FIG. 42 . Wherein, the first heavily doped region 708 a runs through the emitter capping layer 706 and the emitter layer 705 , and the first heavily doped region 708 a is not in contact with the base layer 704 . Wherein, the concentration of the dopant implanted in the first heavily doped region 708a is to reduce the resistivity of the ohmic contact resistance between the emitter and the emitter risk layer 706 and the path between the emitter and the active region of the base layer. The resistivity on the object; the type of carriers provided by the ion-implanted dopant is consistent with the carrier type of the dopant in the emitter layer 706 and the emitter layer 705; the ion-implanted dopant It can be a single element or a mixture of multiple elements; the surface density of the ion-implanted dopant (that is, the dose per unit area (per square centimeter)) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14～1e17 Atoms/cm²; the energy of ion implantation needs to be determined according to the thickness of the semiconductor material layer spanning, for example, considering the thickness of the emitter capping layer 706 and the emitter layer 705 . The doping depth of the emitter capping layer 706 and the emitter layer 705 by the dopant may be less than or equal to the thickness of the emitter capping layer 706 and the emitter layer 705 , which is not specifically limited in this embodiment. After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopant, so that the carriers are evenly distributed in the first heavily doped region 708a. Wherein, the annealing process in the fabrication of the subsequent electrode (emitter) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the first heavily doped region 708 a is greater than or equal to 1e18 atoms/cm 3 , for example, it may be 1e18˜1e21 atoms/cm 3 . It should be noted that the higher the dopant concentration in the first heavily doped region 708 a is, the higher the carrier concentration provided by the dopant in the first heavily doped region 708 a is.

1204. Fabricate the emitter in the emitter opening.

Specifically, as shown in FIG. 43, the emitter 707a is formed by opening the emitter window. Specifically, the emitter 707a can be formed by opening the emitter window by using a metal deposition process, an evaporation process, or an electroplating process. Usually, the emitter 707a can be Use copper, aluminum, manganese and other metals as simple substances or alloys. Wherein, the first heavily doped region 708a is in contact with the emitter 707a.

1205. Fabricate a photoresist covering multiple semiconductor material layers, and perform photolithography on the base region layer to form a first base opening and a second base opening; inject carriers through the first base opening The dopant to form the second heavily doped region; the dopant that provides carriers is implanted through the second base opening to form the third heavily doped region, and then the first base opening is made in the first base opening. Base, make the second base in the second base opening.

Referring to FIG. 43 , a photoresist covering multiple semiconductor material layers is fabricated, and photolithography is performed on the base region layer to form a first base opening and a second base opening. Specifically, as shown in FIG. 43, a photoresist is first coated on the emitter electrode, the surface of the bare drain of the base layer 704, and the surface of the bare drain of the sub-collector layer 702, and then photolithography is performed on the base layer. , forming a first base window and a second base window, such as the first base window and the second base window shown in FIG. 44 . The second heavily doped region 708b1 is formed by implanting the dopant that provides carriers through the first base opening, wherein the second heavily doped region 708b1 runs through the base layer 704, and the second heavily doped region 708b1 is connected to the collector The layer 703 is not in contact; the dopant that provides carriers is implanted through the second base opening to form a third heavily doped region 708b2, the third heavily doped region 708b2 runs through the base layer 704, and the third heavily doped region 708b2 is not in contact with the collector layer 703 . Wherein, the concentration of the ion-implanted dopant is to reduce the resistivity of the ohmic contact resistance between the base and the base layer 704; the type of carriers provided by the ion-implanted dopant and the The carrier type of the dopant is consistent; the dopant for ion implantation can be a single element or a mixture of multiple elements; the surface density of the dopant for ion implantation (ie the dose per unit area (per square centimeter) ) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14-1e17 atoms/square centimeter; the energy of ion implantation needs to be determined according to the thickness of the semiconductor material layer spanning, for example, it is considered to be less than or equal to the thickness of the base layer 704. The doping depth of the base layer 704 by the dopants is less than or equal to the depth of the base layer 704 , which is not specifically limited in this embodiment. After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopant so that the carriers are evenly distributed. Wherein, the annealing process in the fabrication of the subsequent electrode (base electrode) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the second heavily doped region 708b1 and the third heavily doped region 708b2 is greater than or equal to 1e18 atoms/cm3, for example, 1e18˜1e21 atoms/cm3. It should be noted that, when the dopant concentration in the second heavily doped region 708b1 and the third heavily doped region 708b2 is higher, the dopant concentration in the second heavily doped region 708b1 and the third heavily doped region 708b2 The carrier concentration provided is also higher.

The first base is made in the first base opening and the second base is made in the second base opening. As shown in Figure 45, the first base 707b1 is formed by opening a window in the first base. Specifically, the first base 707b1 can be formed by opening a window in the first base by using a metal deposition process, an evaporation process, or an electroplating process. Usually The first base electrode 707b1 can be made of copper, aluminum, manganese and other metal elements or alloys. The second base 707b2 is fabricated in the opening of the second base, which can be fabricated using the same material and process as the first base 707b1. Usually, the first base 707b1 and the second base 707b2 are formed simultaneously in the same process. Wherein, the second heavily doped region 708b1 is in contact with the first base 707b1 , and the third heavily doped region 708b2 is in contact with the second base 707b2 .

1207. Fabricate a photoresist covering multiple semiconductor material layers, and perform photolithography on the sub-collector layer to form a first collector window and a second collector window; provide current-carrying through injection through the first collector window Carrier dopant to form the fourth heavily doped region; inject carrier dopant through the second collector window to form the fifth heavily doped region; make the first collector window in the first Collector, make the second collector in the second collector opening.

Making a photoresist covering multiple semiconductor material layers, and performing photolithography on the sub-collector layer to form a first collector opening and a second collector opening. Specifically, as shown in FIG. 45, a photoresist is first coated on the emitter 707a, on the first base 707b1, on the second base 707b2 and on the surface of the exposed drain of the sub-collector layer 702, and then photolithography Photolithography is performed above the glue to form a first collector window and a second collector window, such as the first collector window and the second collector window shown in FIG. 46 . The dopant that provides carriers is implanted through the first collector window to form the fourth heavily doped region 708c1, wherein the fourth heavily doped region 708c1 penetrates the sub-collector layer 702; A dopant that provides carriers forms a fifth heavily doped region 708 c 2 , wherein the fifth heavily doped region 708 c 2 penetrates through the sub-collector layer 702 .

It should be noted that, considering the material of the substrate 701, the fourth heavily doped region 708c1 may or may not be in contact with the substrate 701, and the fifth heavily doped region 708c2 may or may not be in contact with the substrate 701, for example: When the substrate 701 is made of a conductive material, in order to avoid direct conduction between the substrate 701 and the fourth heavily doped region 708c1 or the fifth heavily doped region 708c2, the fourth heavily doped region 708c1 may not be in contact with the substrate 701, and The fifth heavily doped region 708c2 may not be in contact with the substrate 701; of course, when the substrate 701 is made of an insulating material, the fourth heavily doped region 708c1 may or may not be in contact with the substrate 701, and the fifth heavily doped region 708c2 may or may not be in contact with the substrate 701 .

Among them, the dopant concentration of ion implantation in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 is aimed at reducing the resistivity of the ohmic contact resistance between the collector and the sub-collector layer 702; the ion implanted dopant The type of carriers provided is consistent with the carrier type of the dopant in the sub-collector layer 702; the ion-implanted dopant can be a single element or a mixture of multiple elements; the ion-implanted doping The surface density of the object (that is, the dose per unit area (per square centimeter)) can be greater than or equal to 1e14 atoms/square centimeter, for example, it can be 1e14-1e17 atoms/square centimeter; the energy of ion implantation needs to be based on the thickness of the semiconductor material layer spanning Determined, for example, considering a thickness less than or equal to the sub-collector layer 702 . The doping depth of the sub-collector layer 702 by the dopant is smaller than the depth of the sub-collector layer 702 , which is not specifically limited in this embodiment. After the ion implantation is completed, an annealing process is required to activate the carriers of the implanted dopant, so that the carriers are evenly distributed in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2. Wherein, the annealing process in the fabrication of the subsequent electrode (collector) can also be used to activate the carriers of the implanted dopant. After the final ion implantation is completed, the dopant concentration in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 is greater than or equal to 1e18 atoms/cm 3 , for example, 1e18˜1e21 atoms/cm 3 . It should be noted that, when the dopant concentration in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 is higher, the concentration of the dopant in the fourth heavily doped region 708c1 and the fifth heavily doped region 708c2 The carrier concentration provided is also higher.

Make the first collector in the first collector opening and the second collector in the second collector opening. As shown in FIG. 46, the first collector electrode 707c1 is formed by opening the first collector electrode window. Specifically, the first collector electrode 707c1 can be formed on the collector window 1 by using a metal deposition process, an evaporation process, or an electroplating process. Usually, the first collector electrode 707c1 A collector electrode 707c1 can be made of copper, aluminum, manganese and other metals or alloys. The second collector electrode 707c2 is fabricated in the opening of the second collector electrode, and the same material and process as that of the first collector electrode 707c1 can be used for fabrication. Usually, the first collector electrode 707c1 and the second collector electrode 707c2 are formed simultaneously in the same process. Wherein, the fourth heavily doped region 708c1 is in contact with the first collector electrode 707c1, and the fifth heavily doped region 708c2 is in contact with the second collector electrode 707c2.

It should be noted that the fabrication sequence of the above-mentioned base window, collector window and emitter window is not limited. Of course, in some examples, the first base, the second base, the first collector, the second collector, and the emitter can also be fabricated simultaneously through one process.

Wherein, the path between the active region and the emitter of the base layer 704 includes: the emitter layer 705, the emitter capping layer 706; the path between the active region and the collector of the base layer 704 includes: Collector layer 702, collector layer 703. The path between the active area of the base layer 704 and the base includes: other areas than the active area of the base layer 704 . In this way, the integrated circuit including the HBT shown in FIG. 7 can be manufactured.

It should be noted that the photoresists mentioned in the specific implementation manners of the examples of the present application are all positive photoresists, that is, the photoresist can be activated after being illuminated, and then the activated photoresist can be removed. Of course, negative photoresists can also be used in actual operations. It should be noted that negative photoresists will not be activated after being illuminated, and will be activated without illumination. Therefore, when negative photoresist is used, the light-transmitting area and the opaque area of the light-shielding plate in the illustration need to be exchanged, that is, the original light-transmitting area becomes an opaque area, and the original opaque area becomes an opaque area. into a light-transmitting area, and the other steps remain unchanged. Whether positive photoresist or negative photoresist is used, all belong to the protection scope of the embodiments of the present application. Finally, it should be noted that: the above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto, and any changes or replacements within the technical scope disclosed in the application shall be covered by this application. within the scope of the application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

An integrated circuit, characterized in that it includes a substrate covered with transistors;

The transistor includes a channel layer stacked on the substrate, a barrier layer, and a source, a drain, and a gate disposed on the barrier layer;

The transistor further includes a first heavily doped region and/or a second heavily doped region;

Wherein, the first heavily doped region runs through the barrier layer and the channel layer, and the first heavily doped region is in contact with the source; the second heavily doped region runs through the potential a barrier layer and the channel layer, the second heavily doped region is in contact with the drain;

Dopants providing carriers are disposed in the first heavily doped region and the second heavily doped region.
The integrated circuit according to claim 1, wherein the transistors at least include a high electron mobility transistor (HEMT) and a metal-semiconductor field effect transistor (MESFET); the transistor is N-type, and the dopant provides N-type carrier;

or,

The transistor is P-type, and the dopant provides P-type carriers.
The integrated circuit according to claim 1 or 2, characterized in that the dopant comprises one or more impurity elements.
The integrated circuit according to any one of claims 1-3, characterized in that the dopant providing N-type carriers includes at least one or more impurities in silicon Si, germanium Ge or tin Sn element; the dopant providing P-type carriers includes at least one or more impurity elements in beryllium Be or carbon C.
The integrated circuit according to any one of claims 1-4, characterized in that the concentration of the dopant in the first heavily doped region and the second heavily doped region is greater than or equal to a predetermined concentration.
The integrated circuit of claim 5, wherein the predetermined concentration is 1e18 atoms/cm3.
The integrated circuit according to any one of claims 1-6, characterized in that,

A first sinking layer is provided between the source and the barrier layer, and a second sinking layer is provided between the drain and the barrier layer;

The first heavily doped region runs through the first capping layer;

The second heavily doped region runs through the second risk layer.
The integrated circuit according to any one of claims 1-7, characterized in that,

At least one buffer layer is further arranged between the channel layer and the barrier layer;

The first heavily doped region runs through the at least one buffer layer;

The second heavily doped region runs through the at least one buffer layer.
The integrated circuit of claim 8, wherein

A doped layer is further arranged between any two adjacent buffer layers in the at least one buffer layer;

The first heavily doped region runs through the doped layer;

The second heavily doped region runs through the doped layer.
The integrated circuit according to any one of claims 1-9, wherein the material of the substrate comprises any of the following: gallium arsenide GaAs, indium phosphide InP, gallium nitride GaN.
A power amplifier circuit, characterized by comprising a packaging structure and the integrated circuit according to any one of claims 1-10, wherein the integrated circuit is packaged inside the packaging structure.
An electronic device, comprising a power amplifier and an antenna, wherein the power amplifier is used to amplify a radio frequency signal and output it to the antenna for external radiation, and the power amplifier comprises the power amplification circuit as claimed in claim 11 .
The electronic device according to claim 12, wherein the electronic device comprises a base station or a terminal.
A method of manufacturing an integrated circuit, characterized in that,

Fabricating a stacked channel layer and a barrier layer sequentially on the substrate;

making a photoresist covering the barrier layer;

performing photolithography on the photoresist, forming a source opening in the region of the source, and forming a drain opening in the region of the drain;

A first heavily doped region and a second heavily doped region are formed by injecting dopants that provide carriers through the source opening and the drain opening; wherein, the first heavily doped region runs through The barrier layer and the channel layer, the second heavily doped region runs through the barrier layer and the channel layer;

A source, a drain and a gate are formed on the barrier layer, wherein the first heavily doped region is in contact with the source, and the second heavily doped region is in contact with the drain.
The method for manufacturing an integrated circuit according to claim 14, further comprising: forming a first risk layer and a second risk layer on the barrier layer before making the photoresist covering the barrier layer ;

Then the making of the photoresist covering the barrier layer includes: making the photoresist covering the first risk layer and the second risk layer;

The step of performing photolithography on the photoresist to form a source window in the region of the source, and forming a drain window in the region of the drain includes: performing photolithography on the photoresist, in the first A source window is formed in the region of the source on the first risk layer, and a drain window is formed in the region of the drain on the second risk layer;

The first heavily doped region runs through the first sink layer; the second heavily doped region runs through the second sink layer.
The method for manufacturing an integrated circuit according to claim 14 or 15, wherein said sequentially manufacturing channel layers and barrier layers stacked on the substrate comprises: sequentially manufacturing stacked trench layers on the substrate A channel layer, at least one buffer layer and a barrier layer;

Wherein, the first heavily doped region runs through the at least one buffer layer; the second heavily doped region runs through the at least one buffer layer.
The method for manufacturing an integrated circuit according to claim 16, wherein a doped layer is formed between any two adjacent buffer layers in the at least one buffer layer; the first heavily doped A region runs through the doped layer; the second heavily doped region runs through the doped layer.
The method for manufacturing an integrated circuit according to any one of claims 14-17, wherein:

The implantation of the dopant providing carriers through the source opening and the drain opening, after forming the first heavily doped region and the second heavily doped region, further includes:

An annealing process is performed to anneal the dopant.
The manufacturing method of an integrated circuit according to any one of claims 14-17, characterized in that, the implantation of the dopant providing carriers through the source opening and the drain opening forms a second After the first heavily doped region and the second heavily doped region, it also includes:

The dopant is annealed through the annealing process of the source, the drain and the gate.
The method for manufacturing an integrated circuit according to any one of claims 14-19, wherein the transistors at least include HEMTs and MESFETs; the transistors are N-type, and the dopant provides N-type carriers ;

or,

The transistor is P-type, and the dopant provides P-type carriers.
The method for manufacturing an integrated circuit according to any one of claims 14-20, wherein the dopant includes one or more impurity elements.
The method for manufacturing an integrated circuit according to any one of claims 14-21, wherein the dopant providing N-type carriers includes at least one of silicon Si, germanium Ge, or tin Sn or A variety of impurity elements; the dopant providing P-type carriers includes at least one or more impurity elements in beryllium Be or carbon C.
The method for manufacturing an integrated circuit according to any one of claims 14-22, wherein the concentration of the dopant in the first heavily doped region and the second heavily doped region is greater than or equal to a predetermined concentration.
The method of manufacturing an integrated circuit according to claim 23, wherein the predetermined concentration is 1e18 atoms/cubic centimeter.