WO2023178683A1

WO2023178683A1 - High electron mobility transistor, doherty power amplifier and electronic device

Info

Publication number: WO2023178683A1
Application number: PCT/CN2022/083158
Authority: WO
Inventors: 丁瑶; 汤岑
Original assignee: 华为技术有限公司
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2023-09-28

Abstract

The present application relates to the technical field of semiconductors. Provided in the present application are a high electron mobility transistor, a Doherty power amplifier and an electronic device. The present application uses novel channel high electron mobility transistors to replace power amplifiers of multiple power amplifier circuits in the Doherty power amplifier, so that the number of dies used by the Doherty power amplifier can be reduced. The high electron mobility transistor comprises a substrate, and a first channel layer, a first barrier layer, a second channel layer, a second barrier layer and a cap layer which are arranged on the substrate and are stacked from bottom to top, wherein the first barrier layer is located on the side of the first channel layer away from the substrate, and the second barrier layer is located on the side of the second channel layer away from the substrate; the transistor further comprises a gate, a source, a first drain and a second drain; the cap layer is arranged on the side of the second barrier layer away from the substrate; the source, the gate and the second drain are arranged on the cap layer; the first drain is arranged on the first channel layer and is electrically connected to the first channel layer.

Description

High electron mobility transistors, Doherty power amplifiers and electronic equipment

Technical field

This application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor, a Doherty power amplifier and electronic equipment.

Background technique

Doherty power amplifier is a high-power amplifier currently widely used in wireless communication systems. Currently, the Doherty power amplifier includes at least two power amplifier circuits, and each power amplifier circuit is equipped with a power amplifier. Since power amplifiers located in different channels use different dies and need to configure gate voltages separately, this leads to a series of problems such as complex peripheral circuits, poor consistency in mass production, and high costs.

Contents of the invention

Embodiments of the present application provide a high electron mobility transistor, a Doherty power amplifier and electronic equipment, which can reduce the number of dies used in the Doherty power amplifier.

The present application provides a high electron mobility transistor, including a substrate and a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer that are stacked from bottom to top on the substrate. , cap layer. The first barrier layer is located on a side of the first channel layer away from the substrate, and the second barrier layer is located on a side of the second channel layer away from the substrate. The transistor also includes a gate electrode, a source electrode, a first drain electrode, and a second drain electrode. The cap layer is disposed on a side of the second barrier layer away from the substrate, the source electrode, the gate electrode, and the second drain electrode are disposed on the cap layer, and the first drain electrode is disposed on the first channel layer and connected with the first channel layer. The channel layer is electrically connected, the second drain electrode is electrically connected to the second channel layer, and the source electrode is electrically connected to both the first channel layer and the second channel layer.

The above-mentioned high electron mobility transistor can form multiple channels (including the first channel and the second channel) by repeatedly setting the channel layer and the barrier layer, thereby breaking through the theoretical limit of single-channel devices and maintaining high The electron mobility also increases the areal density of the two-dimensional electron gas in the channel. Compared with the traditional single-channel structure, this multi-channel HEMT can effectively reduce the on-resistance and increase the device power density. And based on the multiple channels of the high electron mobility transistor, two signal paths that do not interfere with each other can be formed, so that one bare chip can meet the needs of multiple amplification tubes in the Doherty power amplifier, while also avoiding the need for multiple amplification tubes. The gate voltage of the tube is configured independently, thus simplifying the circuit complexity of the Doherty power amplifier and reducing the cost.

In some possible implementation methods, the first drain electrode is in ohmic contact with the first channel layer; the second drain electrode is in ohmic contact with the second channel layer; and the source electrode is in ohmic contact with both the first channel layer and the second channel layer. touch. Among them, ways to achieve ohmic contact may include etching ohmic contact, implanting ohmic contact, and high-temperature metal ohmic contact.

In some possible implementations, a first insertion layer is provided between the first channel layer and the first barrier layer; a second insertion layer is provided between the second channel layer and the second barrier layer; by inserting The arrangement of layers can improve the electron mobility of the two-dimensional electron gas generated at the channel.

In some possible implementations, a nucleation layer and a buffer layer are provided between the substrate and the first channel layer; the nucleation layer is close to the substrate relative to the buffer layer.

In some possible implementations, the high electron mobility transistor is a GaN HEMT.

An embodiment of the present application also provides a Doherty power amplifier, which includes a main power amplifier circuit and an auxiliary power amplifier circuit. The main power amplifier circuit includes a first amplifier tube, which is used to amplify the signal input to the main power amplifier circuit. The auxiliary power amplifier circuit includes a second amplifier tube, and the second amplifier tube is used to amplify the signal input to the auxiliary power amplifier circuit. The first amplifying tube and the second amplifying tube multiplex the high electron mobility transistor provided in any of the aforementioned possible implementation methods. The source electrode of the high electron mobility transistor serves as the source electrode of the first amplifier tube and the second amplifier tube. The gate electrode of the high electron mobility transistor serves as the gate electrode of the first amplifier tube and the second amplifier tube. The first drain of the high electron mobility transistor serves as the drain of the first amplifier tube. The second drain of the high electron mobility transistor serves as the drain of the second amplifier tube.

In the above-mentioned Doherty power amplifier, a dual-channel high electron mobility transistor is used to replace the two amplifiers in the main power amplifier circuit and the auxiliary power amplifier circuit, and the auxiliary power amplifier is controlled by reasonably setting the distance between the two channels. The gate voltage of the amplifier tube in the circuit is turned on, thus forming two signal paths that do not interfere with each other to meet the needs of the two power amplifier circuits. In this case, the transistor can use one bare chip to meet the needs of multiple power amplifiers. It also avoids the need to separately configure gate voltages for multiple power amplifiers, thereby simplifying the circuit complexity of the Doherty power amplifier and reducing costs. .

In some possible implementation methods, the source of the high electron mobility transistor is connected to the ground terminal; after the input signal of the gate of the high electron mobility transistor is amplified by the first amplifying tube and the second amplifying tube, it passes through the first amplifying tube respectively. drain and 2nd drain output.

In some possible implementation methods, the Doherty power amplifier further includes: a third amplification tube, a fourth amplification tube, a first microstrip line, a second microstrip line, and a third microstrip line. The first drain is connected to the gate of the third amplifier tube, the drain of the third amplifier tube is connected to the combining point through the first microstrip line, and the source of the third amplifier tube is connected to the ground. The second drain is connected to the gate of the fourth amplifier tube through the second microstrip line, the drain of the fourth amplifier tube is connected to the combining point, and the source of the fourth amplifier tube is connected to the ground. The combining point is connected to the output of the Doherty power amplifier through a third microstrip line. In this case, the Doherty power amplifier is an E-Doherty architecture.

In some possible implementations, the high electron mobility transistor includes a plurality of transistor units arranged in sequence and in parallel. The plurality of transistor units include a first transistor unit, a second transistor unit, and a third transistor unit that are arranged adjacently in sequence. The first transistor unit and the second transistor unit share the same source, and the first transistor unit and the second transistor unit are symmetrically arranged along the source. The second transistor unit and the third transistor unit share the same first drain, and the second transistor unit and the third transistor unit are symmetrical along the first drain. In each transistor unit, the second drain electrode is located in a region between the source electrode and the first drain electrode, and the gate electrode is located in a region between the source electrode and the second drain electrode.

An embodiment of the present application provides an electronic device, including a transmitter; the transmitter adopts the Doherty power amplifier provided in any of the above possible implementation methods.

Description of the drawings

Figure 1 is a schematic circuit diagram of a Doherty power amplifier provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a high electron mobility transistor provided in the prior art;

Figure 3 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present application;

FIG. 5 is a schematic layout design diagram of a high electron mobility transistor used in a Doherty power amplifier according to an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description, embodiments, claims and drawings of this application are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating. Or suggestive order. "And/or" is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, "A and/or B" can mean: only A exists, only B exists, and A and B exist simultaneously. , where A and B can be singular or plural. The character "/" generally indicates that the related objects are in an "or" relationship. "At least one (item)" means one or more, and "plurality" means two or more. “At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c" ”, where a, b, c can be single or multiple. "Installation", "connection", "connection", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediary, or it can be It is the internal connection between two components. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, the inclusion of a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such processes, methods, products or devices. "Up", "down", "left", "right", "top", "bottom", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. Relative descriptions and clarifications are used, which may vary accordingly depending on changes in the orientation in which components in the drawings are placed.

An embodiment of the present application provides an electronic device, which is provided with a transmitter, and a Doherty power amplifier is used in the transmitter. The Doherty power amplifier adopts a new multi-channel high-voltage amplifier tube as the amplifier tube in the multi-channel power amplifier circuit. Replacement with high electron mobility transistor (HEMT) is equivalent to using one bare chip to meet the needs of multiple amplifier tubes. It also avoids the need to separately configure gate voltages for multiple amplifier tubes, thereby simplifying the Doherty power amplifier. The circuit complexity is reduced and the cost is reduced.

This application does not limit the installation form of the above-mentioned electronic equipment. Illustratively, the electronic device can be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, a radar, a base station and other electronic products.

The following is a schematic description of the specific structure of the Doherty power amplifier provided in the embodiment of the present application.

Referring to Figure 1, the Doherty power amplifier provided by this application includes an input terminal IN, an output terminal OUT, and multiple power amplifier circuits connected between the input terminal IN and the output terminal OUT, such as main power amplifier circuit 1 (main) and Auxiliary power amplifier circuit 2 (peak).

It can be understood here that the multi-channel power amplifier circuit in the Doherty power amplifier usually includes a main power amplifier circuit (main), and at least one auxiliary power amplifier circuit (peak) in addition to the main power amplifier circuit (main). The embodiment of the present application is explained by taking a main power amplifier circuit (main) and an auxiliary power amplifier circuit 2 as an example. In other possible implementation methods, the Doherty power amplifier may include two or more auxiliary power amplifier circuits (peaks).

Referring to Figure 1, the main power amplifier circuit 1 (main) includes a first amplifier tube D_1 (driver main), and the signal input to the main power amplifier circuit 1 is amplified through the first amplifier tube D_1. The auxiliary power amplifier circuit 2 (peak) includes a second amplifier tube D_2 (driver peak), and the signal input to the auxiliary power amplifier circuit 2 is amplified through the second amplifier tube D_2.

On this basis, this application also provides a new type of dual-channel high electron mobility transistor (HEMT). For the specific structure, please refer to Figure 3 and the relevant description below. Referring to Figure 1, in this application, a dual-channel transistor (HEMT) is used to replace the first amplifier tube D_1 and the second amplifier tube D_2. The dual-channel transistor (HEMT) includes a gate, a source, a first The drain electrode and the second drain electrode; the first drain electrode and the second drain electrode are respectively connected to two different channels. The first drain of the dual-channel transistor (HEMT) serves as the drain of the first amplifying tube D_1; the second drain of the dual-channel transistor (HEMT) serves as the drain of the second amplifying tube D_2. The gate electrode of the dual-channel transistor (HEMT) serves as the gate electrode of the first amplifier tube D_1 and the second amplifier tube D_2, and the source electrode of the dual-channel transistor (HEMT) serves as the gate electrode of the first amplifier tube D_1 and the second amplifier tube D_2. The source; that is, the gate of the first amplifier tube D_1 and the gate of the second amplifier tube D_2 are the same, and the gate of the dual-channel transistor (HEMT) is multiplexed; the source of the first amplifier tube D_1 and the gate of the second amplifier tube D_2 are the same. The sources of tube D_2 are the same, and the sources of the dual-channel transistor (HEMT) are multiplexed.

Schematically, in a Doherty power amplifier, the source of the dual-channel transistor (HEMT) can be connected to the ground, the gate is connected to the input terminal IN of the Doherty power amplifier, and the first drain and the second drain are related The circuit is connected to the output terminal OUT of the Doherty power amplifier. In this way, after the input signal at the input terminal IN is amplified by the first amplifier tube D_1 and the second amplifier tube D_2, it is output to the output terminal OUT through the first drain and the second drain respectively.

To sum up, in the Doherty power amplifier provided by the embodiment of the present application, a dual-channel transistor (HEMT) is used to replace the two amplifier tubes (D_1, D_2) in the main power amplifier circuit 1 and the auxiliary power amplifier circuit 2. The channel transistor (HEMT) can use one bare chip to meet the needs of multiple power amplifiers. It also avoids the need to separately configure gate voltages for multiple power amplifiers, thereby simplifying the circuit complexity of the Doherty power amplifier and reducing costs.

Of course, FIG. 1 is only a schematic illustration using a dual-channel high electron mobility transistor (HEMT) to replace the amplifier tubes in the two-way power amplifier circuit. In other possible implementation methods, the transistor may be provided with three or more channels, thereby enabling the replacement of amplifier tubes in three or more power amplifier circuits.

In addition, this application does not limit the architecture of the Doherty power amplifier. As long as the amplifier tubes in the multi-channel power amplifier circuit have in-phase input signals, they can be replaced by high electron mobility transistors (HEMTs) provided in the embodiments of this application.

Schematically, in some possible implementation methods, as shown in Figure 1, the Doherty power amplifier can be an E-Doherty architecture (enhance Doherty). In this case, the Doherty power amplifier may include a third amplification tube D_3, a fourth amplification tube D_4, a first microstrip line 10, a second microstrip line 20, and a third microstrip line 30. The drain of the first amplifier tube D_1 (that is, the first drain) is connected to the gate of the third amplifier tube D_3. The drain of the third amplifier tube D_3 is connected to the combining point O through the first microstrip line 10. The source of the third amplifier tube D_3 is connected to the ground; the drain of the second amplifier tube D_2 (that is, the second drain) is connected to the gate of the fourth amplifier tube D_4 through the second microstrip line 20. The drain of D_4 is connected to the combining point O, and the source of the fourth amplifier tube D_4 is connected to the ground; the combining point O is connected to the output terminal OUT of the Doherty power amplifier through the third microstrip line 30 .

In the above-mentioned E-Doherty architecture (enhance Doherty), the first amplifier tube D_1 and the second amplifier tube D_2 have the same phase input signal, so a dual-channel HEMT can be used instead. In this E-Doherty architecture, the signal input by the main power amplifier circuit 1 is amplified by the first amplifier tube D_1, further amplified by the third amplifier tube D_3, and impedance transformed through the first microstrip line 10 and output to the combining point. O. The signal input to the auxiliary power amplifier circuit 2 is amplified by the second amplifier tube D_2, phase compensated through the second microstrip line 20, and then amplified by the fourth amplifier tube D_4 before being output to the combining point O. The signals of the two power amplifier circuits (1, 2) undergo impedance transformation through the third microstrip line 30 after the combining point O and are output to the output terminal OUT of the Doherty power amplifier.

It can be understood that the total phase of the first power amplifier circuit 1 (including D_1, D_3, 10) and the total phase of the second power amplifier circuit 2 (including D_2, D_4, 20) are basically the same.

Those skilled in the art will understand that, for the connection between the input terminal (gate) and the output terminal (drain) of the above-mentioned amplifiers (D_1, D_2, D_3, D_4), the input terminals may be correlated through an input matching circuit. The circuit connection, the output terminal can be related to the circuit connection through the output matching circuit.

In addition, it can also be understood that in the multi-channel power amplifier circuits (1, 2) of the Doherty power amplifier, the order of turning on the driving power amplifiers is different. Usually, the main power amplifier circuit (main) can be turned on first, and the auxiliary power amplifier circuit (peak) Then turn on. Therefore, when using a multi-channel high electron mobility transistor (HEMT), the distance between multiple channels can be designed according to actual needs to meet the control signal requirements of the multi-channel power amplifier circuit.

The specific structure of the multi-channel high electron mobility transistor (HEMT) provided in the embodiment of the present application will be further described below in conjunction with the Doherty power amplifier.

Figure 2 is a schematic structural diagram of a traditional single-channel electron mobility transistor (HEMT). Referring to Figure 2, a channel layer and a barrier layer are provided in a single-channel HEMT, and a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer (ie, the heterojunction interface) (2-dimension electron gas, 2DEG) forms channel 100.

Compared with the following, referring to Figure 3, the multi-channel HEMT used in the embodiment of the present application forms multiple channels (such as 101, 102) by repeatedly growing channel layers and barrier layers in the epitaxial structure. Thereby breaking through the theoretical limit of single-channel devices, increasing the two-dimensional electron gas (2DEG) surface density in the channel while maintaining high electron mobility. Compared with the traditional single-channel structure, this multi-channel HEMT can effectively reduce On-resistance, improve device power density.

What can be understood here is that in multi-channel HEMT, the lower channel (i.e. the side closest to the substrate) is opened earlier and therefore can be used for the main power amplifier circuit 1 (main); the upper channel is relatively different from the lower channel It opens later, so the upper channel can be used for the auxiliary power amplifier circuit 2 (peak), and by reasonably setting the distance between adjacent channels, the turn-on gate voltage of the driving power amplifier in the auxiliary power amplifier circuit (peak) is controlled, thereby Two signal paths that do not interfere with each other are formed to meet the needs of the two power amplifier circuits (1, 2).

Schematically, as shown in Figure 3, the embodiment of the present application provides a dual-channel HEMT. The transistor includes a substrate 11 (substrate), a nucleation layer 12 (nucleation), and a buffer layer 13 sequentially provided on the substrate 11. (buffer), first channel layer 21 (channel), first barrier layer 31 (barrier), second channel layer 22 (channel), second barrier layer 32 (barrier), cap layer 40 (cap) . The interface between the first channel layer 21 and the first barrier layer 31 forms the first channel 101 , and the interface between the second channel layer 22 and the second barrier layer 32 forms the second channel 102 .

In addition, the transistor also includes a gate G, a source S, a first drain D1, and a second drain D2. The first drain D1 is electrically connected to the first channel layer 21 , and the second drain D2 is electrically connected to the second channel layer 22 . The first drain electrode D1 may be disposed on the first channel layer 21 to form an electrical connection with the first channel layer 21 . The gate G, the source S, and the second drain D2 may be disposed on the cap layer 40 , and the second drain D2 and the second channel layer 22 are electrically connected through ion implantation. The source S is electrically connected to the first channel layer 21 and the second channel layer 22 through ion implantation.

In this case, when the above-mentioned dual-channel HEMT is applied to the aforementioned E-Doherty architecture, the first drain D1 is equivalent to the drain of the aforementioned first amplifier tube D_1, and the second drain D2 is equivalent to the second amplifier tube D_1. The drain of tube D_2. This dual-channel HEMT can transform the traditional planar layout into a vertical layout. The dual-channel HEMT can replace the two amplifier tubes (D_1, D_2). In this way, a bare One chip can meet the needs of two driving power amplifiers, and at the same time, it avoids the need to separately configure the gate voltage for the two power amplifier circuits, simplifying the circuit complexity of the Doherty power amplifier and reducing the production cost.

In terms of the working principle of the above-mentioned dual-channel HEMT: the voltage between the two drains (D1, D2) and the source S (that is, the drain-source voltage V _D1S , V _D2S ) makes the voltage between the two channels (101, 102) A lateral electric field is generated within the device, and under the action of the lateral electric field, the two-dimensional electron gas (2DEG) is transmitted along the two heterojunction interfaces to form a drain output current (as indicated by the arrow in Figure 3). By controlling the voltage input to the gate G, the depth of the potential well in the heterojunction can be controlled, and the surface density of the two-dimensional electron gas (2DEG) in the channel (101, 102) can be changed, thereby controlling the two drains (D1, 102). D2) output current.

This application does not limit the electrical connection method between the first drain electrode D1 and the first channel layer 21 . Illustratively, in some possible implementations, the first drain D1 and the first channel layer 21 may be arranged to form an ohmic contact, thereby ensuring the electrical connection between the first drain D1 and the first channel 101 . Similarly, the second drain electrode D2 can be arranged to form ohmic contact with the second channel layer 22 , and the source electrode S can form ohmic contact with the first channel layer 21 and the second channel layer 22 . Among them, the method of realizing ohmic contact between the source S, the drain (D1, D2) and the channel layer (21, 22) may include but is not limited to etching ohms, implanting ohms, and high-temperature metal ohms.

Schematically, in some possible implementation methods, as shown in FIG. 3 , the first drain electrode D1 can be connected to the surface of the first channel layer 21 in an etched ohmic contact manner, and the second drain electrode D2 can be connected to the second drain electrode D2 by etching ohmic contact. The surface of the channel layer 22 is connected by implanting ohmic contact, and the source S is connected with the first channel layer 21 and the second channel layer 22 by implanting ohmic contact. In this case, an etching process can be used to remove the film layer above the first channel layer 21 to leak the surface of the first channel layer 21 , and perform the first drain electrode in the leakage area of the first channel layer 21 . The fabrication of D1 ensures ohmic contact between the first drain electrode D1 and the surface of the first channel layer 21 . An implantation process is used to perform ion implantation at a position below the source S to form an implantation region a1. The source S forms ohmic contact with the first channel layer 21 and the second channel layer 22 in the implantation region a1. An implantation process is used to perform ion implantation at a position below the second drain electrode D2 to form an implantation region a2. The second drain electrode D2 forms an ohmic contact with the second channel layer 22 through the implantation region a2.

In addition, as shown in FIG. 4 , in some possible implementations, a first insertion layer n1 may be provided between the first channel layer 21 and the first barrier layer 31 , and between the second channel layer 22 and the second A second insertion layer n2 is provided between the barrier layers 32. The electron mobility of the 2DEG generated at the channel (101, 102) can be improved by the arrangement of the insertion layer (n1, n2).

In addition, this application does not impose restrictions on the materials used for the above-mentioned substrate 11 and other related film layers in the transistor. In practice, they can be set as needed.

Illustratively, the substrate 11 can be made of materials including but not limited to SiC, Si, GaN, GaAs, InP, etc.

Illustratively, the nucleation layer 12 can be made of materials including but not limited to AlN, InAlN, InGaN, ScAlN and the like.

Illustratively, the buffer layer 13 may be made of materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN, etc.

Illustratively, the channel layers (21, 22) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and the like. For example, in some embodiments, the above-mentioned transistors may be GaN HEMTs, and the channel layers (21, 22) may be GaN.

Illustratively, the barrier layers (31, 32) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and the like.

Illustratively, the insertion layer (n1, n2) can use materials including but not limited to AlN, GaN, InAlN, InGaN, ScAlN and other materials.

Illustratively, the cap layer 40 may be made of materials including but not limited to SiN, GaN, AIN, InAlN, InGaN, ScAlN, and the like.

It should be noted that both Figures 3 and 4 are schematically illustrated by taking the HEMT adopting a dual-channel structure as an example, but the application is not limited thereto. In some possible implementation methods, the HEMT also adopts a three-channel structure. , four-channel structure, etc., which can be applied to multi-channel Doherty power amplifiers.

In addition, those skilled in the art should understand that in actual layout design (layout), a single HEMT structure can use multiple transistor units (cells) arranged in parallel. In this application, multiple transistor cells arranged in parallel are used. (i.e., cellular structure) distribution method is not limited.

Schematically, taking the dual-channel HEMT in Figure 4 as an example, the layout design of multiple transistor units in the HEMT will be described below. As shown in FIG. 5 , in some possible implementations, the HEMT may include multiple transistor units (such as C1, C2, and C3) arranged in parallel and arranged in parallel, and two adjacent transistor units are arranged symmetrically. Specifically, the plurality of transistor units include a first transistor unit C1, a second transistor unit C2, and a third transistor unit C3 that are arranged adjacently in sequence. Among them, the first transistor unit C1 and the second transistor unit C2 use the same source S, that is, the first transistor unit C1 and the second transistor unit C2 use the same source pattern; and the first transistor unit C1 and the second transistor unit C2 is placed symmetrically along this source. The second transistor unit C2 and the third transistor unit C3 share the first drain D1, that is, the second transistor unit C2 and the third transistor unit C3 adopt a common first drain pattern, and the second transistor unit C2 and the third transistor unit C3 share the first drain pattern. C3 is arranged symmetrically along the first drain D1. In addition, in each transistor unit (such as C1, C2, C3), the second drain D2 is located in the area between the source S and the first drain D1, and the gate G is located in the source S and the second drain D2 the area between.

Of course, in the HEMT, the sources S of all transistor units are connected to the same conductive pattern as the source of the HEMT, and all the first drains D1 are connected to the same conductive pattern through wires as an output pin of the HEMT. , all the second drains D2 are connected to the same conductive pattern through leads as another output pin of the HEMT, so as to be connected to the subsequent circuit through the two output pins. Among them, the lead connected to the first drain D1 and the lead connected to the second drain D2 can be isolated by a dielectric bridge or an air bridge to ensure the normal operation of the two output pins.

It can be understood that the above-mentioned first transistor unit C1, second transistor unit C2, and third transistor unit C3 do not specifically refer to the three fixed transistor units in the HEMT. They are only relative concepts and can be any of the multiple transistor units. Three transistor units arranged adjacent to each other.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A high electron mobility transistor, characterized by:

substrate;

A first channel layer and a first barrier layer are stacked on the substrate, and the first barrier layer is located on a side of the first channel layer away from the substrate;

A second channel layer and a second barrier layer are stacked on the first barrier layer, and the second barrier layer is located on a side of the second channel layer away from the substrate;

a cap layer, the cap layer being disposed on the side of the second barrier layer away from the substrate;

A first drain electrode, the first drain electrode is disposed on the first channel layer and is electrically connected to the first channel layer;

A source electrode, a gate electrode and a second drain electrode are provided on the cap layer. The second drain electrode is electrically connected to the second channel layer. The source electrode is connected to the first channel layer and the second drain electrode. The second channel layers are all electrically connected.
The high electron mobility transistor according to claim 1, characterized in that:

The first drain electrode is in ohmic contact with the first channel layer;

The second drain electrode is in ohmic contact with the second channel layer;

The source electrode is in ohmic contact with the first channel layer and the second channel layer.
The high electron mobility transistor according to claim 1 or 2, characterized in that:

A first insertion layer is provided between the first channel layer and the first barrier layer;

A second insertion layer is provided between the second channel layer and the second barrier layer.
The high electron mobility transistor according to any one of claims 1-3, characterized in that:

A nucleation layer and a buffer layer are provided between the substrate and the first channel layer;

The nucleation layer is close to the substrate relative to the buffer layer.
The high electron mobility transistor according to any one of claims 1 to 4, characterized in that the high electron mobility transistor is a GaN HEMT.
A Doherty power amplifier, characterized in that it includes a main power amplifier circuit and an auxiliary power amplifier circuit;

The main power amplifier circuit includes a first amplifier tube, the first amplifier tube is used to amplify the signal input to the main power amplifier circuit;

The auxiliary power amplifier circuit includes a second amplifier tube, the second amplifier tube is used to amplify the signal input to the auxiliary power amplifier circuit;

The first amplifier tube and the second amplifier tube multiplex the high electron mobility transistor according to any one of claims 1 to 5;

The source of the high electron mobility transistor serves as the source of the first amplifier tube and the second amplifier tube;

The gate electrode of the high electron mobility transistor serves as the gate electrode of the first amplifier tube and the second amplifier tube;

The first drain of the high electron mobility transistor serves as the drain of the first amplifier tube;

The second drain of the high electron mobility transistor serves as the drain of the second amplifier tube.
The Doherty power amplifier according to claim 6, characterized in that,

The source of the high electron mobility transistor is connected to the ground;

After the input signal of the gate of the high electron mobility transistor is amplified by the first amplifier tube and the second amplifier tube, it is output through the first drain electrode and the second drain electrode respectively.
The Doherty power amplifier according to claim 6 or 7, characterized in that,

The Doherty power amplifier also includes: a third amplification tube, a fourth amplification tube, a first microstrip line, a second microstrip line, and a third microstrip line;

The first drain is connected to the gate of the third amplifier tube, the drain of the third amplifier tube is connected to the combining point through the first microstrip line, and the source of the third amplifier tube Connect to the ground terminal;

The second drain is connected to the gate of the fourth amplifier tube through the second microstrip line, and the drain of the fourth amplifier tube is connected to the combining point. The source is connected to the ground terminal;

The combining point is connected to the output end of the Doherty power amplifier through the third microstrip line.
The Doherty power amplifier according to any one of claims 6-8, characterized in that,

The high electron mobility transistor includes a plurality of transistor units arranged in parallel and arranged in parallel;

The plurality of transistor units include a first transistor unit, a second transistor unit, and a third transistor unit arranged adjacently in sequence;

The first transistor unit and the second transistor unit share a source and are symmetrically arranged along the source;

The second transistor unit and the third transistor unit share a first drain and are symmetrical along the first drain;

In each of the transistor units, the second drain electrode is located in the area between the source electrode and the first drain electrode, and the gate electrode is located in the area between the source electrode and the second drain electrode. .
An electronic device, characterized in that it includes a transmitter; the transmitter adopts the Doherty power amplifier according to any one of claims 6-9.