CN110729190B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
- Publication number
- CN110729190B CN110729190B CN201810778073.1A CN201810778073A CN110729190B CN 110729190 B CN110729190 B CN 110729190B CN 201810778073 A CN201810778073 A CN 201810778073A CN 110729190 B CN110729190 B CN 110729190B
- Authority
- CN
- China
- Prior art keywords
- shallow trench
- trench isolation
- gate structure
- semiconductor substrate
- field plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 48
- 239000012212 insulator Substances 0.000 description 10
- 210000000746 body region Anatomy 0.000 description 6
- -1 boron ions Chemical class 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 238000002513 implantation Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010267 cellular communication Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the method comprises the steps of providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation; forming a patterned photoresist layer over the gate structure; etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation; a shield field plate is formed in the recess. According to the manufacturing method of the semiconductor device, the patterned photoresist layer is formed on the grid electrode, then the grid electrode and the shallow trench isolation are etched by taking the patterned photoresist layer as a mask, and the shielding field plate is formed in the groove formed by etching the shallow trench isolation, so that the process steps are simplified, the process cost is saved, and the device performance is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the continued development of semiconductor technology, lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused MOSFET, LDMOS) devices are widely used in mobile phones, especially in cellular phones, due to their good short channel characteristics. With the increasing growth of the mobile communication market (especially the cellular communication market), the manufacturing process of LDMOS devices is becoming mature. The LDMOS as a power switch device has the characteristics of relatively high working voltage, simple process, easy compatibility with a low-voltage CMOS circuit in process and the like. Since it is generally used in power circuits, it is necessary to obtain a large output power, and therefore it is necessary to be able to withstand a high breakdown voltage. Meanwhile, as the performance requirement on the device of the LDMOS is higher, the control on the electric field distribution needs to be further enhanced.
Therefore, there is a need to propose a new method for fabricating a semiconductor device to solve the above-mentioned problems.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;
forming a patterned photoresist layer over the gate structure;
etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;
a shield field plate is formed in the recess.
Further, the material of the shielding field plate comprises metal.
Further, the gate structure is etched with the patterned photoresist layer as a mask to form separate first and second gate structures.
Further, the step of forming a metal contact over the semiconductor substrate is included simultaneously with the step of forming the shield field plate.
Further, the upper surface of the shielding field plate is not lower than the upper surface of the grid structure.
Further, the semiconductor device includes an LDMOS device.
The present invention also provides a semiconductor device including:
a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;
a groove is formed in the shallow trench isolation, and a shielding field plate is formed in the groove.
Further, the material of the shielding field plate comprises metal.
Further, the gate structure includes separate first and second gate structures.
Further, the upper surface of the shielding field plate is not lower than the upper surface of the grid structure.
The invention also provides an electronic device which comprises the semiconductor device and an electronic component connected with the semiconductor device.
According to the manufacturing method of the semiconductor device, the patterned photoresist layer is formed on the grid electrode, then the grid electrode and the shallow trench isolation are etched by taking the patterned photoresist layer as a mask, and the shielding field plate is formed in the groove formed by etching the shallow trench isolation, so that the process steps are simplified, the process cost is saved, and the device performance is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following more particular description of embodiments of the present invention, as illustrated in the accompanying drawings. The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and not constitute a limitation to the invention. In the drawings, like reference numerals generally refer to like parts or steps.
In the accompanying drawings:
fig. 1 is a schematic flow chart of a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention.
Fig. 2A-2D are schematic cross-sectional views of devices obtained respectively from steps performed sequentially by a method according to an exemplary embodiment of the invention.
Fig. 3 shows a schematic view of an electronic device according to an exemplary embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
Since LDMOS devices are commonly used in power circuits, a large output power is required, and thus must withstand a high breakdown voltage. Meanwhile, as the performance requirement on the device of the LDMOS is higher, the control on the electric field distribution needs to be further enhanced.
In order to overcome the defects in the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;
forming a patterned photoresist layer over the gate structure;
etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;
a shield field plate is formed in the recess.
Wherein the material of the shielding field plate comprises metal; etching the gate structure by taking the patterned photoresist layer as a mask to form a first gate structure and a second gate structure which are separated; forming the shielding field plate and simultaneously forming a metal contact above the semiconductor substrate; the upper surface of the shielding field plate is not lower than the upper surface of the grid structure; the semiconductor device includes an LDMOS device.
According to the manufacturing method of the semiconductor device, the patterned photoresist layer is formed on the grid electrode, then the grid electrode and the shallow trench isolation are etched by taking the patterned photoresist layer as a mask, and the shielding field plate is formed in the groove formed by etching the shallow trench isolation, so that the process steps are simplified, the process cost is saved, and the device performance is improved.
Referring to fig. 1 and 2A-2D, wherein fig. 1 shows a schematic flow chart of a method of fabricating a semiconductor device according to an exemplary embodiment of the present invention, and fig. 2A-2D show schematic cross-sectional views of devices respectively obtained by steps of the method according to an exemplary embodiment of the present invention, which are sequentially carried out.
The invention provides a preparation method of a semiconductor device, as shown in fig. 1, comprising the following main steps:
step S101: providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;
step S102: forming a patterned photoresist layer over the gate structure;
step S103: etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a groove in the shallow trench isolation;
step S104: a shield field plate is formed in the recess.
First, step S101 is performed, and as shown in fig. 2A, a semiconductor substrate 200 is provided, in which a shallow trench isolation 201 is formed in the semiconductor substrate 200, and a gate structure 202 is formed on the shallow trench isolation 201.
Illustratively, the semiconductor device of the present invention comprises a lateral double diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) device, which comprises a first conductivity type and a second conductivity type. Illustratively, the first conductivity type is P-type and the second conductivity type is N-type, wherein the P-type dopant ions include, but are not limited to, boron ions and the N-type dopant ions include, but are not limited to, phosphorous ions or arsenic ions.
Illustratively, the semiconductor substrate 200 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. As one example, the semiconductor substrate 200 is a silicon substrate having a first conductivity type or a second conductivity type.
Illustratively, a P-well is formed in the semiconductor substrate 200 as a Body 2001. As an example, a standard well implantation process is used to form a P-well in a semiconductor substrate, which may be formed by a high energy implantation process, or by a low energy implantation, along with a high temperature thermal annealing process.
Illustratively, a Drift region (Drift) 2002 is also formed in the semiconductor substrate 200, the Drift region 2002 being located within the semiconductor substrate 200, typically a lightly doped region, and for an N-trench LDMOS, the Drift region is N-doped. As an example, the drift region 2002 and the P-well may be formed in a similar manner by a high energy implantation process, or by a low energy implantation in combination with a high temperature thermal annealing process.
As an example, semiconductor substrate 200 has a first conductivity type, body region 2001 has a first conductivity type, and drift region 2002 has a second conductivity type to form an NLDMOS device.
Illustratively, a source region 2004 and a body drain region 2006 are formed in the body region 2001, a doped region 2003 is formed in the drift region 2002, a drain region 2005 is formed in the doped region 2003, and a source and a drain can be respectively led out from the source region 2004 and the drain region 2005.
Further, the source region 2004, the drain region 2005, and the doped region 2003 have the second conductivity type, and the body extension region 2006 has the first conductivity type. Wherein the doping concentration of the drain region 2005 is greater than the doping concentration of the doping region 2003, and the doping concentration of the doping region 2003 is greater than the drift region 2002. As an example, an N-type impurity is implanted into the body region 2001 to form the source region 2004, an N-type impurity is implanted into the doped region 2003 to form the drain region 2005, and the doping concentrations of the source region 2004 and the drain region 2005 may be the same, and thus, both may be simultaneously doped. As an example, a P-type impurity forming body extension region 2006 is implanted in the body region 2001.
Illustratively, shallow trench isolation (Shallow Trench Isolation, STI) 201 is formed in the semiconductor substrate 200. Specifically, a portion of the semiconductor substrate 200 is etched to form shallow trenches in which an isolation material is filled to form shallow trench isolations 201 that isolate active regions.
Illustratively, the shallow trench isolation 201 has a gate structure 202 formed thereon. The gate structure 202 includes a gate dielectric layer and a gate material layer sequentially stacked from bottom to top. The gate dielectric layer comprises an oxide layer, such as silicon dioxide (SiO 2 ) A layer. The gate material layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer.
In addition, an interlayer dielectric layer (not shown) is formed on the semiconductor substrate 200, and the interlayer interface layer covers the source region 2004, the drain region 2005, and the body extension region 2006.
Next, step S102 is performed, and as shown in fig. 2B, a patterned photoresist layer 203 is formed on the gate structure 202.
Illustratively, a photoresist layer is coated on the upper surface of the gate structure 202, and then an exposure and development process is performed by means of a photomask having an exposure pattern, thereby forming an opening pattern in the photoresist.
Next, step S103 is performed, as shown in fig. 2C, to etch the gate structure 202 and the shallow trench isolation 201 with the patterned photoresist layer 203 as a mask, so as to form a groove in the shallow trench isolation 201. Further, the gate structure 202 is etched with the patterned photoresist layer 203 as a mask to form separate first and second gate structures 2021 and 2022.
Illustratively, the gate structure 202 and the shallow trench isolation 201 are etched with the patterned photoresist layer 203 as a mask to form a first recess 204 and a second recess 205, wherein a portion of the gate structure 202 and a portion of the shallow trench isolation 201 are etched to form the first recess 204, the gate structure 202 is etched until an upper surface of the shallow trench isolation 201 is exposed to form the second recess 205, and the second recess 205 separates the gate structure 202 into the first gate structure 2021 and the second gate structure 2022. Specifically, the gate structure 202 and the shallow trench isolation 201 are etched using a dry etching process including, but not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods.
The gate structure 202 is separated into the first gate structure 2021 and the second gate structure 2022 by the second groove 205 to serve as a gate field plate, so that the capacitance of the LDMOS device is increased, the electric field distribution is improved, and the voltage withstand performance is further improved.
Further, the method includes a step of etching an interlayer dielectric layer by using the patterned photoresist layer 203 as a mask to form a Contact hole (Contact hole) in the interlayer dielectric layer above the source region 2004, the drain region 2005 and the body drain region 2006, while etching the gate structure 202 and the shallow trench isolation 201 by using the patterned photoresist layer 203 as a mask.
Next, step S104 is performed, and as shown in fig. 2D, a shielding field plate 206 is formed in the first recess 204.
Illustratively, a metal material (e.g., tungsten) is filled in the first recess 204 to form a shield field plate 206, and an upper surface of the shield field plate 206 is not lower than an upper surface of the gate structure 202. In the present embodiment, the step of filling metal in the Contact holes above the source region 2004, the drain region 2005, and the body-drawn region 2006 to form metal Contacts (CT) is included simultaneously with the formation of the shield field plate 206.
By forming the shield field plate 206 in the first recess 204, the capacitance of the LDMOS device is increased, the electric field distribution is improved, and thus the withstand voltage performance is improved.
According to the manufacturing method of the semiconductor device, the photoresist layer is formed once and the etching process is performed once in the steps, so that compared with the prior art, the manufacturing method of the semiconductor device has the advantages of simplifying the process steps, saving the process cost and improving the device performance.
The structure of the semiconductor device according to the embodiment of the present invention is described below with reference to fig. 2D. The semiconductor device includes: a semiconductor substrate 200, wherein shallow trench isolation 201 is formed in the semiconductor substrate 200, and a gate is formed on the shallow trench isolation 201; the shallow trench isolation 201 has a recess formed therein, in which a shield field plate 206 is formed.
Illustratively, the semiconductor device of the present invention comprises a lateral double diffused metal oxide semiconductor (Laterally Diffused Metal Oxide Semiconductor, LDMOS) device, which comprises a first conductivity type and a second conductivity type. Illustratively, the first conductivity type is P-type and the second conductivity type is N-type, wherein the P-type dopant ions include, but are not limited to, boron ions and the N-type dopant ions include, but are not limited to, phosphorous ions or arsenic ions.
Illustratively, the semiconductor substrate 200 may be at least one of the following mentioned materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. As one example, the semiconductor substrate 200 is a silicon substrate having a first conductivity type or a second conductivity type.
Illustratively, a P-well is formed in the semiconductor substrate 200 as a Body (Body) 2001, and a Drift (Drift) 2002 is also formed in the semiconductor substrate 200, the Drift 2002 being located within the semiconductor substrate 200, typically a lightly doped region, which is N-doped for an N-trench LDMOS. As an example, semiconductor substrate 200 has a first conductivity type, body region 2001 has a first conductivity type, and drift region 2002 has a second conductivity type to form an NLDMOS device.
Further, an active region (source) 2004 and a body drain region 2006 are formed in the body region 2001, a doped region 2003 is formed in the drift region 2002, a drain region (drain) 2005 is formed in the doped region 2003, and a source and a drain can be respectively drawn out from the source region 2004 and the drain region 2005. Wherein the source region 2004, the drain region 2005 and the doped region 2003 have the second conductivity type and the body extension region 2006 has the first conductivity type. Wherein the doping concentration of the drain region 2005 is greater than that of the doped region 2003, and the doping concentration of the doped region 2003 is greater than that of the drift region 2002.
Illustratively, shallow trench isolation (Shallow Trench Isolation, STI) 201 is formed in the semiconductor substrate 200. The shallow trench isolation 201 has a first recess formed therein, and the first recess has a shield field plate 206 formed therein. Further, the material of the shield field plate 206 includes a metal, such as tungsten. By forming the shield field plate 206 in the shallow trench isolation 201, the capacitance of the LDMOS device is increased, the electric field distribution is improved, and the withstand voltage performance is further improved.
Illustratively, a second recess 205 is formed in the gate structure 202, the second recess 205 separating the gate structure 202 into a first gate structure 2021 and a second gate structure 2022. The gate structure 202 is separated into the first gate structure 2021 and the second gate structure 2022 by the second groove 205 to serve as a gate field plate, so that the capacitance of the LDMOS device is increased, the electric field distribution is improved, and the voltage withstand performance is further improved.
The invention also provides an electronic device comprising a semiconductor device and an electronic component connected with the semiconductor device. Wherein the semiconductor device includes: a semiconductor substrate 200, wherein shallow trench isolation 201 is formed in the semiconductor substrate 200, and a gate is formed on the shallow trench isolation 201; the shallow trench isolation 201 has a recess formed therein, in which a shield field plate 206 is formed.
The electronic component may be any electronic component such as a discrete device, an integrated circuit, etc.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or any intermediate product including the semiconductor device.
Wherein fig. 3 shows an example of a handset. The exterior of the cellular phone 300 is provided with a display portion 302, an operation button 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in the housing 301.
The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein shallow trench isolation is formed in the semiconductor substrate, and a grid structure is formed on the shallow trench isolation;
forming a patterned photoresist layer over the gate structure;
etching the gate structure and the shallow trench isolation by using the patterned photoresist layer as a mask to form a first groove and a second groove, wherein part of the gate structure and part of the shallow trench isolation are etched to form the first groove, the gate structure is etched until the upper surface of the shallow trench isolation is exposed to form the second groove, and the second groove separates the gate structure into the first gate structure and the second gate structure;
and forming a shielding field plate in the first groove.
2. The method of manufacturing of claim 1, wherein the material of the shield field plate comprises a metal.
3. The method of claim 1, wherein the gate structure is etched using the patterned photoresist layer as a mask to form separate first and second gate structures.
4. The method of manufacturing of claim 1, further comprising the step of forming a metal contact over the semiconductor substrate concurrently with forming the shield field plate.
5. The method of claim 1, wherein an upper surface of the shield field plate is not lower than an upper surface of the gate structure.
6. The method of manufacturing of claim 1, wherein the semiconductor device comprises an LDMOS device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810778073.1A CN110729190B (en) | 2018-07-16 | 2018-07-16 | Semiconductor device, manufacturing method thereof and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810778073.1A CN110729190B (en) | 2018-07-16 | 2018-07-16 | Semiconductor device, manufacturing method thereof and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110729190A CN110729190A (en) | 2020-01-24 |
| CN110729190B true CN110729190B (en) | 2024-02-27 |
Family
ID=69217352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810778073.1A Active CN110729190B (en) | 2018-07-16 | 2018-07-16 | Semiconductor device, manufacturing method thereof and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110729190B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113838906B (en) * | 2020-06-23 | 2024-01-09 | 芯恩（青岛）集成电路有限公司 | LDMOS transistor and preparation method thereof |
| CN117116995A (en) * | 2023-10-24 | 2023-11-24 | 粤芯半导体技术股份有限公司 | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571393A (en) * | 2015-10-07 | 2017-04-19 | 爱思开海力士有限公司 | Lateral high voltage integrated devices having trench insulation field plates and metal field plates |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5385679B2 (en) * | 2008-05-16 | 2014-01-08 | 旭化成エレクトロニクス株式会社 | Lateral semiconductor device and manufacturing method thereof |
| JP6509665B2 (en) * | 2015-07-23 | 2019-05-08 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2018
- 2018-07-16 CN CN201810778073.1A patent/CN110729190B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571393A (en) * | 2015-10-07 | 2017-04-19 | 爱思开海力士有限公司 | Lateral high voltage integrated devices having trench insulation field plates and metal field plates |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110729190A (en) | 2020-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10643905B2 (en) | IC unit and method of manufacturing the same, and electronic device including the same | |
| KR101909204B1 (en) | Semiconductor device having embedded strain-inducing pattern and method of forming the same | |
| US11075284B2 (en) | Semiconductor structure and forming method thereof | |
| JP2009540579A (en) | Self-aligned gate JFET structure and manufacturing method thereof | |
| KR20150117516A (en) | Method of Forming Semiconductor device | |
| US11081484B2 (en) | IC unit and method of manufacturing the same, and electronic device including the same | |
| CN108155237B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| KR20160055380A (en) | High-voltage integrated device and method of fabricating the same | |
| TWI684281B (en) | High voltage transistor using buried insulating layer as gate dielectric | |
| CN113594039A (en) | Semiconductor structure and forming method thereof | |
| CN110729190B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| JP2014203851A (en) | Semiconductor device and manufacturing method of the same | |
| US10217828B1 (en) | Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same | |
| CN109801960A (en) | Semiconductor devices and its manufacturing method and electronic equipment including the device | |
| US20130069143A1 (en) | Trench type power transistor device and method of fabricating the same | |
| CN113130646B (en) | Semiconductor device and manufacturing method thereof | |
| CN107481929B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN109979993B (en) | High-voltage MOS device, manufacturing method thereof and electronic device | |
| US9437596B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN109980010B (en) | Method for manufacturing semiconductor device and integrated semiconductor device | |
| US10074650B2 (en) | Deep trench isolation for RF devices on SOI | |
| US20080272401A1 (en) | Inverted Junction Field Effect Transistor and Method of Forming Thereof | |
| CN108346689B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| US10199478B2 (en) | Transistor and method for forming the same | |
| US9349748B2 (en) | Method for forming deep trench isolation for RF devices on SOI |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |