CN110557969B

CN110557969B - Method for manufacturing resistance change type memory and resistance change type memory

Info

Publication number: CN110557969B
Application number: CN201880000596.1A
Authority: CN
Inventors: 姚国峰; 沈健
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2018-04-03
Filing date: 2018-04-03
Publication date: 2023-05-16
Anticipated expiration: 2038-04-03
Also published as: CN110557969A; WO2019191907A1

Abstract

The invention provides a manufacturing method of a resistance change type memory and the resistance change type memory, wherein the method comprises the following steps: arranging deep trenches filled with polysilicon on the SOI wafer on the insulating layer to obtain the SOI wafer with the deep trenches; the deep groove penetrates through the silicon device layer and the oxygen burying layer of the SOI wafer and reaches the supporting layer; manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning a supporting layer of an SOI wafer containing a CMOS circuit to the surface of a buried oxide layer, and forming a groove at the top end of a deep groove filled with polysilicon; and manufacturing the memristor on the buried oxide layer of the SOI wafer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved.

Description

Method for manufacturing resistance change type memory and resistance change type memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a resistance change memory and a resistance change memory.

Background

The resistive random access memory (Resistive Random Access Memory, RRAM) is a nonvolatile (Non-volatile) memory which stores information by utilizing the variable resistance characteristic of materials, and has the advantages of low power consumption, high storage density, high read-write speed, strong repeated operation tolerance, long data retention time and the like. The memory cell of the RRAM is called a memristor and is a two-terminal device consisting of a lower electrode, a resistance layer and an upper electrode; the access control unit of the RRAM is a Metal-Oxide-semiconductor field effect transistor (MOSFET), which is a common device of a CMOS circuit.

In the prior art, memristors of the RRAM are usually located between interlayer metals (Inter-metal), so that the electrode material selection range is narrow, and only standard CMOS process compatible materials can be used. However, in order to improve the electrical characteristics of memristors in RRAM, noble metal materials having a higher work function, such as platinum (Pt), iridium (Ir), etc., are sometimes used in addition to metals commonly used in standard CMOS processes, such as tantalum (Ta), titanium (Ti), tungsten (W), titanium nitride (TiN), etc.

However, these noble metal materials with higher work functions tend to be incompatible with standard CMOS processes. Therefore, if the RRAM product is to be diced on a standard CMOS process line of a Front-end-of-wafer (Front-end) factory, the range of options for RRAM electrode materials is severely limited, thereby limiting the electrical storage characteristics of the memristor.

Disclosure of Invention

The invention provides a manufacturing method of a resistance change type memory and the resistance change type memory, which are used for realizing separation of a RRAM standard CMOS circuit manufacturing process and a memristor manufacturing process, so that noble metal is introduced to serve as an electrode of a memristor in the large-scale production process of the RRAM, and the electrical storage characteristic of the memristor in the RRAM is improved.

In a first aspect, the present invention provides a method for manufacturing a resistance change type memory, including:

arranging deep trenches filled with polysilicon on the SOI wafer on the insulating layer to obtain the SOI wafer with the deep trenches; the deep trench penetrates through the silicon device layer and the buried oxide layer of the SOI wafer and reaches the supporting layer;

manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit;

thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon;

And manufacturing a memristor on the buried oxide layer of the SOI wafer, wherein a lower electrode of the memristor is manufactured in the groove.

Optionally, the disposing a deep trench filled with polysilicon on the SOI wafer on the insulating layer to obtain the SOI wafer with the deep trench includes:

sequentially growing a pad oxide layer, a pad nitride layer and a hard mask layer on a silicon device layer of a silicon-on-insulator SOI wafer;

forming a deep trench on the SOI wafer by reactive ion etching, wherein the deep trench comprises: a memory cell region deep trench and a peripheral circuit region deep trench; the storage unit region deep groove and the peripheral circuit region deep groove penetrate through the silicon device layer and the oxygen burying layer of the SOI wafer and reach the supporting layer;

removing the hard mask layer of the SOI wafer with the deep groove by adopting a wet etching mode, and performing thermal oxidation on the SOI wafer with the deep groove to form a layer of pad silicon oxide with preset thickness on the silicon surface of the deep groove;

filling the deep trench with polysilicon for the first time, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep trench to form a groove region between the upper surface of the polysilicon in the deep trench and the surface of the silicon device layer;

Performing high-energy ion implantation around the groove area according to a preset inclination angle to form a buried connecting band; the doping type of the ions is the same as that of the polysilicon;

and removing the liner silicon oxide on the side wall around the groove area by adopting a wet etching mode, filling the deep groove with polysilicon for the second time, and removing the polysilicon on the surface of the liner nitride layer and part of polysilicon in the deep groove so that the depth between the upper surface of the polysilicon in the deep groove and the upper surface of the silicon device layer is smaller than or equal to a preset threshold value.

Optionally, fabricating a complementary metal oxide semiconductor CMOS circuit on the SOI wafer with the deep trenches, comprising:

manufacturing electronic devices and metal interconnections among the electronic devices required in the CMOS circuit on the SOI wafer with the deep trenches; the electronic device includes: metal oxide semiconductor field effect transistor MOSFET devices, capacitors, resistors; the metal interconnection includes: the semiconductor device comprises a silicon nitride insulating layer, a dielectric layer before metal deposition, a contact hole, an intermetallic dielectric layer, a metal layer and a through hole; metal interconnects are used to connect the electronic devices to electrically interconnect the electronic devices into a CMOS circuit.

Optionally, thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep trench filled with polysilicon, including:

temporarily bonding one side of the SOI wafer containing the CMOS circuit with a first carrier wafer, wherein the first carrier wafer is used for supporting the SOI wafer with the deep trenches;

thinning the supporting layer of the SOI wafer containing the CMOS circuit so that the thickness of the supporting layer is within a preset range;

removing the rest of the supporting layer and part of the polysilicon in the deep trench by adopting an etching process so as to form a groove with a preset depth range on the surface of the polysilicon in the deep trench and the surface of the buried oxide layer, wherein the etching process comprises the following steps: dry etching and wet etching; and the etching process has a greater etching rate for silicon than for silicon oxide.

Optionally, fabricating a memristor on the buried oxide layer of the SOI wafer includes:

manufacturing a lower electrode of the memristor in the groove;

manufacturing a resistance layer of the memristor on the buried oxide layer and the lower electrode of the memristor;

and manufacturing an upper electrode of the memristor above the resistance layer.

Optionally, fabricating a bottom electrode of the memristor in the recess includes:

depositing a metal layer with a preset thickness on the surface of the oxygen burying layer, wherein the material of the metal layer comprises the following components: iridium, palladium, gold, platinum, ruthenium; the deposition mode includes chemical vapor deposition, evaporation, sputtering and the like.

And removing the metal layer on the surface of the buried oxide layer by adopting an ion beam etching process, and only leaving the metal layer in the groove, wherein the metal layer in the groove forms a lower electrode of the memristor.

Optionally, fabricating a resistive layer of the memristor on the buried oxide layer and the lower electrode of the memristor includes:

depositing a resistor layer on the buried oxide layer, wherein the resistor layer comprises the following materials: metal oxides such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), zirconium oxide (ZrOx), scandium oxide (ScOx), oxygen Hua (YOx), nickel oxide (NiOx), tungsten oxide (WOx), and vanadium oxide (VOx);

and removing the resistance layer above the deep groove of the peripheral circuit region through photoetching and etching processes.

Optionally, fabricating an upper electrode of the memristor above the resistive layer includes:

depositing an upper electrode layer with a preset thickness on the resistor layer, wherein the upper electrode layer is made of the following materials: metals having a strong oxygen storage capacity such as tantalum (Ta), hafnium (Hf), titanium (Ti), tungsten (W), chromium (Cr), and nickel (Ni).

Optionally, after depositing the upper electrode layer with a preset thickness on the resistive layer, the method further includes:

depositing a conductive layer with preset thickness on the upper electrode layer, wherein the conductive layer comprises the following materials: aluminum, titanium, copper;

and depositing a silicon oxide dielectric layer on the surface of the conductive layer in a PECVD mode, and carrying out planarization treatment on the upper surface of the silicon oxide dielectric layer.

Optionally, after depositing a silicon oxide dielectric layer on the surface of the conductive layer in a PECVD manner and performing planarization treatment on the upper surface of the silicon oxide dielectric layer, the method further comprises:

temporarily bonding the upper surface of the silicon oxide dielectric layer with the second carrier wafer, and releasing the temporary bonding of the front surface of the SOI wafer containing the CMOS circuit with the first carrier wafer;

determining a target position of an aluminum bonding pad on one surface of the SOI wafer containing the CMOS circuit;

removing the dielectric layer on the target position through photoetching and etching processes until the metal layer below the dielectric layer is exposed;

manufacturing an aluminum bonding pad on the target position;

a passivation layer is arranged on one surface of the SOI wafer containing the CMOS circuit and the aluminum bonding pad;

and removing the passivation layer on the aluminum bonding pad to obtain a welding spot, wherein the welding spot is used for connecting an external circuit.

Optionally, after the upper electrode of the memristor is fabricated above the resistive layer, the method further includes:

determining a target position of an aluminum bonding pad to be arranged on the other surface of the SOI wafer containing the CMOS circuit;

forming an opening structure on the target position by adopting photoetching and etching processes, wherein the bottom of the opening structure reaches a metal layer of the CMOS circuit;

depositing a silicon oxide isolation layer on the other surface of the SOI wafer containing the CMOS circuit, the bottom surface of the opening structure and the side wall, wherein the silicon oxide isolation layer is used for isolating a silicon device layer;

removing the silicon oxide isolation layer on the surface of the upper electrode of the memristor and at the bottom of the opening structure by adopting photoetching and etching processes;

sequentially arranging a redistribution layer and a passivation layer on the other surface of the SOI wafer containing the CMOS circuit, the bottom surface of the opening structure and the side wall; wherein the material of the redistribution layer includes: aluminum;

and removing the passivation layer on the bottom surface of the opening structure to obtain welding spots, wherein the welding spots are used for connecting an external circuit.

sequentially growing a pad oxide layer, a pad nitride layer and a hard mask layer on the SOI wafer on the insulating layer;

Forming a deep trench on the SOI wafer by a reactive ion etching mode; the deep trench penetrates through the silicon device layer and the buried oxide layer of the SOI wafer and reaches the supporting layer;

filling the deep trench with polysilicon, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep trench to form a groove region between the upper surface of the polysilicon in the deep trench and the surface of the silicon device layer; the polysilicon in the deep trench is connected with one end of a common contact hole, one end of the common contact hole is also connected with a source electrode of a transistor in the CMOS circuit, and the other end of the common contact hole is connected with a metal layer of metal interconnection in the CMOS circuit.

In a second aspect, the present invention provides a resistance change memory manufactured by the method for manufacturing a resistance change memory according to any one of the first aspect, comprising: a storage unit and an access control unit;

The memory cell comprises a lower electrode, a resistor layer and an upper electrode, and the access control unit comprises a metal oxide semiconductor field effect transistor MOSFET; wherein:

the access control unit is manufactured on one surface of a silicon-on-insulator SOI wafer, the storage unit is manufactured on the other surface of the SOI wafer, and the access control unit is connected with the lower electrode of the storage unit through a deep groove filled with polysilicon on the SOI wafer.

Optionally, the bottom electrode of the memory cell is fabricated in a recess formed by the buried oxide layer of the SOI wafer and the deep trench, where the material of the bottom electrode includes: iridium, palladium, gold, platinum, ruthenium; the upper electrode layer comprises the following materials: metals having a strong oxygen storage capacity such as tantalum (Ta), hafnium (Hf), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni); the material of the resistance layer comprises: metal oxides such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), zirconium oxide (ZrOx), scandium oxide (ScOx), oxygen Hua (YOx), nickel oxide (NiOx), tungsten oxide (WOx), and vanadium oxide (VOx).

In a third aspect, the present invention provides a manufacturing apparatus of a resistance change type memory, comprising:

A memory for storing a program;

a processor for executing the program stored by the memory, the processor being for performing the method of any one of the first aspects when the program is executed.

In a fourth aspect, the present invention provides a computer-readable storage medium comprising: the instructions, when executed on a computer, cause the computer to perform the method of any of the first aspects.

According to the manufacturing method of the resistance change memory and the resistance change memory, the SOI wafer with the deep groove is obtained by arranging the deep groove filled with polysilicon on the SOI wafer of the silicon on the insulating layer; the deep trench penetrates through the silicon device layer and the buried oxide layer of the SOI wafer and reaches the supporting layer; manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon; and manufacturing a memristor on the buried oxide layer of the SOI wafer, wherein a lower electrode of the memristor is manufactured in the groove. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved. And the bottom electrode of the memristor is directly arranged in the deep trench, so that the area of the bottom electrode is determined by the size of the deep trench in the previous process, and a photomask and photoetching are not needed, thereby getting rid of the limitation of larger minimum line width of the photoetching process in the middle and later wafer processing factories, and being beneficial to realizing high-density storage.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.

FIG. 1 is a schematic diagram of an equivalent circuit of a resistance change memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a prior art resistance change memory;

FIG. 3 is a flowchart of a method for manufacturing a resistance change memory according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a silicon-on-insulator SOI wafer;

FIG. 5 is a schematic diagram of the structure of an SOI wafer with deep trenches;

FIG. 6 is a schematic diagram of the structure of an SOI wafer comprising CMOS circuits;

FIG. 7 is a schematic diagram of a structure in which a recess is formed at a top end position of a deep trench on the back surface of an SOI wafer;

FIG. 8 is a schematic diagram of a structure after the bottom electrode of the memristor is fabricated in the recess;

FIG. 9 is a schematic diagram of a structure after a resistive layer of a memristor is fabricated on a buried oxide layer;

FIG. 10 is a flowchart of a method for manufacturing a resistance change memory according to a second embodiment of the present invention;

FIG. 11 is a schematic diagram of a structure after the upper electrode of the memristor is fabricated on the resistive layer;

FIG. 12 is a schematic diagram of the structure after fabrication of an aluminum pad and passivation layer on one side of an SOI wafer containing CMOS circuitry;

FIG. 13 is a flowchart of a method for manufacturing a resistance change memory according to a third embodiment of the present invention;

FIG. 14 is a schematic diagram of the structure after fabrication of an aluminum pad and passivation layer on the other side of the SOI wafer containing the CMOS circuits;

FIG. 15 is a schematic diagram of a structure in which interconnections between transistors and memristors are made through common contact holes;

fig. 16 is a schematic structural diagram of a manufacturing apparatus of a resistance change memory according to a fourth embodiment of the present invention.

Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

In the following, some terms in the present application are explained for easy understanding by those skilled in the art.

1) The resistive random access memory (Resistive Random Access Memory, RRAM) is a nonvolatile (Non-volatile) memory which stores information by utilizing the variable resistance characteristic of materials, and has the advantages of low power consumption, high storage density, high read-write speed, strong repeated operation tolerance, long data retention time and the like.

2) Metal-Oxide-semiconductor field effect transistors (MOSFETs) are one of the most common devices in integrated circuits, and can be classified into N-channel type with majority of electrons and P-channel type with majority of holes, commonly referred to as N-type Metal Oxide semiconductor field effect transistors (NMOSFETs) and P-type Metal Oxide semiconductor field effect transistors (PMOSFETs), according to the polarity of the "channel".

3) Memristors, collectively known as memristors (memristors). Memristors have the dimension of resistance, but unlike resistance, the resistance of memristors is determined by the charge flowing through it. Therefore, by measuring the resistance of memristors, the amount of charge flowing through the memristors can be known, and the effect of memory charge is achieved. When the memristor is used as a storage unit, the working principle is as follows: when a direct current or pulse forward voltage is applied between the upper electrode and the lower electrode, conductive filaments (filaments) are formed in the resistor layer to present a low resistance state; when a direct current or pulse reverse voltage is applied, the conductive filaments in the resistive layer "break" to assume a high resistance state. This variable second-order resistance characteristic effectively enables the storage and switching of data "0" and "1".

4) Complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) refers to a technology used in the fabrication of large scale integrated circuit chips or chips fabricated using such technology.

Fig. 1 is an equivalent circuit schematic diagram of a resistance change memory according to an embodiment of the present invention, as shown in fig. 1, a mosfet 100 and a memristor 101 form a base unit 10 of an RRAM, wherein a drain of the mosfet 100 is connected to one end of the memristor 101, another end of the memristor 101 is grounded, a source of the mosfet 100 is connected to a Bit Line (BL) 111, and a gate of the mosfet 100 is connected to a Word Line (WL). The RRAM includes a plurality of base cells, and addressing of each base cell may be commonly defined by a Word Line (WL) 110 and a Bit Line (BL) 111.

Fig. 2 is a schematic diagram of a resistance change memory in the prior art, and as shown in fig. 2, a MOSFET is composed of a Substrate (Substrate) 12, a Source (Source) 122, a Drain (Drain) 121, a Gate dielectric layer (Gate) 123, a Gate (Gate) 124, and a sidewall (Spacer) 15. The drain 121 is electrically connected to the lower electrode 105 of the memristor 101 through a Contact hole (Contact) 16 and a metal 17. A resistance layer 106 is arranged between the lower electrode 105 and the upper electrode 107 of the memristor 101; the upper electrode 107 of the memristor 101 is connected to an external circuit through a Via (Via) 18, a metal 19. Because the memristors of the RRAM are positioned between interlayer metals (Inter-metal), the electrode material selection range of the memristors is narrow, and only materials compatible with a standard CMOS process can be used, so that the selectable range of the electrode material of the RRAM is limited, and the improvement of the electrical storage characteristics of the memristors is prevented.

The invention provides a manufacturing method of a resistance change type memory and the resistance change type memory, and aims to solve the technical problems in the prior art.

The following describes the technical scheme of the present invention and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present invention will be described below with reference to the accompanying drawings.

Fig. 3 is a flowchart of a method for manufacturing a resistance change memory according to an embodiment of the present invention, as shown in fig. 3, the method in the embodiment may include:

s101, arranging deep trenches filled with polysilicon on the SOI wafer on the insulating layer to obtain the SOI wafer with the deep trenches.

In this embodiment, a Silicon-On-Insulator (SOI) wafer may be used instead of a normal Silicon wafer as a substrate material of the RRAM. Fig. 4 is a schematic structural diagram of a SOI wafer on an insulating layer, as shown in fig. 4, the SOI wafer comprising: silicon device layer 30 (Silicon device layer), buried oxide layer 31 (Buried oxide) and Support layer 32 (Support layer), SOI wafer front side 300, SOI wafer back side 328. Specifically, an SOI wafer having a silicon thickness of 2.7 microns for the silicon device layer 30, a thickness of 0.2 microns for the buried oxide layer 31, and a thickness of 725 microns for the support layer 32 may be employed as the substrate material for the RRAM.

Fig. 5 is a schematic structural diagram of an SOI wafer with deep trenches, and as shown in fig. 5, a pad oxide layer 302, a pad nitride layer 303 and a hard mask layer are sequentially grown on the front surface 300 of the SOI wafer; the storage unit area is provided with a first deep trench 3401 penetrating through the SOI wafer silicon device layer 30 and the buried oxide layer 31 and reaching the support layer 32; a second deep trench 3402 penetrating the SOI wafer silicon device layer 30, the buried oxide layer 31, and reaching the support layer 32 is provided in the peripheral circuit region. A layer of Liner Oxide (Liner Oxide) 305 is arranged on the silicon surfaces of the first deep trench 3401 and the second deep trench 3402; and the first deep trench 3401 and the second deep trench 3402 are sequentially filled with the first layer of polysilicon 306 and the second layer of polysilicon 309. A buried strap 308 is also provided around the top of the first deep trench 3401. The upper surfaces of the second layer polysilicon 309 of the first and second

deep trenches

3401, 3402 are level-different from the upper surface 300 of the silicon device layer 30, thereby forming a recess 310.

Optionally, referring to fig. 5, in this embodiment, a Pad oxide layer (Pad oxide), a Pad Nitride layer (Pad Nitride), and a Hard mask layer (Hard mask) may be sequentially grown on a silicon-on-insulator SOI wafer; forming deep trenches on an SOI wafer by means of reactive ion etching (Reactive Ion Etch, RIE), the deep trenches comprising: a memory cell region deep trench and a peripheral circuit region deep trench (corresponding to the first deep trench 3401 and the second deep trench 3402 in fig. 5, respectively); the deep trenches of the storage unit region and the deep trenches of the peripheral circuit region penetrate through the silicon device layer and the buried oxide layer of the SOI wafer and reach the supporting layer. Removing the hard mask layer of the SOI wafer with the deep groove by adopting a wet etching mode, and performing thermal oxidation on the SOI wafer with the deep groove to form a layer of pad silicon oxide with preset thickness on the silicon surface of the deep groove; filling the deep trench with polysilicon for the first time, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep trench to form a groove region between the upper surface of the polysilicon in the deep trench and the surface of the silicon device layer; performing high-energy ion implantation around the groove area according to a preset inclination angle to form a buried connecting band; the doping type of the ions is the same as that of the polysilicon; and removing the liner silicon oxide on the side wall around the groove region by adopting a wet etching mode, filling the deep groove with polysilicon for the second time, and removing the polysilicon on the surface of the liner nitride layer and part of polysilicon in the deep groove so that the depth between the upper surface of the groove region in the deep groove and the upper surface of the silicon device layer is smaller than or equal to a preset threshold value.

Specifically, taking fig. 5 as an example, the first deep trench 3401 may be provided to have a width of 0.3 micrometers, a depth of 3 micrometers, and an aspect ratio of 10:1. It should be noted that the depth of the first deep trench 3401 and the second deep trench 3402 reaching the supporting layer 32 is not more than 0.2 micrometers. The hard mask layer is etched by wet etching, and then the SOI wafer is put into a high temperature furnace for thermal oxidation at a temperature ranging from 800 ℃ to 1100 ℃ to form a layer of pad silicon oxide 305 with a thickness of 20 nanometers on the silicon surface of the deep trench. The doped first layer of polysilicon 306 is filled using a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process. Doping can reduce the resistivity of polysilicon and improve the conductivity. And then removing the redundant polysilicon on the surface of the pad nitride layer 303 by adopting Chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP) and etching back (Etch back), and forming a groove (process) on the polysilicon in the deep groove, wherein the depth of the groove is about 120 nanometers from the front surface 300 of the SOI wafer. High energy ion implantation is performed around the recess at an angle of 15 degrees from the normal to the SOI wafer to form buried strap 308, with the implanted ions being n-type dopants and the doping profile of the polysilicon and drain. The silicon oxide surrounding the recess is then removed by wet etching to remove the barrier to carrier migration. The LPCVD process is adopted to fill the doped second layer of polysilicon 309 again, and then the superfluous polysilicon on the surface of the pad nitride layer 303 is removed by adopting the CMP and back etching modes, so that the depth of the groove 310 from the silicon surface 300 after the second back etching is controlled to be not more than 50 nanometers.

Optionally, a pad oxide layer, a pad nitride layer and a hard mask layer can be sequentially grown on the SOI wafer; forming deep trenches on the front side of the SOI wafer in a reactive ion etching mode; removing the hard mask layer of the SOI wafer with the deep groove by adopting a wet etching mode, and performing thermal oxidation on the SOI wafer with the deep groove to form a layer of pad silicon oxide with preset thickness on the silicon surface of the deep groove; filling the deep trench with polysilicon, and removing the polysilicon on the surface of the pad nitride layer and part of the polysilicon in the deep trench to form a groove region between the surface of the polysilicon in the deep trench and the surface of the silicon device layer; the polysilicon in the deep trench is connected with one end of a common contact hole, one end of the common contact hole is also connected with a source electrode of a transistor in the CMOS circuit, and the other end of the common contact hole is connected with a metal layer of metal interconnection in the CMOS circuit.

Specifically, fig. 15 is a schematic structural diagram of interconnection between a transistor and a memristor through a common contact hole. As shown in fig. 15, the common contact hole 601 is simultaneously in contact connection with the first deep trench and the transistor source 314. By using the method, the manufacturing process of the polysilicon deep trench can be simplified, and the processes of double polysilicon filling, ion implantation and the like are not needed.

S102, manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove, and obtaining the SOI wafer containing the CMOS circuit.

In this embodiment, electronic devices required in the CMOS circuit and metal interconnections between the electronic devices may be fabricated on the SOI wafer with the deep trenches; the electronic device includes: metal oxide semiconductor field effect transistor MOSFET devices, capacitors, resistors; the metal interconnection includes: the semiconductor device comprises a silicon nitride insulating layer, a dielectric layer before metal deposition, a contact hole, an intermetallic dielectric layer, a metal layer and a through hole; metal interconnects are used to connect the electronic devices to electrically interconnect the electronic devices into a CMOS circuit. A specific CMOS circuit structure may be referred to in fig. 6.

Fig. 6 is a schematic structural diagram of an SOI wafer including CMOS circuitry, as shown in fig. 6, where fig. 6 shows the structure of two N-type MOSFETs comprising: p-well 312, source 313, drain 314, gate dielectric 315, gate 316, sidewall (Spacer) 317, and shallow trench isolation (Shallow Trench Isolation, STI) 311 for isolating adjacent transistors are formed in silicon device layer 30. The P-type MOSFET structure is similar to the N-type, except that the dopants are different. After finishing the manufacture of devices such as MOSFETs, the manufacture of metal interconnections comprises the following steps: a silicon nitride insulating layer 318, a dielectric layer (Pre Metal Dielectrics, PMD) 320 before metal deposition, a Contact 321, an inter-metal dielectric layer (Inter Metal Dielectrics, IMD) 330, a metal layer 331 and a via layer 332. The metal interconnect functions to connect the transistors together to form a complete circuit. The remaining metal materials are mainly aluminum (Al) or copper (Cu) except for tungsten (W) for the contact hole. In this embodiment, the interlayer metal is copper. Since the process of forming both MOSFET devices and metal interconnects is well known in the art, it will not be described in detail herein.

S103, thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon.

In this embodiment, one surface of the SOI wafer including the CMOS circuit may be temporarily bonded to a first carrier wafer, where the first carrier wafer is used to support the SOI wafer with the deep trench; thinning the supporting layer of the SOI wafer containing the CMOS circuit so that the thickness of the supporting layer is within a preset range; removing the rest part of the supporting layer by adopting an etching process, and forming a groove with a preset depth range at the top end position of the deep groove filled with the polysilicon, wherein the etching process comprises the following steps: dry etching and wet etching; and the etching process has a greater etching rate for silicon than for silicon oxide. Specifically, the structure after forming the groove at the top end position of the deep trench can refer to fig. 7.

Fig. 7 is a schematic structural diagram of forming a recess at a top end position of a deep trench on a back surface of an SOI wafer, and as shown in fig. 7, a front surface 341 of the SOI wafer including a CMOS circuit is temporarily bonded to a first Carrier wafer 340, and the first Carrier wafer 340 plays a supporting role in the thinning process of the SOI wafer supporting layer 32. A recess 352 is formed by an etching process at a top end position of the deep trench on the back side of the SOI wafer. Wherein the recess 352 is formed by a difference in height between the top surface of the polysilicon within the deep trench and the upper surface 351 of the buried oxide layer 31.

The specific process can be carried out in two stages: the first stage is to thin the thickness of SOI wafer support layer 32 from 725 microns to around 20 microns using standard thinning processes including rough grinding, finish grinding, polishing, etc. The second stage removes all of the remaining silicon of the support layer 32 by an etching process to reach the buried oxide layer surface 351. The etching mode can be dry etching or wet etching, and the etching selectivity ratio of silicon to silicon oxide is required to be larger. This example uses a dry etching process with a selectivity ratio of 10:1, i.e., silicon etching rate 10 times that of silicon oxide. After etching, a groove 352 is formed at the top of the polysilicon deep groove, and the depth of the groove is 20-50 nanometers.

S104, manufacturing a memristor on the buried oxide layer of the SOI wafer, wherein a lower electrode of the memristor is manufactured in the groove.

In this embodiment, a metal layer with a preset thickness may be deposited on the surface of the oxygen-buried layer, and then an ion beam etching process is used to remove the metal layer on the surface of the oxygen-buried layer, and only the metal layer in the groove is left, where the metal layer in the groove forms the lower electrode of the memristor. Wherein, the material of metal layer includes: iridium, palladium, gold, platinum, ruthenium, and the like. The deposition mode includes chemical vapor deposition, evaporation, sputtering and the like.

It should be noted that noble metals such as iridium, palladium, gold, platinum, ruthenium, etc. have higher work functions, but are not generally used in previous wafer processing plants due to potential metal contamination issues that are incompatible with standard CMOS processes. Therefore, step S104 in this embodiment is performed in the middle and later wafer processing factories. Fig. 8 is a schematic structural diagram of a memristor after the bottom electrode is fabricated in the recess, in fig. 8, taking Metal platinum as an example, platinum triacetylacetone is used as a precursor, and a layer of platinum with a thickness of 30 nm is deposited on the upper surface 351 of the oxygen-buried layer 31 by a Metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD) process. Alternatively, platinum may also be deposited using an evaporation or sputtering process. The platinum on the upper surface 351 of the buried oxide layer 31 is then removed directly with an Ion Beam Etch (IBE) process without a masking process, leaving only the platinum electrode 353 within the recess.

In this embodiment, since the bottom electrode of the memristor is directly formed in the groove, the size of the electrode area depends on the deep groove size in the previous process, unlike the conventional process which needs to define the electrode area by photolithography, so that the size limitation of the photolithography process of the middle and subsequent wafer processing factories is eliminated, and the high-density storage is facilitated.

In this embodiment, a resistive layer may be deposited on the buried oxide layer, and then the resistive layer above the deep trench in the peripheral circuit region may be removed by photolithography and etching processes. The material of the resistance layer comprises: metal oxides such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), zirconium oxide (ZrOx), scandium oxide (ScOx), oxygen Hua (YOx), nickel oxide (NiOx), tungsten oxide (WOx), and vanadium oxide (VOx). Specific structure may refer to fig. 9, and fig. 9 is a schematic structural diagram of a memristor after a resistor layer is fabricated on a buried oxide layer. First, a resistive layer 354 is deposited on the surface 351 of the buried oxide layer 31, and the resistive layer above the second deep trench 3402 is removed by a photolithography (etching) process. In this embodiment, the resistive layer material is oxidized (HfOx) and then prepared by an atomic layer deposition (Atomic layer deposition, ALD) process, with a thickness of 3-10 nm.

In this embodiment, an upper electrode layer with a preset thickness may be deposited on the resistive layer, where materials of the upper electrode layer include: metals having a strong oxygen storage capacity such as tantalum (Ta), hafnium (Hf), titanium (Ti), tungsten (W), chromium (Cr), and nickel (Ni).

In the embodiment, a deep trench filled with polysilicon is arranged on the front surface of a silicon-on-insulator SOI wafer to obtain the SOI wafer with the deep trench; manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the front surface of the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning the back of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon; manufacturing a lower electrode of the memristor in the groove; manufacturing a resistance layer of the memristor on the buried oxide layer; and manufacturing an upper electrode of the memristor above the resistance layer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved. And the bottom electrode of the memristor is directly arranged in the deep trench, so that the area of the bottom electrode is determined by the size of the deep trench in the previous process, and a photomask and photoetching are not needed, thereby getting rid of the limitation of larger minimum line width of the photoetching process in the middle and later wafer processing factories, and being beneficial to realizing high-density storage.

Fig. 10 is a flowchart of a method for manufacturing a resistance change memory according to a second embodiment of the present invention, as shown in fig. 10, the method in this embodiment may include:

s201, arranging deep trenches filled with polysilicon on a silicon-on-insulator SOI wafer to obtain an SOI wafer with the deep trenches;

s202, manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit;

s203, thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon;

s204, manufacturing a lower electrode of the memristor in the groove;

s205, manufacturing a resistance layer of the memristor on the buried oxide layer;

s206, manufacturing an upper electrode of the memristor above the resistance layer.

In this embodiment, the specific implementation process and principle of step S201 to step S206 are described in the related description of the method shown in fig. 1, and are not repeated here.

S207, depositing a conductive layer with a preset thickness on the upper electrode layer.

In this embodiment, when the upper electrode is made of tantalum (Ta), because the resistivity of tantalum is high, the tantalum is directly used as the conductive line to generate a large signal delay, so that a layer of low-resistivity material needs to be deposited on top of the tantalum as the conductive layer. Therefore, aluminum (Al) can be used as the material of the conductive layer 363, with a thickness of 200 nm, which is also prepared by a sputtering process, and the pattern of the upper electrode and the conductive layer above it is obtained once through photolithography and etching processes. Referring to fig. 11, fig. 11 is a schematic diagram of a structure of a resistor layer after the upper electrode of the memristor is fabricated.

And S208, depositing a silicon oxide dielectric layer on the surface of the conductive layer in a PECVD mode, and carrying out flattening treatment on the upper surface of the silicon oxide dielectric layer.

In this embodiment, a silicon oxide dielectric layer 364 may be deposited on the aluminum surface by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and a planar silicon oxide dielectric layer surface 361 may be obtained after CMP. The memristor 350 of the Pt-HfOx-Ta structure has been fabricated so far.

S209, manufacturing an aluminum bonding pad and a passivation layer on one surface of the SOI wafer containing the CMOS circuit.

In this embodiment, the upper surface of the silicon oxide dielectric layer may be bonded to the second carrier wafer, and the front surface of the SOI wafer including the CMOS circuit may be temporarily bonded to the first carrier wafer; determining a target position of an aluminum bonding pad to be arranged on the front surface of the SOI wafer containing the CMOS circuit; removing the dielectric layer on the target position through photoetching and etching processes until the metal layer below the dielectric layer is exposed; manufacturing an aluminum bonding pad on the target position; a passivation layer is arranged on the front surface of the SOI wafer containing the CMOS circuit and the aluminum welding disk; and removing the passivation layer on the aluminum bonding pad to obtain a welding spot, wherein the welding spot is used for connecting an external circuit.

Fig. 12 is a schematic diagram of the structure after aluminum pads and passivation layers are fabricated on one side of an SOI wafer containing CMOS circuitry. The silicon oxide dielectric layer surface 361 is bonded to the second carrier wafer 360 and then the first carrier wafer 340 is de-bonded. And the front side 341 of the SOI wafer containing the CMOS circuitry is brought up. The dielectric material at specific locations on the front side 341 of the SOI wafer containing the CMOS circuitry is removed by photolithography and etching processes, exposing the underlying metal layer 331. An aluminum Pad (Al Pad) 370 and a Passivation layer (Passivation) 372 are then formed on the front side 341 of the SOI wafer containing the CMOS circuitry, and a Window 371 (Pad Window Open) is formed in the aluminum Pad for connection to an external power source, signal or ground. Since the process of aluminum pad and passivation layer window formation is conventional, it will not be described in detail herein.

In the embodiment, a deep trench filled with polysilicon is arranged on a silicon-on-insulator SOI wafer to obtain the SOI wafer with the deep trench; manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the front surface of the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning the back of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon; manufacturing a lower electrode of the memristor in the groove; manufacturing a resistance layer of the memristor on the buried oxide layer; and manufacturing an upper electrode of the memristor above the resistance layer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved. And the bottom electrode of the memristor is directly arranged in the deep trench, so that the area of the bottom electrode is determined by the size of the deep trench in the previous process, and a photomask and photoetching are not needed, thereby getting rid of the limitation of larger minimum line width of the photoetching process in the middle and later wafer processing factories, and being beneficial to realizing high-density storage.

Fig. 13 is a flowchart of a method for manufacturing a resistance change memory according to a third embodiment of the present invention, as shown in fig. 13, the method in this embodiment may include:

s301, arranging deep trenches filled with polysilicon on a silicon-on-insulator SOI wafer to obtain an SOI wafer with the deep trenches;

s302, manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit;

s303, thinning the supporting layer of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon;

s304, manufacturing a lower electrode of the memristor in the groove;

s305, manufacturing a resistance layer of the memristor on the buried oxide layer;

s306, manufacturing an upper electrode of the memristor above the resistance layer.

In this embodiment, for the specific implementation process and principle of step S301 to step S306, please refer to the related description of the method shown in fig. 1, and the detailed description is omitted here.

S307, manufacturing an aluminum bonding pad and a passivation layer on the other surface of the SOI wafer containing the CMOS circuit.

In this embodiment, the target position where the aluminum pad needs to be disposed on the other surface of the SOI wafer containing the CMOS circuit may be determined first; forming an opening structure on the target position by adopting photoetching and etching processes, wherein the bottom of the opening structure reaches a metal layer of the CMOS circuit; depositing a silicon oxide isolation layer on the back surface, the bottom surface of the opening structure and the side wall of the SOI wafer containing the CMOS circuit, wherein the silicon oxide isolation layer is used for isolating a silicon device layer; removing the silicon oxide isolation layer on the surface of the upper electrode of the memristor and at the bottom of the opening structure by adopting photoetching and etching processes; sequentially arranging a redistribution layer and a passivation layer on the back surface of the SOI wafer containing the CMOS circuit, the bottom surface of the opening structure and the side wall; wherein the material of the redistribution layer includes: aluminum; and removing the passivation layer on the bottom surface of the opening structure to obtain welding spots, wherein the welding spots are used for connecting an external circuit.

Fig. 14 is a schematic structural diagram of an aluminum pad and passivation layer fabricated on the other side of an SOI wafer containing CMOS circuitry. Specifically, interconnection of the memristor upper electrode 355 and the metal layer 331 may be achieved by digging out the silicon device layer 30 of the peripheral circuit region, without providing the second deep trench 3402 like in the peripheral circuit region. In addition, aluminum pads 404 are also formed on the back side of the SOI wafer, which has the advantage that one bonding process can be omitted. After the fabrication of the memristor upper electrode 355 is completed, the opening structure 400 needs to be formed at a specific position of the peripheral circuit through photolithography and etching processes, so that the metal layer 331 is exposed. A silicon oxide Isolation layer (Isolation layer) 401 is then deposited, 300 nm thick, to isolate the silicon device layer 30 from a redistribution layer (RDL) 402.

Optionally, to ensure electrical connection, the silicon oxide isolation layer 401 is removed in the area of the opening structure 400 and the area of the memristor upper electrode 355 by a photolithographic and etching process. Finally, a redistribution layer 402 and a Passivation layer (Passivation) 403 are fabricated, and a Window 404 (Pad Window Open) is formed. The material of the redistribution layer 402 is aluminum, with a thickness of 800 nm, and the redistribution layer 402 may be used as a conductive layer over the memristor upper electrode 355, or may be used as an aluminum pad (Al pad) to connect to an external power source, signal, or ground.

In the embodiment, a deep trench filled with polysilicon is arranged on the front surface of a silicon-on-insulator SOI wafer to obtain the SOI wafer with the deep trench; manufacturing a Complementary Metal Oxide Semiconductor (CMOS) circuit on the front surface of the SOI wafer with the deep groove to obtain the SOI wafer containing the CMOS circuit; thinning the back of the SOI wafer containing the CMOS circuit to the surface of the buried oxide layer, and forming a groove at the top end of the deep groove filled with the polysilicon; manufacturing a lower electrode of the memristor in the groove; manufacturing a resistance layer of the memristor on the buried oxide layer; and manufacturing an upper electrode of the memristor above the resistance layer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved. And the bottom electrode of the memristor is directly arranged in the deep trench, so that the area of the bottom electrode is determined by the size of the deep trench in the previous process, and a photomask and photoetching are not needed, thereby getting rid of the limitation of larger minimum line width of the photoetching process in the middle and later wafer processing factories, and being beneficial to realizing high-density storage. Interconnection of the upper electrode of the memristor and the metal layer can be achieved by digging out a silicon device layer of the peripheral circuit region, and processing steps are simplified.

The invention also provides a resistance change type memory manufactured by the method of any one of the figures 3, 10 and 13, comprising the following steps: a storage unit and an access control unit; the memory cell comprises a lower electrode, a resistor layer and an upper electrode, and the access control unit comprises a metal oxide semiconductor field effect transistor MOSFET; wherein: the access control unit is manufactured on one surface of a silicon-on-insulator SOI wafer, the storage unit is manufactured on the other surface of the SOI wafer, and the access control unit is connected with the lower electrode of the storage unit through a deep groove filled with polysilicon on the SOI wafer.

Optionally, the bottom electrode of the memory cell is fabricated in a recess formed by the buried oxide layer of the SOI wafer and the deep trench, where the material of the bottom electrode includes: iridium, palladium, gold, platinum, ruthenium; the upper electrode layer comprises the following materials: metals having a strong oxygen storage capacity such as tantalum (Ta), hafnium (Hf), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), etc.; the material of the resistance layer comprises: metal oxides such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), niobium oxide (NbOx), zirconium oxide (ZrOx), scandium oxide (ScOx), oxygen Hua (YOx), nickel oxide (NiOx), tungsten oxide (WOx), and vanadium oxide (VOx).

In this embodiment, an access control unit is disposed on the front surface of a silicon-on-insulator SOI wafer, and a memory cell is fabricated on the back surface of the SOI wafer, and the access control unit is connected to the lower electrode of the memory cell through a deep trench filled with polysilicon on the front surface of the SOI wafer. Therefore, the separation of the RRAM standard CMOS circuit manufacturing process and the memristor manufacturing process is realized, and noble metal is introduced to serve as an electrode of the memristor in the large-scale production process of the RRAM, so that the electrical storage characteristic of the memristor in the RRAM is improved. And the bottom electrode of the memristor is directly arranged in the deep trench, so that the area of the bottom electrode is determined by the size of the deep trench in the previous process, and a photomask and photoetching are not needed, thereby getting rid of the limitation of larger minimum line width of the photoetching process in the middle and later wafer processing factories, and being beneficial to realizing high-density storage.

Fig. 16 is a schematic structural diagram of an apparatus for manufacturing a resistance change memory according to a fourth embodiment of the present invention, and as shown in fig. 16, an apparatus 50 for manufacturing a resistance change memory according to the present embodiment includes:

a processor 51 and a memory 52; wherein:

the memory 52 is used for storing executable instructions, and may also be a flash memory.

A processor 51 for executing executable instructions stored in a memory to implement the steps of the method according to the above-described embodiments. Reference may be made in particular to the description of the embodiments of the method described above.

Alternatively, the memory 52 may be separate or integrated with the processor 51.

When the memory 52 is a device independent from the processor 51, the manufacturing apparatus 50 of a resistance change type memory may further include:

a bus 53 for connecting the memory 52 and the processor 51.

In addition, the embodiment of the application further provides a computer-readable storage medium, in which computer-executable instructions are stored, when the at least one processor of the user equipment executes the computer-executable instructions, the user equipment performs the above possible methods.

Among them, computer-readable media include computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In addition, the application specific integrated circuit may be located in the user equipment. The processor and the storage medium may reside as discrete components in a communication device.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: read Only Memory (ROM), random Access Memory (RAM), magnetic or optical disks, and the like.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method of manufacturing a resistance change type memory, comprising:

2. The method of claim 1, wherein disposing deep trenches filled with polysilicon on a silicon-on-insulator SOI wafer results in a SOI wafer with deep trenches, comprising:

3. The method of claim 1, wherein fabricating complementary metal oxide semiconductor CMOS circuitry on the SOI wafer with deep trenches comprises:

4. The method of claim 1, wherein thinning the support layer of the SOI wafer comprising CMOS circuitry to the surface of the buried oxide layer and forming a recess at a top location of the deep trench filled with polysilicon comprises:

5. The method of claim 1, wherein fabricating a memristor on the buried oxide layer of the SOI wafer comprises:

manufacturing a lower electrode of the memristor in the groove;

6. The method of claim 5, wherein fabricating a lower electrode of a memristor within the recess comprises:

depositing a metal layer with a preset thickness on the surface of the oxygen burying layer, wherein the material of the metal layer comprises the following components: iridium, palladium, gold, platinum, ruthenium; the deposition method comprises the following steps: chemical vapor deposition, evaporation and sputtering;

7. The method of claim 5, wherein fabricating a resistive layer of the memristor on the buried oxide layer and a lower electrode of the memristor comprises:

depositing a resistor layer on the buried oxide layer, wherein the resistor layer comprises the following materials: hafnium oxide HfOx, titanium oxide TiOx, tantalum oxide TaOx, niobium oxide NbOx, zirconium oxide ZrOx, scandium oxide ScOx, yttrium oxide YOx, nickel oxide NiOx, tungsten oxide WOx, vanadium oxide VOx;

8. The method of claim 5, wherein fabricating an upper electrode of a memristor over the resistive layer comprises:

depositing an upper electrode layer with a preset thickness on the resistor layer, wherein the upper electrode layer is made of the following materials: tantalum Ta, hafnium Hf, titanium Ti, tungsten W, chromium Cr, nickel Ni.

9. The method of claim 8, further comprising, after depositing an upper electrode layer of a predetermined thickness on the resistive layer:

10. The method of claim 9, further comprising, after depositing a silicon oxide dielectric layer on the surface of the conductive layer by PECVD and planarizing the upper surface of the silicon oxide dielectric layer:

bonding the upper surface of the silicon oxide dielectric layer with a second carrier wafer, and removing the temporary bonding between the front surface of the SOI wafer containing the CMOS circuit and the first carrier wafer;

manufacturing an aluminum bonding pad on the target position;

11. The method of claim 5, further comprising, after fabricating an upper electrode of a memristor over the resistive layer:

12. The method of claim 1, wherein disposing deep trenches filled with polysilicon on a silicon-on-insulator SOI wafer results in a SOI wafer with deep trenches, comprising:

13. A resistance change memory, characterized by being manufactured by applying the manufacturing method of the resistance change memory according to any one of claims 1 to 12, comprising: a storage unit and an access control unit;

14. The resistance change memory according to claim 13, wherein a lower electrode of the memory cell is formed in a recess formed by the buried oxide layer of the SOI wafer and the deep trench, wherein a material of the lower electrode comprises: iridium, palladium, gold, platinum, ruthenium; the upper electrode layer comprises the following materials: tantalum Ta, hafnium Hf, titanium Ti, tungsten W, chromium Cr, nickel Ni; the material of the resistance layer comprises: hafnium oxide HfOx, titanium oxide TiOx, tantalum oxide TaOx, niobium oxide NbOx, zirconium oxide ZrOx, scandium oxide ScOx, yttrium oxide YOx, nickel oxide NiOx, tungsten oxide WOx, vanadium oxide VOx.