KR20080050099A - Phase change ram device and method of manufacturing the same - Google Patents

Abstract

A phase change memory device and a method for manufacturing the same are provided to lower an operation voltage of the phase change memory device by forming a buried common source line in a trench of a semiconductor substrate. An isolation layer(201) is formed in a surface of a semiconductor substrate(200). A trench is formed on a common source formation region of a semiconductor substrate. A buried common source line(203) is formed in the trench. A gate(204) is arranged on the substrate and formed between the buried common source lines. A drain(202b) is formed so that a transistor is formed in the substrate surface at a side of the gate on which the buried common source line is not formed. A first interlayer dielectric(291) is formed on the substrate to cover the transistor. A lower electrode(207) includes a contact plug(206) which is configured to contact to the drain in the first interlayer dielectric. A second interlayer dielectric(292) is formed on the first interlayer dielectric to cover the lower electrode. A lower electrode contact(208) is contacted to the lower electrode in the second interlayer dielectric. A phase change layer(209) and an upper electrode(210) are laminated on the lower electrode contact. A third interlayer dielectric(293) is formed on the second interlayer dielectric to cover the upper electrode and the phase change layer. An upper electrode contact(211) is formed to be contacted to the upper electrode in the third interlayer dielectric. A bit line(212) is formed on the third interlayer dielectric including the upper electrode contact.

Description

Phase change RAM device and method of manufacturing the same

1 is a photograph showing a phase change memory device according to the prior art.

2 is a cross-sectional view showing a phase change memory device according to an embodiment of the present invention.

3A to 3G are cross-sectional views illustrating processes for manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200,300: semiconductor substrate 201,301: device isolation film

202a and 302a impurity doped region 202b and 302b drain

203,303: buried common source line 204,304: gate

205,305: spacer 206,306: contact plug

207,307: lower electrode 208,308: lower electrode contact

209, 309: phase change film 210, 310: upper electrode

211,311: Upper electrode contact 212,312: Bit line

291,391: first interlayer insulating film 292,393: second interlayer insulating film

293,393: third interlayer insulating film H1: first contact hole

H2: 2nd contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory element and a method for manufacturing the same, and more particularly, to a phase change memory element capable of increasing the amount of current between a drain and a source, and a manufacturing method thereof.

Generally, a memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a ROM that keeps the input data stored even when the power is cut off. ) Are largely divided into elements. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased.

In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies have been conducted to develop new memory devices having the characteristics of the nonvolatile memory device and having a simple structure. For example, a phase change memory device has recently been developed. RAM) has been proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information.

In other words, the phase-conversion memory device uses a chalcogenide film as a phase-conversion film, which is a compound film composed of germanium (Ge), stevidium (Sb), and tellurium (Te). GST film), a phase change occurs between an amorphous state and a crystalline state by an applied current, that is, Joule heat, wherein the resistivity of the phase change film having an amorphous state is in a crystalline state. Since it is higher than the specific resistance of the phase change film having a value, the current flowing through the phase change film in the read mode is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

On the other hand, in the phase change memory device, since a current flow is required to be 1 ㎃ or more for the phase change of the GST film, the current required for the phase change of the GST film must be reduced by reducing the contact area between the GST film and the electrode.

1 is a view illustrating a structure of a conventional phase change memory device, in which gates are formed on a semiconductor substrate, and sources / drains are formed in the substrate surfaces on both sides of the gate. Contact plugs are formed on the source / drain, respectively.

A lower electrode is formed on the contact plug formed on the drain of the substrate, and a common source line is formed on the contact plug formed on the source of the substrate.

A bottom electrode contact is formed on the lower electrode, and a GST film and an upper electrode are stacked on the lower electrode contact.

A top electrode contact is formed on the upper electrode, and a bit line is formed on the upper electrode.

On the other hand, as described above, in the conventional phase change memory device, a contact plug is formed on the source of the substrate to electrically connect with the lower electrode. As the size of the chip decreases, the contact plug becomes smaller. As a result, the contact area between the contact plug and the source becomes smaller, resulting in higher contact resistance.

This increase in contact resistance decreases the amount of current flowing from the drain to the source, resulting in unstable phase change while lowering Joule heat between the lower electrode contact and the phase change film.

An object of the present invention is to provide a phase change memory device capable of increasing the amount of current flowing from a drain to a source, and a method of manufacturing the same.

In order to achieve the above object, the present invention is a semiconductor substrate provided with a device isolation film in the surface, the trench formed in the common source line forming region; A buried common source line formed in said trench; A gate disposed on the substrate and formed between the buried common source lines; A drain formed to form a transistor in the substrate surface on the side of the gate where the buried common source line is not formed; A first interlayer insulating film formed on the substrate so as to cover the transistor; A lower electrode including a contact plug formed to contact the drain in the first interlayer insulating film; A second interlayer insulating film formed on the first interlayer insulating film to cover the lower electrode; A lower electrode contact formed to contact the lower electrode in the second interlayer insulating film; A phase conversion layer and an upper electrode stacked on the lower electrode contact; A third interlayer dielectric layer formed on the second interlayer dielectric layer to cover an upper electrode and a phase change layer; An upper electrode contact formed in contact with the upper electrode in the third interlayer insulating film; And a bit line formed on the third interlayer insulating layer including the upper electrode contact.

The semiconductor device may further include an impurity doped region formed inside the trench surface on which the buried common source line is formed.

The buried common source line may include a shallower depth than the device isolation layer.

The buried common source line includes one made of an aluminum film, a tungsten film, a copper film, a titanium nitride film, and a titanium tungsten film.

The gate includes one formed to overlap the buried common source line.

The lower electrode including the contact plug includes one formed by a dual damascene process.

And a metal line including a metal plug formed to contact the buried common source line in the first interlayer insulating layer.

In addition, the present invention includes the steps of providing a semiconductor substrate having a device isolation film in the surface, the trench formed in the common source line forming region; Forming a buried common source line in the trench; Forming a gate on a substrate on the buried common source line; Performing impurity ion implantation on the substrate on which the buried common source line is not formed to form a drain such that a transistor is formed in the substrate surface on the side of the gate; Forming a first interlayer insulating film on the substrate so as to cover the transistor; Forming a contact plug in the first interlayer dielectric layer to contact the drain and forming a lower electrode; Forming a second interlayer insulating film on the first interlayer insulating film to cover the lower electrode; Etching the second interlayer insulating layer to form a first contact hole exposing a lower electrode; Forming a lower electrode contact in contact with the lower electrode in the first contact hole; Forming a phase conversion film and an upper electrode on the lower electrode contact; Forming a third interlayer dielectric layer on the second interlayer dielectric layer to cover an upper electrode and a phase change layer; Etching the third interlayer insulating layer to form a second contact hole exposing an upper electrode; Forming an upper electrode contact in contact with the upper electrode in the second contact hole; And forming a bit line on the third interlayer insulating film including the upper electrode contact.

Here, after preparing the trench-formed semiconductor substrate, prior to forming the buried common source line, impurity ion implantation is performed on the substrate on which the trench is formed to form an impurity doped region inside the trench surface. It further includes;

The buried common source line may include forming a shallower depth than the device isolation layer.

The buried common source line includes forming one of an aluminum film, a tungsten film, a copper film, a titanium nitride film, and a titanium tungsten film.

The gate includes forming overlapping with the buried common source line.

The contact plug and the lower electrode in contact with the drain in the first interlayer insulating layer may be formed by a dual damascene process.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a phase change memory device according to an embodiment of the present invention.

As illustrated, the phase change memory device of the present invention includes a semiconductor substrate 200 having a device isolation film 201 in its surface, and having a trench formed in a common source line forming region, and a buried common source line formed in the trench. a substrate on the side of the gate 204 formed on the buried common soure line 203, the gate 204 formed between the buried common source line 203, and the buried common source line 204 not formed. A drain 202b formed to form a transistor in the surface, a first interlayer insulating film 291 formed on a substrate to cover the transistor, and a contact plug formed to contact the drain 202b in the first interlayer insulating film 291. A lower electrode 207 including 206, a second interlayer insulating film 292 formed on the first interlayer insulating film 291 to cover the lower electrode 207, and a lower portion in the second interlayer insulating film 292. Electrode 207 ), A bottom electrode contact 208 formed to contact the bottom electrode, a phase conversion film 209 and an upper electrode 210 stacked on the bottom electrode contact 208, and an upper electrode on the second interlayer insulating film 292. A third interlayer insulating film 293 formed to cover the 210 and the phase change film 209, an upper electrode contact 211 formed to contact the upper electrode 210 in the third interlayer insulating film 293, and the And a bit line 212 formed on the third interlayer insulating film 293 including the upper electrode contact 211.

The impurity doped region 202a is formed inside the trench surface on which the buried common source line 203 is formed.

The buried common source line 203 is formed to be shallower than the device isolation layer 201, and the buried common source line 203 is formed of any one of an aluminum film, a tungsten film, a copper film, a titanium nitride film, and a titanium tungsten film. Done in one.

The lower electrode 207 including the contact plug 206 is formed by a dual damascene process.

Unexplained reference numeral 205 denotes a spacer.

As described above, in the phase change memory device of the present invention, a buried common source line is formed in the source of the semiconductor substrate, thereby reducing the resistance of the source, thereby reducing the resistance of the source. The amount of current between the drain and the source can be increased.

Specifically, a common soure line in the related art is formed on a contact plug formed on a source of a substrate, so that the contact plug decreases correspondingly with a gradual decrease in design rules. As the contact area between the source and the contact plug becomes smaller, the contact resistance increases.

Thus, in the present invention, the contact plug is not formed on the source of the substrate, and as the buried common source line is formed in the source in the substrate, the resistance in the source is lowered, and the amount of current between the drain and the source can be increased. .

As described above, the present invention can increase the amount of current between the drain and the source, thereby having the effect of lowering the operating voltage of the phase conversion memory element.

In addition, according to the present invention, since the gate is formed to overlap the buried common source line, even when the design rule is small, the gate can be formed largely stably, and the channel length is shortened to improve current flow. Can be.

In detail, FIGS. 3A to 3G are cross-sectional views illustrating processes for manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, an isolation layer 301 is formed in the surface of the semiconductor substrate 300 to define an active region according to a known process.

Next, after forming a mask pattern M exposing a common source line forming region on the substrate 300 including the device isolation layer 201, the exposed portion of the substrate is etched using the mask pattern M. FIG. As a result, a trench T defining a common source line region is formed.

In this case, the trench T is formed to have a depth smaller than that of the device isolation layer 301.

Referring to FIG. 3B, in the state in which the mask pattern is removed, impurity ion implantation is performed on the substrate on which the trench T is formed to form an impurity doped region 302a inside the surface of the trench T. Referring to FIG.

In this case, the impurity ion implantation is performed by P (phosphorus) or As (arsenic).

Then, after depositing the first conductive material on the substrate to fill the trench (T), the first conductive material by chemical mechanical polishing (CMP) to the device isolation film in the trench (T) A buried common source line 303 having a shallower depth than 301 is formed.

In this case, the first conductive material may be deposited by any one of an aluminum film, a tungsten film, a copper film, a titanium nitride film, and a titanium tungsten film.

Referring to FIG. 3C, gate materials are sequentially deposited on a substrate on which the buried common source line 303 is formed and then etched to form a substrate on the substrate, preferably between the buried common source line 303. A gate 304 is formed on the 300.

In this case, the gate 304 is formed to overlap the buried common source line 303.

Then, impurity ion implantation is performed on the substrate on which the buried common source line is not formed to form a drain 302b so that a transistor is formed in the substrate surface on the side of the gate 304.

Next, an insulating film is deposited on the gate 304 and the substrate 300, and then etched to form spacers 305 on both sidewalls of the gate 304.

Referring to FIG. 3D, after forming a first interlayer insulating film 391 on a substrate to cover the transistor, the hole is formed by etching the first interlayer insulating film 391 according to a dual damasence process. do.

Then, after depositing a second conductive material on the first interlayer insulating film 391 to fill the hole, the contact plug 306 to contact the drain 302b in the hole by CMP of the second conductive material. And a lower electrode 307 on the contact plug 306.

Referring to FIG. 3E, after forming a second interlayer insulating film 392 on the first interlayer insulating film 391 to cover the lower electrode 307, the second interlayer insulating film 392 is etched to form a lower electrode ( A first contact hole H1 exposing 307 is formed.

Thereafter, a lower electrode contact conductive film is deposited on the second interlayer insulating layer 392 so that the first contact hole H1 is filled, and then the conductive film is CMP to lower the electrode in the first contact hole H1. A lower electrode contact 308 is formed in contact with 307.

Referring to FIG. 3F, a phase change material film and an upper electrode conductive film are deposited on a second interlayer insulating film 392 including the lower electrode contact 308, and then etched to form a phase change material film on the lower electrode contact 308. The phase change film 309 and the upper electrode 310 are formed.

Referring to FIG. 3G, after the third interlayer insulating film 393 is formed on the second interlayer insulating film 392 to cover the upper electrode 310 and the phase change film 309, the third interlayer insulating film 393 is formed. ) Is formed to form a second contact hole H2 exposing the upper electrode 310.

After depositing a conductive film for the upper electrode contact on the third interlayer insulating film 393 so that the second contact hole (H2) is filled, the conductive film is CMP to the upper electrode 310 and the second contact hole (H2) An upper electrode contact 311 to contact is formed.

Thereafter, a bit line 312 is formed on the third interlayer insulating film 393 including the upper electrode contact 311.

As described above, the driving principle of the phase change memory device according to the present invention is briefly described. A current is formed from the bit line to the drain of the transistor through the upper electrode and the phase change film, and is formed between two buried common source lines. Current flows through the gate to the buried common source line.

As described above, the embodiments of the present invention have been described, but the present invention is not limited thereto, and those skilled in the art to which the present invention pertains have many modifications and variations without departing from the spirit of the present invention. Will understand.

As described above, according to the present invention, as the buried common source line is formed in the source in the semiconductor substrate, the resistance in the source decreases and the amount of current between the drain and the source increases, thereby lowering the operating voltage of the phase change memory device. Will be.

In addition, according to the present invention, as the gate is formed to overlap the buried common source line, a stable gate may be formed and the channel length may be reduced.

Claims (12)

A semiconductor substrate having an isolation layer in the surface thereof and having a trench formed in a common source line forming region; A buried common source line formed in said trench; A gate disposed on the substrate and formed between the buried common source lines; A drain formed to form a transistor in the substrate surface on the side of the gate where the buried common source line is not formed; A first interlayer insulating film formed on the substrate so as to cover the transistor; A lower electrode including a contact plug formed to contact the drain in the first interlayer insulating film; A second interlayer insulating film formed on the first interlayer insulating film to cover the lower electrode; A lower electrode contact formed to contact the lower electrode in the second interlayer insulating film; A phase conversion layer and an upper electrode stacked on the lower electrode contact; A third interlayer dielectric layer formed on the second interlayer dielectric layer to cover an upper electrode and a phase change layer; An upper electrode contact formed in contact with the upper electrode in the third interlayer insulating film; And A bit line formed on the third interlayer insulating layer including the upper electrode contact; Phase change memory device comprising a. The method of claim 1, And an impurity doped region formed inside the trench surface on which the buried common source line is formed. The method of claim 1, And the buried common source line is formed to a shallower depth than the device isolation layer. The method of claim 1, And the buried common source line is any one of an aluminum film, a tungsten film, a copper film, a titanium nitride film, and a titanium tungsten film. The method of claim 1, And the gate is formed to overlap the buried common source line. The method of claim 1, And the lower electrode including the contact plug is formed by a dual damascene process. Providing a semiconductor substrate having a device isolation film in a surface thereof and having a trench formed in a common source line forming region; Forming an impurity region on the entire surface of the trench by performing impurity ion implantation on the resultant substrate on which the trench is formed; Forming a buried common source line in the trench including the impurity region; Forming a gate on a substrate on the buried common source line; Performing impurity ion implantation on the substrate on which the buried common source line is not formed to form a drain such that a transistor is formed in the substrate surface on the side of the gate; Forming a first interlayer insulating film on the substrate so as to cover the transistor; Forming a contact plug in the first interlayer dielectric layer to contact the drain and forming a lower electrode; Forming a second interlayer insulating film on the first interlayer insulating film to cover the lower electrode; Etching the second interlayer insulating layer to form a first contact hole exposing a lower electrode; Forming a lower electrode contact in contact with the lower electrode in the first contact hole; Forming a phase conversion film and an upper electrode on the lower electrode contact; Forming a third interlayer dielectric layer on the second interlayer dielectric layer to cover an upper electrode and a phase change layer; Etching the third interlayer insulating layer to form a second contact hole exposing an upper electrode; Forming an upper electrode contact in contact with the upper electrode in the second contact hole; And Forming a bit line on the third interlayer insulating film including the upper electrode contact; A method for manufacturing a phase change memory device comprising a. The method of claim 7, wherein After the step of providing the semiconductor substrate with the trench formed, before the step of forming the buried common source line, And performing impurity ion implantation on the trench-formed substrate to form an impurity doped region inside the trench surface. The method of claim 7, wherein And the buried common source line is formed to have a depth shallower than that of the device isolation layer. The method of claim 7, wherein And the buried common source line is formed of any one of an aluminum film, a tungsten film, a copper film, a titanium nitride film and a titanium tungsten film. The method of claim 7, wherein And the gate is formed to overlap the buried common source line. The method of claim 11, And a contact plug and a lower electrode in contact with the drain in the first interlayer insulating film are formed by a dual damascene process.

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