KR20060122268A - Phase change ram device and method of manufacturing the same - Google Patents

Abstract

A phase change memory device and a method for manufacturing the same are provided to restrain etch damage when forming a metal pad and a ground line by isolating between a GST(Ge,Sb,Te) cell region and a ground voltage supply region. A substrate(21) has a GST cell region and a ground voltage supply region. An isolation layer(23) is formed in the substrate to define a T-type active region(22). Word lines(24) are crossed to the T-type active region. A junction region is formed in the active region of both sides of the word line. A first tungsten plug is formed on the GST cell region, and a second tungsten plug is formed on the ground voltage supply region. A dot-type metal pad(28) is formed on the GST cell region to contact the first tungsten plug, and a bar-type ground line(29) is formed on the ground voltage supply region to contact the second tungsten plug. A GST cell composed of a lower electrode and a GST layer is formed on the metal pad of the GST cell region.

Description

Phase change RAM device and method of manufacturing the same

1 is a cross-sectional view showing a conventional phase change memory element.

2A to 2D are plan views of processes for explaining a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 T-type active region

23: device isolation layer 24: word line

26a: first tungsten plug 26b: second tungsten plug

28: metal pad 29: ground line

The present invention relates to a phase change memory device and a method of manufacturing the same, and more particularly, to a phase change memory device and a method of manufacturing the same to prevent the occurrence of etching damage in the ground voltage application region by changing the layout.

In general, a memory device is a volatile random access memory (RAM) device that loses inputted information when the power is cut off, and a ROM that keeps the stored information stored even when the power is cut off. ) Are largely divided into elements. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased.

In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies have been conducted to develop new memory devices having the characteristics of the nonvolatile memory device and having a simple structure. For example, a phase change RAM device has recently been developed. ) Has been proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information.

In other words, the phase-conversion memory device uses a chalcogenide film as a phase-conversion film, which is a compound film composed of germanium (Ge), stevidium (Sb), and tellurium (Te). GST film), a phase change occurs between an amorphous state and a crystalline state by an applied current, that is, Joule heat, wherein the resistivity of the phase change film having an amorphous state is in a crystalline state. Since it is higher than the specific resistance of the phase change film having a value, the current flowing through the phase change film in the read mode is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

On the other hand, in the phase change memory device, since a current flow is required to be 1 ㎃ or more for the phase change of the GST film, the current required for the phase change of the GST film must be reduced by reducing the contact area between the GST film and the electrode.

1 is a cross-sectional view illustrating a conventional phase change memory device, which will be described below.

As shown, gates 4 are formed in the active region of the semiconductor substrate 1 defined by the isolation layer, and a junction region (not shown) is formed in the substrate surface on both sides of the gate 4. have. An interlayer insulating film 5 is formed on the entire surface of the substrate so as to cover the gates 4, and a region where a GST cell is to be formed and a line to which a ground voltage is applied (hereinafter referred to as a "Vss line"). The first tungsten plug 6a and the second tungsten plug 6b are formed in the interlayer insulating film 5 to be formed.

The first oxide film 7 is formed on the interlayer insulating film 5 including the first and second tungsten plugs 6a and 6b, and the first tungsten is formed in the GST cell formation region according to the damascene process. A metal pad 8 having a dot shape is formed to contact the plug 6a, and a ground line having a bar shape to contact the second tungsten plug 6b in a region to which a ground voltage is to be applied. 9) is formed.

Subsequently, a second oxide film 10 is formed on the first oxide film 7 including the metal pad 8 and the ground line 9, and in the second oxide film 10 in the region where the GST cell is to be formed. A plug type bottom electrode contact 11 is formed to contact the metal pad 8.

The GST layer 12 and the upper electrode 13 are stacked in a pattern so as to contact the lower electrode contact 11 on a portion of the second oxide layer on which the GST cell is to be formed. And a GST cell composed of the lower electrode contact 11, the GST film 12 and the upper electrode 13 stacked thereon.

A third oxide film 14 is formed on the second oxide film 10 to cover the GST cell, and a metal wiring 15 is formed on the third oxide film 14 to contact the upper electrode 13. It is.

However, in the conventional phase-change memory device as described above, when the metal pad and the ground line are simultaneously formed using the damascene process, the ground line region elongated in the bar shape is a GST cell in which the metal pad is formed. Etch damage of the lower layers may occur during the etching process compared to the region, thereby causing deterioration of the characteristics of the finally obtained phase change memory device.

Accordingly, an object of the present invention is to provide a phase change memory device and a method of manufacturing the same, which are designed to solve the conventional problems as described above, and to prevent the occurrence of etching damage in the ground voltage application region by changing the layout. There is this.

Another object of the present invention is to provide a phase change memory device and a method for manufacturing the same, which ensure device characteristics by suppressing etching damage when forming a ground line.

In order to achieve the above object, the present invention, a semiconductor substrate having a GST cell region and a ground voltage application region separated from each other; An isolation layer formed to define T-type active regions in the semiconductor substrate; Several word lines formed on the semiconductor substrate to pass through active regions; A junction region formed in the substrate active region on both sides of the word line; A first tungsten plug formed on the GST cell region of the substrate active region; A second tungsten plug formed on the ground voltage applying region of the active region; A metal pad having a dot shape formed to contact the first tungsten plug on the GST cell region; A bar-shaped ground line formed to contact the second tungsten plug on the ground voltage applying region; And a GST cell including a plug type lower electrode, a GST film, and an upper electrode stacked on the metal pad of the GST cell region.

In addition, the present invention provides a method for forming a semiconductor device comprising: forming an isolation layer defining a plurality of T-type active regions in a semiconductor substrate having a GST cell region and a ground voltage application region separated from each other; Forming several word lines on the semiconductor substrate through predetermined portions of an active region; Forming a junction region in the substrate active region on both sides of the word line; Forming an interlayer insulating film on an entire surface of the substrate to cover the word lines; Forming a first tungsten plug on the active region of the GST cell region and a second tungsten plug on the active region of the ground voltage application region; Forming a dot-shaped metal pad contacting the first tungsten plug on the interlayer insulating layer of the GST cell region and contacting the second tungsten plug on the interlayer insulating layer of the ground voltage application region separated from the GST cell region; Forming a ground line; And forming a GST cell formed of a stacked structure of a lower electrode, a GST film, and an upper electrode on a metal pad of the GST cell region.

Here, the dot-type metal pad and the bar-type ground line may form the ground line after the metal pad is formed first, or the metal pad is formed after the ground line is first formed. .

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described, and the present invention separates the region in which the GST cell is located from the region in which the ground voltage is applied by changing the layout, and the metal pad and the ground voltage applying region in the GST cell region. Separate ground lines at

In this case, the etching damage of the lower layers may be suppressed when the bar-type ground line is formed, and thus, the characteristics of the finally obtained phase change memory device may be secured by suppressing the etching damage.

In detail, FIGS. 2A to 2D are plan views for each process for explaining a method of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 23 may be formed in the semiconductor substrate 21 to define the T-type active regions 22. Then, several gates, that is, word lines 24, are formed on the front surface of the substrate through predetermined portions of the active region 22 according to a known process. In this case, the word line 24 is formed to partially expose the active region to be contacted with the ground line through partial bending.

Next, although not shown, a junction region is formed in the substrate active region 22 on both sides of the word line 24 through the implantation of high concentration ions of impurities.

Referring to FIG. 2B, an interlayer insulating film (not shown) is formed on the entire surface of the substrate to cover the word line 24, and then the surface of the substrate is flattened. Then, after selectively etching the interlayer insulating film portions of the region where the GST cell is to be formed and the region where the ground voltage is to be applied, tungsten deposition and chemical mechanical polishing (CMP) are performed to first tungsten in the region where the GST cell is to be formed. A plug 26a is formed, and a second tungsten plug 26b is formed in a region to which a ground voltage is to be applied.

Referring to FIG. 2C, a metal film 28 having a dot shape contacting the first tungsten plug 26a is formed on the interlayer insulating film portion of the region where the GST cell is to be formed by performing metal film deposition and etching thereof. .

Referring to FIG. 2D, a metal film is deposited and etched again on the substrate resultant to contact the second tungsten plug 26b in a region separated from the GST cell region in which the metal pad 28 is formed. A bar-shaped ground line 29 is formed in a direction perpendicular to the word line 24.

Here, in the related art, a dot-type metal pad and a bar-type ground line are simultaneously formed using a damascene process. Thus, etching damage is caused to lower layers in the ground voltage application region. Metal pads are formed first, and then the ground line of the ground voltage application region is formed later, and in particular, the metal pad forming region and the ground line forming region are separated, thereby simultaneously using the damascene process for the metal pad and the ground line. The etching damage in the ground voltage application region can be suppressed or significantly reduced as compared with the conventional art.

Subsequently, although not shown, a GST cell is formed by sequentially forming a plug type lower electrode, that is, a lower electrode contact, a patterned GST layer and an upper electrode, on the metal pad 28 of the GST cell region. Then, a series of well-known subsequent processes including a metallization forming process are carried out in order to complete the manufacture of the phase change memory device according to the present invention.

Meanwhile, in the above-described embodiment of the present invention, the metal pads in the form of dots in the GST cell region are formed first, and the bar-type ground lines in the ground voltage application region are formed later, but as another embodiment of the present invention, the ground It is also possible to first form a bar-type ground line in the voltage application region, and then form a metal pad in the form of a dot in the GST cell region later.

In this case as well, the metal pad in the GST cell region and the ground line in the ground voltage application region are separately formed, and the etching damage can be suppressed or significantly reduced by separating the formation region.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art to which the present invention pertains have many modifications and variations without departing from the spirit of the present invention. It will be appreciated that it can be added.

As described above, according to the present invention, the etching damage is generated when the metal pad in the form of a dot and the ground line in the form of a bar are formed by separating the region having the GST cell and the region where the ground voltage is applied by changing the layout. It is possible to suppress, thereby improving the characteristics of the finally obtained phase change memory element.

In addition, although not described in detail, the present invention may facilitate the subsequent process by suppressing the etch damage of the lower layers, and in particular, the thickness of the oxide film may be uniform in the lower electrode contact forming process performed by the E-beam process. In this way, a uniform bottom electrode contact can be formed.

Claims (8)

A semiconductor substrate having a GST cell region and a ground voltage application region separated from each other; An isolation layer formed to define T-type active regions in the semiconductor substrate; Several word lines formed on the semiconductor substrate to pass through active regions; A junction region formed in the substrate active region on both sides of the word line; A first tungsten plug formed on the GST cell region of the substrate active region; A second tungsten plug formed on the ground voltage applying region of the active region; A metal pad having a dot shape formed to contact the first tungsten plug on the GST cell region; A bar-shaped ground line formed to contact the second tungsten plug on the ground voltage applying region; And And a GST cell comprising a plug type lower electrode, a GST film, and an upper electrode stacked on the metal pad of the GST cell region. The phase change memory device of claim 1, wherein the word line is partially bent to expose a portion of an active region to be in contact with a ground line. The phase change memory device of claim 1, wherein the ground line is disposed in a direction perpendicular to a word line. Forming a device isolation film defining a plurality of T-type active regions in a semiconductor substrate having a GST cell region and a ground voltage application region separated from each other; Forming several word lines on the semiconductor substrate through predetermined portions of an active region; Forming a junction region in the substrate active region on both sides of the word line; Forming an interlayer insulating film on an entire surface of the substrate to cover the word lines; Forming a first tungsten plug on the active region of the GST cell region and a second tungsten plug on the active region of the ground voltage application region; Forming a dot-shaped metal pad contacting the first tungsten plug on the interlayer insulating layer of the GST cell region and contacting the second tungsten plug on the interlayer insulating layer of the ground voltage application region separated from the GST cell region; Forming a ground line; And And forming a GST cell formed of a stacked structure of a lower electrode, a GST film, and an upper electrode on the metal pad of the GST cell region. The method of claim 4, wherein the word line is formed to be bent to expose a portion of the active region to be in contact with the ground line. The method of claim 4, wherein the dot-shaped metal pad and the bar-type ground line form the metal pad first and then form the ground line. The method of claim 4, wherein the dot-type metal pad and the bar-type ground line form the metal pad after forming the ground line first. 5. The method of claim 4, wherein the ground line is formed to be perpendicular to the word line.

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