KR100772105B1 - Method of manufacturing phase change RAM device - Google Patents

Abstract

The present invention discloses a method of manufacturing a phase change memory element. According to an aspect of the present invention, there is provided a method of manufacturing a phase change memory device, including: preparing a semiconductor substrate having a contact plug; Sequentially forming a conductive film and a hard mask film on the entire surface of the substrate; Etching a portion of the hard mask layer and a portion of the conductive layer below the substrate to form a hole; Forming a phase conversion film on the entire surface of the hard mask film including the hole surface; CMP removing the phase change film formed on the hard mask film; Etching the hard mask layer and the conductive layer to form a first conductive pattern contacting the contact plug on one side of the phase change layer remaining in the hole, and forming a second conductive pattern on the other side of the phase change layer remaining in the hole ; Forming an insulating film on an entire surface of the substrate product on which the first and second conductive patterns are formed; Forming a contact hole exposing the second conductive pattern by etching the insulating film and the hard mask layer on the second conductive pattern; And forming a contact plug for a bit line in the contact hole.

Description

Method of manufacturing phase change memory device {Method of manufacturing phase change RAM device}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a phase change memory device according to the first prior art.

Fig. 2A is a sectional view showing a phase change memory element according to the second prior art.

FIG. 2B is a plan view from above taken along line a-a 'in FIG. 2A;

3A to 3E are cross-sectional views of steps for explaining a method of manufacturing a phase change memory device according to the prior art.

4A through 4D are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an embodiment of the present invention.

5A-5D are plan views corresponding to FIGS. 4A-4D, respectively.

6 is a sectional view showing a phase change memory device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

400: semiconductor substrate 401: device isolation film

402: gate 403a: source region

403b: drain region 404: first insulating film

405: first contact plug 406: second insulating film

407: metal pad 408: ground line

409: third insulating film 410: second contact plug

CL ': conductive film 411: hard mask film

11: first conductive pattern 22: second conductive pattern

412: phase change film 413: fourth insulating film

414: contact plug for bit line 415: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory element, and more particularly, to a method of manufacturing a phase change memory element capable of reducing the contact area between electrodes and a phase change layer and ensuring stable contact characteristics between the bit line and the electrode. It is about.

The memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power is cut off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased. In addition, the flash memory device requires a higher operating voltage than a power supply voltage in connection with a structure in which two gates are stacked, and thus a separate boost circuit is required to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies are being conducted to develop new memory devices having characteristics of the nonvolatile memory device and having a simple structure. For example, recently, a phase change RAM device has been developed. Was proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information. In other words, the phase-conversion memory device uses a chalcogenide film as a phase conversion film. The chalcogenide film is a compound film made of germanium (Ge), stevidium (Sb), and tellurium (Te). The phase change occurs between the amorphous state and the crystalline state by heat generated by the generated current, that is, Joule heat, and at this time, the resistivity of the phase change film having the amorphous state is determined by the crystalline state. Since it is higher than the specific resistance of the phase change film, the current flowing through the phase change film is sensed in the read mode to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

On the other hand, in such a phase conversion memory element, the phase conversion film becomes crystalline from amorphous state to reset, and conversely from amorphous state to crystalline state is called set. In terms of power consumption and operation speed The lower the magnitude of the current for the reset / set (programming), the better. Therefore, by making the contact area between the phase change film and the electrode as small as possible, the current density at the contact surface between the two materials should be increased to lower the current required for the phase change.

Thus, in order to reduce the contact area between the lower electrode and the phase conversion film, the lower electrode is formed in a plug type.

Hereinafter, a conventional phase change memory device will be described with reference to FIG. 1.

1 is a cross-sectional view showing a conventional phase change memory device.

As shown, the gate 102 is formed on the active region of the semiconductor substrate 100 defined by the device isolation film 101, and the source / drain regions 103a, the substrate 102 on both sides of the gate 102 are formed. 103b) is formed. A first insulating film 104 is formed on the entire surface of the substrate to cover the gate 102, and a region where a phase change cell is to be formed and a line to which a ground voltage is applied (hereinafter referred to as a "Vss line"). First contact plugs 105 contacting the source region 103a and the drain region 103b are formed in the first insulating layer portions of the region where the "

The second insulating layer 106 is formed on the first insulating layer 104 including the first contact plug 105, and the first contact plug 105 is formed in the phase conversion cell formation region according to a damascene process. A metal pad 107 having a dot shape is formed to contact the wire, and a ground line 108 having a bar shape is formed to contact the first contact plug 105 in a region to which a ground voltage is to be applied. Is formed.

Subsequently, a third insulating film 109 is formed on the second insulating film 106 including the metal pad 107 and the ground line 108, and the third insulating film 109 in the region where the phase change cell is to be formed. A bottom electrode contact 110 in the form of a plug is formed in the portion to contact the metal pad 107. In addition, the phase conversion film 111 and the upper electrode 112 are sequentially stacked on the lower electrode contact 110 and the third oxide film portion adjacent thereto, and as a result, the lower electrode, which is a plug type lower electrode, is stacked. A phase change cell including an electrode contact 110, a phase change layer 111 and an upper electrode 112 formed thereon are configured.

A fourth insulating layer 113 is formed on the third insulating layer 109 so as to cover the phase change cell, and the upper electrode 112 and the bit line contact plug 114 are formed on the fourth insulating layer 113. A bit line 115 is electrically connected through the bit line 115.

However, in the above-described conventional phase change memory device, since it is difficult to form a plug type lower electrode having a predetermined diameter or less due to the limitation of the exposure process, there is a limit in reducing the contact area between the lower electrode and the phase change film.

If the desired diameter of the plug type lower electrode is less than or equal to a predetermined length, the process of forming the lower electrode contact hole itself is difficult due to the limitation of the exposure process, and the variation of the contact hole diameter is increased, resulting in uniform characteristics. It is very difficult to manufacture a phase change memory device having.

In the above-described conventional phase change memory device, since the lower electrode contact 110, the phase change film 111, the upper electrode 112, and the bit line contact plug 114 are formed on the same axis, the contact hole is formed. In consideration of the formation region, the size of the phase conversion film 111 and the upper electrode 112 should be secured by a predetermined size or more. That is, it is difficult to reduce the size of the phase change film 111 and the upper electrode 112 formed on the lower electrode contact 110 in consideration of the process margin when forming the bit line contact hole.

Therefore, the conventional technology alone has a limitation in reducing the contact area between the electrode and the phase change film, so that it is very difficult to manufacture a phase change memory device having a uniform and low programming current.

Recently, a phase change memory device as shown in FIG. 2A has been proposed to reduce the contact area between the phase change film and the electrode without reducing the diameter of the plug type lower electrode.

The phase change memory device shown in FIG. 2A is formed between the first and second conductive patterns 1 and 2 having a symmetrical shape disposed on the same layer, that is, the third insulating film 209 at a predetermined distance therebetween. The phase conversion film 212 is interposed and in contact with the side wall thereof. The first conductive pattern 1 is a conductive pattern for a lower electrode connected to the source region 203a by the second contact plug 210, the metal pad 207, and the first contact plug 205. The second conductive pattern 2 is a conductive pattern for the upper electrode connected to the bit line 215 by the third contact plug 214.

Reference numeral 201 denotes an isolation layer, 202 a gate, 203b a drain region, 204 a first insulating layer, 206 a second insulating layer, 208 a ground line, 211 a fourth insulating layer, and 213 denotes a fifth insulating film. FIG. 2B is a plan view viewed from above along the line a-a 'of FIG. 2A. Referring to this, the structure of the first and second conductive patterns 1 and 2 and the phase change film 212 therebetween is described. I can see it well.

If the phase change memory device is manufactured to have the structure as shown in FIG. 2A, the contact area between the electrodes and the phase change film can be easily reduced without forming a fine contact hole, and the bit line can be reduced while the size of the phase change film is reduced. And stable contact characteristics of the upper electrode can be secured.

However, there are the following problems in manufacturing the phase change memory element as shown in FIG. 2A.

3A through 3E are cross-sectional views illustrating processes of manufacturing a phase change memory device as illustrated in FIG. 2A, and a brief description of the manufacturing process will be given below.

First, a manufacturing process of the phase change memory device as shown in FIG. 2A will be described.

Referring to FIG. 3A, the device isolation layer 201, the gate 202, the source region 203a, and the drain region 203b may be formed of a first insulating film 204, a first contact plug 205, and a second insulating film 206. ), A metal pad 207, a ground line 208, a third insulating film 209, and a second contact plug 210 are deposited on the entire surface of the resultant semiconductor substrate 200 formed as shown in FIG. 2A. The conductive film is first patterned to make it look like a dumbbell having both sides larger in width than the center portion. Next, a fourth insulating layer 211 is deposited to cover the first patterned conductive layer CL.

Referring to FIG. 3B, a second portion of the fourth insulating layer 211 and a predetermined portion of the first patterned conductive layer CL is second patterned to form a pair of symmetrical conductive patterns of the first patterned conductive layer CL. That is, the first and second conductive patterns 1 and 2 are separated, and an opening, which is a phase conversion film forming region, is formed therebetween.

Referring to FIG. 3C, a phase conversion material film 212 ′ is deposited on the entire surface of the fourth insulating film 211 including the opening surface to have a uniform thickness.

Referring to FIG. 3D, the phase change material film is formed on the fourth insulating layer 211 by performing a mask and etching process so that the phase change material film remains only in the opening. Thus, the phase conversion film 212 is interposed between the first conductive pattern 1 as the first electrode and the second conductive pattern 2 as the second electrode.

As shown in FIG. 3E, after forming the fifth insulating layer 213 to cover the phase change layer 212 and the fourth insulating layer 211, a predetermined portion of the fifth insulating layer 213 is etched to form a fifth insulating layer 213. A bit line contact hole exposing the two conductive patterns 2 is formed.

Then, a third contact plug 214 that is a bit line contact plug is formed in the bit line contact hole, and a second conductive pattern (3) is formed on the fifth insulating layer 213 through a third contact plug 214. A bit line 215, which is a wiring connected with 2), is formed. Thus, a phase change memory element as shown in Figs. 2A and 2B is manufactured.

However, in the conventional method of manufacturing a phase change memory device described above, in order to form the first and second conductive patterns 1 and 2 and the phase change film 212 therebetween, the conductive film must be patterned twice and the phase change material Since the film also needs to be patterned, three mask processes are required, which is very cumbersome and increases the manufacturing cost as the number of masks increases.

In particular, when the mask is misaligned when the phase change material layer is patterned, the phase change layer 212 may not be accurately positioned between the first and second conductive patterns 1 and 2. The contact between the phase change film 212 and the electrodes may not be properly made. As described above, the above-described phase change memory device has disadvantages in terms of its manufacturing process.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, to form a first electrode pattern, a second electrode pattern and a phase conversion film pattern therebetween in the same layer for low power consumption and stable contact characteristics It is an object of the present invention to provide a method of manufacturing a phase change memory device capable of improving troublesome process and problem of contact failure between an electrode pattern and a phase change film pattern.

According to an aspect of the present invention, there is provided a method of manufacturing a phase change memory device, including: preparing a semiconductor substrate having a contact plug; Sequentially forming a conductive film and a hard mask film on the entire surface of the substrate; Etching a portion of the hard mask layer and a portion of the conductive layer below the substrate to form a hole; Forming a phase conversion film on the entire surface of the hard mask film including the hole surface; CMP removing the phase change film formed on the hard mask film; Etching the hard mask layer and the conductive layer to form a first conductive pattern contacting the contact plug on one side of the phase change layer remaining in the hole, and forming a second conductive pattern on the other side of the phase change layer remaining in the hole ; Forming an insulating film on an entire surface of the substrate product on which the first and second conductive patterns are formed; Forming a contact hole exposing the second conductive pattern by etching the insulating film and the hard mask layer on the second conductive pattern; And forming a contact plug for a bit line in the contact hole.

Here, the phase conversion film is formed to partially fill the hole, or to completely fill the hole.

The first conductive pattern includes a main body contacting the contact plug and a connection portion adjacent to one side of the phase change film remaining in the hole, and when viewed in plan view, the connection portion is formed to have a smaller width than the main body. In this case, the connecting portion of the first conductive pattern is formed to have a width smaller than that of the phase change film remaining in the hole in plan view.

The second conductive pattern includes a main body contacting the contact plug for the bit line and a connection part adjacent to the other side of the phase change film remaining in the hole, and when viewed in plan view, the connection part is formed to have a smaller width than the main body. . The connecting portion of the second conductive pattern is formed to have a smaller width than the phase change film remaining in the hole in plan view.

The first and second conductive patterns are formed to have a symmetrical structure with respect to the phase change film remaining in the hole.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an exemplary embodiment of the present invention, and FIGS. 5A to 5D are plan views corresponding to FIGS. 4A to 4D, respectively.

Referring to FIG. 4A, an active region is defined by an isolation layer 401, a gate 402 is formed on the active region, and source / drain regions 403a are formed on surfaces of active regions on both sides of the gate 402. And a semiconductor substrate 400 having 403b formed thereon.

Thereafter, a first insulating layer 404 is formed on the substrate 400 to cover the lower structure, and the first contact plugs contact the source / drain regions 403a and 403b in the first insulating layer 404, respectively. 405 is formed. Thereafter, a second insulating film 406 is formed on the first insulating film 404 including the first contact plug 405, and a source region (not shown) is formed in the second insulating film 406 according to a damascene process. A metal pad 407 is formed in contact with the 403a and a ground line 408 is formed in contact with the drain region 403b.

Next, a third insulating film 409 is formed on the metal pad 407, the ground line 408, and the second insulating film 406, and a portion of the third insulating film 409 on the metal pad 407 is formed. After etching to form a contact hole exposing the metal pad 407, a second contact plug 410 is formed in the contact hole.

Then, the conductive film CL 'and the hard mask film 411 are sequentially formed on the entire surface of the substrate resultant, and then the hard mask film 411 formed on the substrate resultant portion other than the second contact plug 410. ) And a portion of the conductive film CL 'beneath it are etched to form a hole H as an opening. Referring to FIG. 5A, which is a plan view viewed from the top of FIG. 4A, the positions of the second contact plug 410 and the hole H may be confirmed.

Referring to FIG. 4B, after the phase change material film is formed on the entire surface of the hard mask film 411 including the hole H surface, the phase change material film formed on the hard mask film 411 is chemical mechanical polishing. Remove it. Thus, the phase conversion film 412 remains only in the hole H. FIG. 5B is a plan view seen from the top of FIG. 4B.

Referring to FIG. 4C, the hard mask layer 411 and the conductive layer CL ′ are etched to contact the second contact plug 410 on one side of the phase change layer 412 remaining in the hole H. Referring to FIG. The first conductive pattern 11 is formed, and the second conductive pattern 22 is formed on the other side of the phase change film 412 remaining in the hole H.

Here, the first and second conductive patterns 11 and 22 are planar based on the phase change film 412 remaining in the hole H, as shown in FIG. 5C, which is a plan view viewed from the top of FIG. 4C. It is formed to have a symmetrical structure. In addition, the first and second conductive patterns 11 and 22 may be formed to include the main bodies 11a and 22a and the connecting portions 11b and 22b, respectively. The connection part 11b adjacent to one side of the phase change layer 412 remaining in the hole of the second contact plug 410 is formed to have a smaller width than the main body 11a contacting the second contact plug 410. Similarly, the connecting portion 22b adjacent to the other side of the phase change film 412 remaining in the hole in the second conductive pattern 22 is smaller than the main body 22a that contacts the bit line contact plug to be formed later. It is formed to have a width. As a result, the connecting portions 11b and 22b of the first and second conductive patterns 11 and 22 are formed to have a smaller width than the phase change film 412 remaining in the hole in plan view.

In this case, a bit line contact plug may be formed on a portion of the second conductive pattern 22 that is not adjacent to the phase change layer 412, that is, a portion of the main body 22a having a size larger than the connection portion 22b. Part.

Referring to FIG. 4D, a fourth insulating layer 413 is formed on the entire surface of the substrate product on which the first and second conductive patterns 11 and 22 are formed, and a fourth insulating layer on the second conductive pattern 22 is formed. A portion of the 413 and the hard mask layer 411 is etched to form a bit line contact hole exposing the second conductive pattern 22.

Then, a bit line conductive film is formed on the fourth insulating layer 413 so as to fill the bit line contact hole, and the bit line conductive film is patterned to form a bit line contact plug 414 in the bit line contact hole. And a bit line 415 on the fourth insulating film 413.

FIG. 5D is a plan view viewed from above along the line a-a 'of FIG. 4D. Referring to this, the electrodes (first and second conductive patterns; 11 and 22) may not be formed finely. The contact area between the phase change film 412 can be easily reduced, and the stable contact characteristics of the bit line 415 and the electrode (second conductive pattern; 22) can be reduced while reducing the size of the phase change film 412. It can be seen that can be obtained.

Meanwhile, in the present invention, after forming the hole H by etching the phase conversion film forming regions of the conductive film CL ′ and the hard mask film 411 (first mask process), the hard including the hole H is included. The phase change material layer is deposited on the mask layer 411 and the CMP process is performed to leave the phase change layer 412 only in the hole H. Then, the conductive layer CL 'and the hard mask layer 411 are removed. Since the laminated film of the film is patterned (second mask process), the phase conversion film 412 can be accurately retained only inside the hole H, and the mask process can be reduced by one time compared with the conventional one.

Therefore, according to the method of the present invention, it is possible to prevent the occurrence of defects due to misalignment of the phase change film 412, and also to reduce the manufacturing cost and increase the productivity due to the process simplification.

In addition, according to the exemplary embodiment of the present invention, the phase change memory device may be manufactured in a structure in which the phase change film 412 is completely embedded in the hole H, as shown in FIG. 6. This structure is such that the phase conversion material film is not completely formed along the surface of the hole H so as to partially fill the hole H when the phase conversion material film is formed in FIG. 4B. Can be implemented.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person having ordinary skill in the art to which the present invention belongs does not depart from the essential idea of the present invention. It will be appreciated that it can be implemented in a modified form.

As described above, the present invention provides a conductive material for manufacturing a phase change memory device including conductive patterns for first and second electrodes having a symmetrical structure spaced apart on the same layer and a phase change film interposed therebetween. By differently patterning the film and forming the phase change film, the manufacturing process can be simplified and misalignment between the phase change film and the conductive pattern can be prevented.

Therefore, according to the method of the present invention, it is simpler and has a lower incidence of defects than the conventional process without the difficulty of the exposure process for forming the fine contact hole and the increase in the variation of the characteristics due to the formation of the fine contact hole. A phase change memory device can be implemented.

Claims (6)

Preparing a semiconductor substrate having a contact plug; Sequentially forming a conductive film and a hard mask film on the entire surface of the substrate; Etching a portion of the hard mask layer and a portion of the conductive layer below the substrate to form a hole; Forming a phase conversion film on the entire surface of the hard mask film including the hole surface; CMP removing the phase change film formed on the hard mask film; Etching the hard mask layer and the conductive layer to form a first conductive pattern contacting the contact plug on one side of the phase change layer remaining in the hole, and forming a second conductive pattern on the other side of the phase change layer remaining in the hole ; Forming an insulating film on an entire surface of the substrate product on which the first and second conductive patterns are formed; Forming a contact hole exposing the second conductive pattern by etching the insulating film and the hard mask layer on the second conductive pattern; And Forming a contact plug for a bit line in the contact hole; A method for manufacturing a phase change memory device comprising a. The method of claim 1, And the phase change film is formed to partially fill the hole or to completely fill the hole. The method of claim 1, The first conductive pattern includes a main body contacting the contact plug and a connection part adjacent to one side of the phase change film remaining in the hole, and when viewed in plan view, the connection part is formed to have a smaller width than the main body. A method of manufacturing a phase change memory device. The method of claim 1, The second conductive pattern includes a main body contacting the contact plug for the bit line and a connection part adjacent to the other side of the phase conversion film remaining in the hole, and when viewed in plan view, the connection part is formed to have a smaller width than the main body. A method for manufacturing a phase change memory device, characterized in that. The method according to claim 3 or 4, Each connecting portion of the first and second conductive patterns is formed to have a width smaller than that of the phase change film remaining in the hole in plan view. The method of claim 1, The first and second conductive patterns are formed to have a symmetrical structure with respect to the phase change film remaining in the hole.

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