CN117174650B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN117174650B CN117174650B CN202311446155.3A CN202311446155A CN117174650B CN 117174650 B CN117174650 B CN 117174650B CN 202311446155 A CN202311446155 A CN 202311446155A CN 117174650 B CN117174650 B CN 117174650B
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor structure includes: a substrate including a first region and a second region arranged in parallel; a pad nitride layer disposed on the substrate; the compensation nitriding layer is arranged on the pad nitriding layer; the first shallow groove is arranged in the first area; the second shallow groove is arranged in the second region in parallel with the first shallow groove; and the insulating medium is arranged in the first shallow groove and the second shallow groove, and the surface of the insulating medium is flush with the surface of the compensation nitride layer. The semiconductor structure and the manufacturing method thereof provided by the invention improve the performance of the semiconductor structure.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
The CIS (CMOS image sensor) image sensor is a complementary metal oxide semiconductor image sensor, can convert optical signals into electric signals, and can convert the electric signals into digital signals through a reading circuit, is widely applied to the field of vision, and is a core component of a camera module.
In a CIS image sensor, the CIS image sensor includes a logic region and a pixel region, wherein the logic region and the pixel region include a plurality of semiconductor devices, and the different semiconductor devices are isolated by a shallow trench isolation structure (Shallow Trench Isolation, STI). In different areas, STI has different depths, which easily causes problems of leakage, performance and reliability reduction of semiconductor devices in the manufacturing process, and limits the development of CIS image sensors.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which can improve the formation quality of the semiconductor structure, reduce electric leakage and improve the performance, stability and reliability of a semiconductor device.
In order to solve the technical problems, the invention is realized by the following technical scheme.
The invention provides a semiconductor structure, which at least comprises:
a substrate including a first region and a second region arranged in parallel;
a pad nitride layer disposed on the substrate;
the compensation nitriding layer is arranged on the pad nitriding layer;
the first shallow groove is arranged in the first area;
the second shallow groove is arranged in the second region in parallel with the first shallow groove;
and the insulating medium is arranged in the first shallow groove and the second shallow groove, and the surface of the insulating medium is flush with the surface of the compensation nitride layer.
In an embodiment of the present invention, the insulating medium includes a first insulating medium, and a highest portion of the first insulating medium located on the first shallow trench and/or the second shallow trench sidewall is flush with the surface of the pad nitride layer
In an embodiment of the present invention, the insulating medium includes a second insulating medium, the second insulating medium is disposed on the first insulating medium, and a top of the second insulating medium is flush with a surface of the compensation nitride layer.
In an embodiment of the present invention, the pad nitride layer and the compensation nitride layer are made of the same material.
In an embodiment of the present invention, the depth of the second shallow trench is greater than the depth of the first shallow trench.
The invention also provides a manufacturing method of the semiconductor structure, which at least comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area which are arranged in parallel;
forming a pad nitride layer on the substrate;
forming a compensation nitride layer on the pad nitride layer;
forming a first shallow trench in the first region;
forming a second shallow trench in the second region, wherein the second shallow trench is arranged in parallel with the first shallow trench;
and forming an insulating medium in the first shallow groove and the second shallow groove, wherein the surface of the insulating medium is flush with the surface of the compensation nitride layer.
In an embodiment of the present invention, the manufacturing method further includes:
forming a pad oxide layer on the substrate;
forming the pad nitride layer on the pad oxide layer;
etching part of the pad nitride layer, the pad oxide layer and the substrate to form the first shallow trench and the second shallow trench, wherein the thickness of the pad nitride layer remained on the second region is smaller than that of the pad nitride layer on the first region;
depositing a first insulating medium in the first shallow trench and the second shallow trench; and
and flattening the first insulating medium and the pad nitride layer until the first insulating medium is flush with the pad nitride layers on two sides of the first shallow trench and the second shallow trench.
In an embodiment of the present invention, the manufacturing method further includes:
forming a compensation nitride layer on the first insulating medium and the pad nitride layer;
etching part of the compensation nitride layer to form a concave part, wherein the concave part is aligned with the first insulating medium;
depositing a second insulating medium in the recess until the compensation nitride layer is covered;
planarizing the second insulating medium until the second insulating medium is flush with the compensation nitride layers at two sides of the concave part; and
and removing the compensation nitride layer and the pad nitride layer to form a first shallow trench isolation structure and a second shallow trench isolation structure.
In an embodiment of the present invention, a step height between the first shallow trench isolation structure and/or the second shallow trench isolation structure and the pad oxide layer is 40nm to 50nm.
In an embodiment of the present invention, a proportion of hydrofluoric acid in the polishing liquid when the first insulating medium is planarized is greater than a proportion of hydrofluoric acid in the polishing liquid when the first insulating medium and the pad nitride layer are planarized.
In summary, according to the semiconductor structure and the manufacturing method thereof provided by the invention, the unexpected effect of the application is to increase the step height of the shallow trench isolation structure and reduce the influence on the semiconductor device by improving the manufacturing method of the semiconductor structure. The self-alignment of the concave part and the shallow trench can be realized, the performance of the shallow trench isolation structure is improved, the number of masks is not required to be additionally increased, and the cost of the masks is reduced. The leakage problem of the semiconductor device is improved, the performance, stability and reliability of the semiconductor device are improved, and the applicability of the manufacturing method of the semiconductor structure is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first photoresist layer according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a first shallow trench formed in an embodiment of the invention.
FIG. 3 is a schematic diagram of a second photoresist layer according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a second shallow trench formed in an embodiment of the invention.
Fig. 5 is a schematic view of a first insulating medium deposited according to an embodiment of the present invention.
FIG. 6 is a schematic diagram of a first insulating medium planarized to be level with the nitride layer of the two-sided pad in an embodiment of the invention.
FIG. 7 is a schematic diagram of a compensated nitride layer formed according to an embodiment of the invention.
FIG. 8 is a schematic diagram of a third photoresist layer according to an embodiment of the invention.
FIG. 9 is a schematic illustration of forming a recess in a supplemental nitridation in accordance with an embodiment of the present invention.
Fig. 10 is a schematic diagram of a second dielectric deposited in an embodiment of the present invention.
FIG. 11 is a schematic diagram of an embodiment of the present invention after planarizing the second insulating medium to be level with the two side compensation nitride layers.
FIG. 12 is a schematic diagram of the removal of the offset nitride layer and the pad nitride layer according to an embodiment of the invention.
FIG. 13 is a schematic diagram of a first STI structure and a second STI structure according to one embodiment of the present invention.
Fig. 14 is a schematic view of the first and second sti structures after the semiconductor device is fabricated according to an embodiment of the present invention.
FIG. 15 is a schematic diagram of a pad nitride layer and a compensation nitride layer according to another embodiment of the present invention.
FIG. 16 is a schematic diagram of a first STI structure and a second STI structure according to another embodiment of the present invention.
Description of the reference numerals:
10. a substrate; 100. a first region; 200. a second region; 11. a pad oxide layer; 12. pad nitriding layer; 13. a first photoresist layer; 131. a first opening; 141. a first shallow trench; 142. a second shallow trench; 15. a second photoresist layer; 16. a first insulating medium; 17. compensating the nitriding layer; 171. a concave portion; 18. a third photoresist layer; 181. a second opening; 19. a second insulating medium; 21. a first shallow trench isolation structure; 22. and a second shallow trench isolation structure.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is provided first, and the substrate 10 may be any material suitable for forming a semiconductor device, for example, a semiconductor material formed of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer, or other III/V compounds, and the like, and further includes a stacked structure formed of these semiconductor materials, or is a silicon-on-insulator, a stacked silicon-on-insulator, a silicon-germanium-on-insulator, a germanium-on-insulator, and the like. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the substrate 10 includes, for example, a first region 100 and a second region 200 to form shallow trench isolation structures with different depths. In the present application, the first region 100 is used, for example, to form a Pixel sensing unit (Pixel Area) in a CIS image sensor, and the second region 200 is used, for example, to form a metal oxide semiconductor field effect transistor in a peripheral logic circuit unit in a CIS image sensor.
Referring to fig. 1, in an embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10, the pad oxide layer 11 is made of a dense silicon oxide, and the pad oxide layer 11 may be formed by any one of a dry oxide method, a wet oxide method, or an In situ vapor growth method (In-Situ Steam Generation, ISSG). In this embodiment, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900-1150 ℃, oxygen is introduced, the surface of the substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is good. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 40nm, 30nm, 40nm, or the like.
Referring to fig. 1, in an embodiment of the present invention, a pad nitride layer 12 is formed on a pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. Wherein the pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In the present invention, the pad nitride layer 12 may be formed by, for example, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, the pad nitride layer 12 is deposited by reacting at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 900 ℃, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and the thickness of the pad nitride layer 12 is, for example, less than or equal to 120nm, specifically, for example, 120nm, 110nm or 105nm, and by providing the pad nitride layer 12, the substrate 10 can be protected from planarization processes such as chemical mechanical polishing (Chemical Mechanical Polishing, CMP) involved in the fabrication process of the shallow trench isolation structure. And the pad nitride layer 12 can be used as a mask in the shallow trench formation process, and protects the substrate 10 at other positions from damage when the substrate 10 is etched. By setting the thickness of the pad nitride layer 12 to 120nm or less, the pad nitride layer 12 that is too thick may cause problems such as substrate deformation, which is disadvantageous in the production of semiconductor devices such as CIS image sensors that are critical to stress.
Referring to FIGS. 1-2, in one embodiment of the present inventionIn an example, after the pad nitride layer 12 is formed, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of first openings 131 are formed on the first photoresist layer 13 through an exposure and development process, wherein the first openings 131 are used to define the positions of the shallow trench isolation structures. The first etching is performed by using the first photoresist layer 13 as a mask, and the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the first opening 131 are etched to form a first shallow trench 141. In the present embodiment, the first shallow trench 141 is formed by dry etching, for example, and the etching gas includes chlorine (Cl), for example 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) Sulfur hexafluoride (SF) 6 ) Or hydrogen bromide (HBr), or the like, or a mixture thereof with oxygen (O 2 ) And (5) combining. After the etching is completed, the first photoresist layer 13 is removed.
Referring to fig. 2 to 3, in an embodiment of the present invention, after forming the first shallow trench 141, a second photoresist layer 15 is formed on the pad nitride layer 12 and the first shallow trench 141, and the second photoresist layer 15 on the second region 200 is removed through an exposure and development process, and then a second etching is performed. Namely, during the second etching, the area needing to form the deeper shallow trench isolation structure is directly exposed, the self alignment of the first etching and the second etching is ensured, and the performance of the semiconductor device is prevented from being reduced due to the failure of the shallow trench isolation structure.
Referring to fig. 3 to 4, in an embodiment of the present invention, the second photoresist layer 15 and the pad nitride layer 12 are used as masks to further etch the substrate 10 at the bottom of the first shallow trench 141 in the second region 200, so as to form a second shallow trench 142. In the present embodiment, the second shallow trench 142 is formed by dry etching, for example, and the etching gas includes, for example, one or a mixture of chlorine, trifluoromethane, difluoromethane, nitrogen trifluoride, sulfur hexafluoride, hydrogen bromide, or the like, or a combination of them with oxygen. After the etching is completed, the second photoresist layer 15 is removed, thereby forming a first shallow trench 141 in the first region 100 and a second shallow trench 142 in the second region 200. The depth of the first shallow trench 141 in the substrate 10 is 130nm to 160nm, for example, and the depth of the second shallow trench 142 in the substrate 10 is 290nm to 320nm, for example. The depth difference between the first shallow trench 141 and the second shallow trench 142 is determined by the etching amount of the second etching. In other embodiments, the depth and the depth difference between the first shallow trench 141 and the second shallow trench 142 can be specifically designed according to the manufacturing requirements of the semiconductor device. By arranging shallow trenches with different depths, the defects of shallow trench etching in the first region 100 can be reduced, so that carriers generated by photoelectric effect in the first region 100 are prevented from being captured in the defects of the shallow trench isolation structure, and the capacity of the photosensitive region can be increased.
Referring to fig. 4, in an embodiment of the present invention, in order to ensure self-alignment with the first etching during the second etching, no photoresist is formed on the second region 200, and the pad nitride layer 12 on the second region 200 is used as a mask to etch the substrate 10 during the etching. During the etching process, the pad nitride layer 12 on the second region 200 is partially consumed, and after the etching, the thickness of the pad nitride layer 12 remaining on the second region 200 is smaller than the thickness of the pad nitride layer 12 on the first region 100. In this embodiment, the thickness of the pad nitride layer 12 on the first region 100 is, for example, 80 to 110nm, and the thickness of the pad nitride layer 12 on the second region 200 is, for example, 50 to 70nm, i.e., the thicknesses of the pad nitride layers 12 remaining on different regions of the substrate 10 are different.
Referring to fig. 4 to 5, in an embodiment of the present invention, after forming the shallow trenches, a first insulating medium 16 is deposited in the first shallow trenches 141 and the second shallow trenches 142 until the first insulating medium 16 covers the surface of the pad nitride layer 12. Before depositing the first insulating medium 16, the first shallow trenches 141 and the second shallow trenches 142 are subjected to a thermal oxidation process to form liner oxide layers (not shown in the figure), so as to reduce etching damage, and round the bottoms and corners of the first shallow trenches 141 and the second shallow trenches 142, so as to reduce tip leakage. The present invention is not limited to the deposition method of the first insulating medium 16, and for example, the high-quality first insulating medium 16 may be formed by high-density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high-aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP-CVD). After the first insulating medium 16 is deposited, a high temperature tempering process may be performed, for example, at 800 ℃ to 1200 ℃, to increase the density and stress of the first insulating medium 16. In this embodiment, the first insulating medium 16 is, for example, silicon oxide, and in other embodiments, the first insulating medium 16 may be another insulating material suitable for isolation.
Referring to fig. 4 to 6, in an embodiment of the present invention, after the first insulating medium 16 is prepared, the first insulating medium 16 is planarized, for example, by chemical mechanical polishing, until the first insulating medium 16 is consistent with the heights of the pad nitride 12 on the first region 100 and the second region 200, and polishing is stopped. Specifically, during the polishing process, the hydrofluoric acid content of the polishing liquid is increased to increase the polishing rate of the first insulating medium 16 before polishing to the pad nitride layer 12 on the first region 100. After polishing the pad nitride layer 12 on the first region 100, the polishing liquid is replaced, the content of hydrofluoric acid in the polishing liquid is reduced, the proportion of hot phosphoric acid is increased, the polishing rate of the first insulating medium 16 is reduced, and the polishing rate of the pad nitride layer 12 is increased, so that the thicknesses of the pad nitride layers 12 remaining on the first region 100 and the second region 200 are consistent, the heights of the first insulating medium 16 in the first shallow trench 141 and the second shallow trench 142 are consistent with those of the pad nitride layers 12 on both sides, i.e., the highest positions of the first insulating medium 16 in the first shallow trench 141 and the second shallow trench 142 are flush with the surface of the pad nitride layer 12. The first insulating medium 16 at the center of the first and second shallow trenches 141 and 142 is 1 to 2nm lower than the edge due to the polishing. In this embodiment, after polishing the first insulating medium 16, the remaining thickness of the pad nitride layer 12 on the substrate 10 is, for example, 20 to 35nm. If the pad nitride layer 12 with the remaining thickness is directly removed to form a shallow trench isolation structure, the step height of the shallow trench isolation structure is smaller, the ion implantation and the acid cleaning processes are more in the subsequent CIS image sensor manufacturing process, the step height of the shallow trench isolation structure is consumed in the acid cleaning process, the final STI is lower than the substrate, and the problems of electric leakage, performance and reliability of the device are reduced. Therefore, the remaining thickness of the pad nitride layer 12 cannot meet the device fabrication requirements.
Referring to fig. 6 to 7, in an embodiment of the present invention, after polishing the first insulating medium 16, a compensation nitride layer 17 is formed on the pad nitride layer 12 and the first insulating medium 16, and the compensation nitride layer 17 is obtained by a low pressure chemical vapor deposition method, for example. Wherein the substance of the compensation nitride layer 17 and the pad nitride layer 12 are the same. In this embodiment, the compensation nitride layer 17 is, for example, a silicon nitride layer, and the thickness of the compensation nitride layer 17 is, for example, 15nm to 25nm, and is, for example, 18nm, 20nm, 25nm, or the like. In other embodiments, the thickness of the compensation nitride layer 17 is flexibly selected according to the remaining thickness of the pad nitride layer 12 on the substrate 10, and the present invention is not particularly limited.
Referring to fig. 7 to 9, in an embodiment of the present invention, after forming the compensation nitride layer 17, a portion of the compensation nitride layer 17 is etched, and a plurality of recesses 171 are formed in the compensation nitride layer 17. Specifically, a third photoresist layer 18 is formed on the compensation nitride layer 17, and the third photoresist layer 18 is exposed and developed to form a plurality of second openings 181. In this embodiment, the mask plate for exposing the third photoresist layer 18 and the mask plate for exposing the first photoresist layer are the same mask plate, and the position of the formed second opening 181 corresponds to the position of the first opening, that is, the second opening 181 is located on the first insulating medium 16 in the first shallow trench 141 and the second shallow trench 142, so that self alignment can be achieved, and the number of mask plates does not need to be increased additionally, so that the cost of the mask plates is reduced.
Referring to fig. 8 to 9, in an embodiment of the invention, the third photoresist layer 18 is used as a mask to etch the compensation nitride layer 17 exposed by the second opening 181 until the first insulating medium 16 stops, so as to form a plurality of recesses 171, i.e. the recesses 171 are located on the first insulating medium 16. The compensation nitride layer 17 is removed by dry etching, wet etching, or a combination of dry etching and wet etching, for example. In this embodiment, the compensation nitride layer 17 is etched by dry etching, for example, and the etching gas is carbon tetrafluoride, sulfur hexafluoride, silicon tetrachloride, nitrogen trifluoride, or the like, for example. The shape of the recess 171 is ensured by dry etching, the morphology of the shallow trench isolation structure is improved, and isolation performance is ensured.
Referring to fig. 9 to 11, in an embodiment of the present invention, after forming the recess 171, the second insulating medium 19 is deposited in the recess 171 until the second insulating medium 19 covers the surface of the compensation nitride layer 17. The present invention is not limited to the manner of depositing the second insulating medium 19, and may be formed by, for example, chemical vapor deposition or the like to form the second insulating medium 19 of high quality. After the second insulating medium 19 is deposited, a high temperature tempering process may be performed, for example, at 800 ℃ to 1200 ℃, to increase the density and stress of the second insulating medium 19. In this embodiment, the second insulating medium 19 and the first insulating medium 16 are the same material. After the second insulating medium 19 is deposited, the second insulating medium 19 is subjected to a planarization process, for example, chemical mechanical polishing is performed to planarize the second insulating medium 19 until polishing is stopped until the top of the second insulating medium 19 in the recess 171 is level with the surfaces of the offset nitride layers 17 on both sides. During the grinding process, the compensation nitride layer 17 is removed by a small amount.
Referring to fig. 4 and 11 to 12, in an embodiment of the present invention, after the second insulating medium 19 is planarized, the offset nitride layer 17 and the pad nitride layer 12 on the first region 100 and the second region 200 are removed. The present invention is not limited to the removal method of the compensation nitride layer 17 and the pad nitride layer 12, and for example, the removal method may be a dry etching method, a wet etching method, or a combination of a dry etching method and a wet etching method. In this embodiment, for example, an acid solution is used to etch the compensation nitride layer 17 and the pad nitride layer 12, and specifically, a volume fraction of phosphoric acid, for example, 85% -88%, is used to etch the compensation nitride layer 17 and the pad nitride layer 12 at, for example, 150 ℃ -165 ℃ to form the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22. The first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 include a first insulating medium 16 and a second insulating medium 19, and the second insulating medium 19 is located on the first insulating medium 16.
Referring to fig. 4 and 12, in an embodiment of the invention, a first shallow trench isolation structure 21 is formed in a first shallow trench 141, a second shallow trench isolation structure 22 is formed in a second shallow trench 142, a depth of the first shallow trench isolation structure 21 is smaller than a depth of the second shallow trench isolation structure 22, and a depth difference is equal to a depth difference between the first shallow trench 141 and the second shallow trench 142. Steps are formed between the first shallow trench isolation structure 21 and the pad oxide layer 11 and between the second shallow trench isolation structure 22 and the pad oxide layer 11, and the height h of the steps is, for example, 40nm to 50nm, and is, for example, 45nm. The steps in the same area may be equal in height, or the steps in different areas may be unequal in height, and further operations may be performed according to specific manufacturing requirements, which are not described herein. By forming the compensation nitride layer, the thickness of the nitride layer on the substrate is ensured before the pad nitride layer is removed, so that the step height of the shallow trench isolation structure is increased, the shallow trench isolation structure caused by the CIS image sensor in the subsequent acid washing process for many times is prevented from being lower than the surface of the substrate, the effectiveness of STI is ensured, and the failure of the CIS image sensor is reduced.
Referring to fig. 12 to 13, in an embodiment of the present invention, after removing the offset nitride layer 17 and the pad nitride layer 12, the pad oxide layer 11 on the substrate 10 is removed. The pad oxide layer 11 is removed by wet etching, for example, and an etching liquid of the wet etching is hydrofluoric acid or a buffered oxide etching liquid (Buffered Oxide Etch, BOE) or the like, for example. At the same time of etching the pad oxide layer 11, since the second insulating medium 19 is also an oxide layer, the shallow trench isolation structures equal to the pad oxide layer 11 are removed at the same time, the steps between the first shallow trench isolation structure 21 and the pad oxide layer 11, and between the second shallow trench isolation structure 22 and the pad oxide layer 11 are transferred to the first shallow trench isolation structure 21, the second shallow trench isolation structure 22 and the substrate 10, and the time when the pad oxide layer 11 is just removed is controlled, so that the height h of the step is unchanged. After the pad oxide layer 11 is removed, the semiconductor device is continuously fabricated on the substrate 10. In other embodiments, after removing the pad nitride layer 12, other manufacturing processes may be performed on the substrate 10, such as forming a well region, etc., and the pad oxide layer 11 is removed in a subsequent process to reduce damage to the substrate 10. Through the manufacturing process, shallow trench isolation structures with different depths are formed in the substrate, the height of the step is ensured, the formed semiconductor structure is complete, the isolation effect is good, and the use requirement of the CIS image sensor is met.
Referring to fig. 13 to 14, in an embodiment of the invention, after forming the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 with different depths, a CIS image sensor is fabricated. The first region 100 where the first shallow trench isolation structure 21 is formed is used to form a pixel sensing unit in the CIS image sensor, and the second region 200 where the second shallow trench isolation structure 22 is formed is used to form a peripheral logic circuit unit in the CIS image sensor, so as to improve the performance of the CIS image sensor. After the CIS image sensor is formed, the heights of the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 can be ensured to be flush with the substrate, the problem of too low STI filler is solved, the problem of electric leakage of the semiconductor device is improved, and the performance, stability and reliability of the semiconductor device are improved.
Referring to fig. 15 to 16, in another embodiment of the present invention, for a semiconductor device with a stress less stringent than that of the image sensor, in the process of obtaining STI with different depth, a compensation nitride layer 17 may be directly formed on the pad nitride layer 12 before forming the shallow trench, and the compensation nitride layer 17 and the pad nitride layer 12 have a larger stress on the substrate 10, but the effect of the stress may be ignored in the semiconductor device manufactured later. The compensation nitride layer 17, the pad nitride layer 12 and the substrate 10 are etched to form a first shallow trench and a second shallow trench, and a first insulating medium is deposited in the first shallow trench and the second shallow trench until the compensation nitride layer 17 is covered. And when the heights of the first insulating medium and the pad nitride layers at two sides are consistent, the residual thickness of the pad nitride layer 12 is 40-50 nm, and after the pad nitride layer 12 and the pad oxide layer 11 are directly removed, the step height h of the formed STI is 40-50 nm, so that the device manufacturing requirement is met. Namely, the manufacturing method of the semiconductor structure provided by the invention is not only suitable for the CIS image sensor, but also suitable for any manufacturing process with the requirement of improving the height of the STI filler, such as a manufacturing process with larger etching depth, smaller photomask opening ratio or more subsequent pickling times.
In summary, according to the semiconductor structure and the manufacturing method thereof provided by the invention, the manufacturing method of the semiconductor structure is improved, and the unexpected effect of the application is that the step height of the obtained shallow trench isolation structure meets the use requirement of the CIS image sensor, and meanwhile, the influence of stress on the CIS image sensor is avoided. In the manufacturing process, the self-alignment of the concave part and the shallow trench can be realized, the performance of the shallow trench isolation structure is improved, the number of masks is not required to be increased additionally, and the cost of the masks is reduced. The leakage problem of the semiconductor device is improved, and the performance, stability and reliability of the semiconductor device are improved. The manufacturing method of the semiconductor structure can be applied to any manufacturing process with the requirement of improving the height of the STI filler, such as a manufacturing process with larger etching depth, smaller photomask opening ratio or more subsequent pickling times, and the applicability of the manufacturing method of the semiconductor structure is improved.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment (a specific embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily in all embodiments, of the invention. Thus, the appearances of the phrases "in one embodiment (in one embodiment)", "in an embodiment (in an embodiment)", or "in a specific embodiment (in a specific embodiment)" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (8)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area which are arranged in parallel;
forming a pad nitride layer on the substrate;
forming a first shallow trench in the first region;
forming a second shallow trench in the second region, wherein the second shallow trench is arranged in parallel with the first shallow trench;
forming a first insulating medium in the first shallow trench and the second shallow trench, wherein the first insulating medium is flush with the pad nitride layers at two sides of the first shallow trench and the second shallow trench;
forming a compensation nitride layer on the first insulating medium and the pad nitride layer;
etching part of the compensation nitride layer to form a concave part, wherein the concave part is aligned with the first insulating medium;
depositing a second insulating medium in the recess until the compensation nitride layer is covered;
planarizing the second insulating medium until the second insulating medium is flush with the compensation nitride layers at two sides of the concave part;
and removing the compensation nitride layer and the pad nitride layer to form a first shallow trench isolation structure and a second shallow trench isolation structure.
2. The method of claim 1, wherein the insulating medium comprises a first insulating medium, and a highest portion of the first insulating medium in the first shallow trench and/or the second shallow trench is flush with a surface of the pad nitride layer.
3. The method of claim 2, wherein the insulating medium comprises a second insulating medium disposed on the first insulating medium, the top of the second insulating medium being flush with the surface of the compensation nitride layer.
4. The method of claim 1, wherein the pad nitride layer and the compensation nitride layer are formed of the same material.
5. The method of claim 1, wherein the second shallow trench has a depth greater than a depth of the first shallow trench.
6. The method of fabricating a semiconductor structure of claim 1, further comprising:
forming a pad oxide layer on the substrate;
forming the pad nitride layer on the pad oxide layer;
etching part of the pad nitride layer, the pad oxide layer and the substrate to form the first shallow trench and the second shallow trench, wherein the thickness of the pad nitride layer remained on the second region is smaller than that of the pad nitride layer on the first region;
depositing a first insulating medium in the first shallow trench and the second shallow trench; and
and flattening the first insulating medium and the pad nitride layer until the first insulating medium is flush with the pad nitride layers on two sides of the first shallow trench and the second shallow trench.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein a step height between the first shallow trench isolation structure and/or the second shallow trench isolation structure and the pad oxide layer is 40nm to 50nm.
8. The method of manufacturing a semiconductor structure according to claim 6, wherein a proportion of hydrofluoric acid in the polishing liquid when planarizing the first insulating medium is larger than a proportion of hydrofluoric acid in the polishing liquid when planarizing the first insulating medium and the pad nitride layer.
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