CN112928059A - Method for forming shallow trench isolation - Google Patents
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- CN112928059A CN112928059A CN202110080417.3A CN202110080417A CN112928059A CN 112928059 A CN112928059 A CN 112928059A CN 202110080417 A CN202110080417 A CN 202110080417A CN 112928059 A CN112928059 A CN 112928059A
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000002955 isolation Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- 238000001039 wet etching Methods 0.000 claims abstract description 22
- 238000011049 filling Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000009499 grossing Methods 0.000 claims abstract description 3
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 244000208734 Pisonia aculeata Species 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Element Separation (AREA)
Abstract
The application discloses a method for forming shallow trench isolation, and relates to the field of semiconductor manufacturing. The method comprises forming a pad oxide layer and a hard mask layer on a substrate, wherein the hard mask layer is made of silicon nitride; forming a groove in the substrate through photoetching and etching processes; carrying out wet etching treatment on the substrate, removing part of the hard mask layer outside the groove and smoothing the top angle of the hard mask layer; forming an oxide layer; removing the oxide layer to expose the surface of the substrate outside the trench; forming an oxide layer again, wherein the side wall and the bottom of the groove are covered by the oxide layer, and the top angle of the groove is smooth; forming a silicon nitride layer, wherein the silicon nitride layer covers the oxide layer; filling the groove with silicon oxide to form shallow groove isolation; the problem that the existing shallow trench isolation structure is easy to have the defect of deformation of a side wall film in the forming process is solved; the effect of reducing the influence of dark current on the device performance, avoiding the deformation defect of the side wall film of the shallow trench and improving the device performance is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for forming shallow trench isolation.
Background
The CMOS image sensor is a device that converts an optical signal into an electrical signal, and has the characteristics of small volume, low power consumption, low cost, and the like. During device manufacturing, active regions of various devices on the same substrate are isolated through isolation structures. Shallow Trench Isolation (STI) is widely used in the fabrication of CMOS image sensors.
Dark current in the pixel area of a CMOS image sensor adversely affects the performance of the device, and charge escape through the STI oxide layer to the interface is the primary mechanism for dark current generation. At present, in the process of forming the STI, a layer of silicon nitride grows on the surface of an oxide layer of the STI, and the density of the silicon nitride is higher than that of the silicon oxide, so that the escape of charges can be effectively prevented, and the influence of dark current on the performance of a device is reduced.
However, after the deposition of silicon nitride, there is a large residual stress, and the High Density Plasma bombardment is applied when the trench is filled with HDP (High Density Plasma) silicon oxide, which causes the film deformation due to the mismatch of pressure and affects the device performance.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method for forming shallow trench isolation. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for forming shallow trench isolation, where the method includes:
forming a pad oxide layer and a hard mask layer on a substrate, wherein the hard mask layer is made of silicon nitride;
forming a groove in the substrate through photoetching and etching processes;
carrying out wet etching treatment on the substrate, removing part of the hard mask layer outside the groove and smoothing the top angle of the hard mask layer;
forming an oxide layer, wherein the side wall and the bottom of the trench are covered by the oxide layer;
removing the oxide layer to expose the surface of the substrate outside the trench;
forming an oxide layer again, wherein the side wall and the bottom of the groove are covered by the oxide layer, and the top angle of the groove is smooth;
forming a silicon nitride layer, wherein the silicon nitride layer covers the oxide layer;
and filling the groove with silicon oxide to form shallow groove isolation.
Optionally, the wet etching process is performed on the substrate, and includes:
and carrying out wet etching treatment on the hard mask layer on the surface of the substrate.
Optionally, the wet etching process is performed on the substrate, and includes:
and carrying out wet etching treatment on the hard mask layer and the pad oxide layer on the surface of the substrate.
Optionally, forming an oxide layer includes:
and growing an oxide layer by an ISSG process.
Optionally, forming a silicon nitride layer includes:
and forming a silicon nitride layer on the surface of the oxide layer by a deposition process or a heat furnace tube process.
Optionally, filling the trench with silicon oxide to form a shallow trench isolation, including:
and depositing silicon oxide by an HDP (high-density plasma) process, and completely filling the groove by using the silicon oxide to form shallow trench isolation.
Optionally, removing the oxide layer to expose the substrate surface outside the trench, including:
and removing the oxide layer by a wet etching process to expose the surface of the substrate outside the trench.
Optionally, after the trench is filled with silicon oxide and shallow trench isolation is formed, the method further includes:
the substrate is subjected to a CMP process.
The technical scheme at least comprises the following advantages:
forming a pad oxide layer and a hard mask layer on a substrate, etching the substrate to form a groove, carrying out wet etching treatment on the substrate to remove part of the hard mask layer outside the groove and smooth the top angle of the hard mask layer, forming an oxide layer on the groove, removing the oxide layer, forming an oxide layer again, forming a silicon nitride layer on the surface of the oxide layer, filling the groove with silicon oxide, and forming shallow groove isolation in the substrate; the problem that the existing shallow trench isolation structure is easy to have the defect of deformation of a side wall film in the forming process is solved; the effect of reducing the influence of dark current on the device performance, avoiding the deformation defect of the side wall film of the shallow trench and improving the device performance is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram illustrating an implementation of a method for forming shallow trench isolation according to an embodiment of the present disclosure;
fig. 10 is a schematic diagram of a semiconductor device provided in an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flowchart of a method for forming a shallow trench isolation according to an embodiment of the present disclosure is shown, where the method at least includes the following steps:
in step 101, a pad oxide layer and a hard mask layer are formed on a substrate, wherein the hard mask layer is made of silicon nitride.
As shown in fig. 2, a pad oxide layer 22 is formed on the surface of a substrate 21, and a hard mask layer 23 is formed on the surface of the pad oxide layer 22.
Optionally, the substrate is a silicon substrate.
In step 102, a trench is formed in the substrate by a photolithography and etching process.
Coating photoresist on the surface of the hard mask layer, exposing through a mask plate with a groove pattern, transferring the groove pattern into the photoresist layer after developing, etching the hard mask layer by taking the photoresist layer as a mask, and etching the pad oxide layer and the substrate by taking the etched hard mask layer as a mask, as shown in fig. 3, forming a groove 24 in the substrate 21.
The depth and the opening of the trench are determined according to practical situations, and the embodiment of the present application does not limit this.
In step 103, the substrate is subjected to wet etching to remove a portion of the hard mask layer outside the trench and to smooth the top corners of the hard mask layer.
The substrate is subjected to pullback by a wet etching process to remove a portion of the silicon nitride outside the trench 24 and near the trench opening and to round the top corner of the hard mask layer, as shown in fig. 4.
Optionally, after the hard mask layer outside the trench is opened, the exposed pad oxide layer is also removed, or the exposed pad oxide layer is not removed.
In step 104, an oxide layer is formed, and the sidewalls and bottom of the trench are covered with the oxide layer.
An oxide layer 25 is grown on the substrate, and the oxide layer 25 covers the sidewalls and bottom of the trench 24, the substrate surface exposed at both sides of the trench 24, and the hard mask layer 23, as shown in fig. 5. At this time, although the vertex angle of the groove 24 is rounded, the vertex angle of the groove 24 is not smooth enough; the trench 24 is not completely filled. The thickness of the oxide layer 25 is determined according to actual conditions.
In step 105, the oxide layer is removed to expose the substrate surface outside the trench.
The oxide layer 25 on the substrate is removed in preparation for the oxide layer to be formed again. As shown in fig. 6, the oxide layer 25 is removed.
If the pad oxide layer under the opened hard mask layer is not removed in step 103, the pad oxide layer under the opened hard mask layer and the oxide layer 25 are removed together in this step, exposing the substrate surface outside the trench 24.
In step 106, an oxide layer is formed again, the trench sidewalls and bottom are covered with a silicon oxide layer, and the top corners of the trench are rounded.
An oxide layer 26 is again formed on the substrate, and the oxide layer 26 covers the sidewalls and bottom of the trench 24, the substrate surface exposed at both sides of the trench 24, and the hard mask layer 23, as shown in fig. 7, the top corners of the trench 24 are more rounded.
In step 107, a silicon nitride layer is formed overlying the oxide layer.
The thickness of the silicon nitride layer is determined according to practical situations, and the embodiment of the present application does not limit this.
As shown in fig. 8, a silicon nitride layer 27 is formed on the substrate, the silicon nitride layer 27 covering the oxide layer 26. At this point, the trench 24 is not completely filled, and there is still a gap within the trench 24; the thickness of the silicon nitride layer 27 is determined according to practical circumstances.
In step 108, the trench is filled with silicon oxide to form shallow trench isolation.
And depositing silicon oxide on the substrate, wherein the deposited silicon oxide fills the groove to form shallow trench isolation.
As shown in fig. 9, the trench is completely filled with silicon oxide 28, and shallow trench isolation is formed on the substrate 21.
To sum up, in the method for forming shallow trench isolation provided in the embodiment of the present application, a pad oxide layer and a hard mask layer are formed on a substrate, the substrate is etched to form a trench, wet etching is performed on the substrate to remove a portion of the hard mask layer outside the trench, and make the top angle of the hard mask layer smooth, an oxide layer is formed on the trench, the oxide layer is removed again, an oxide layer is formed again, a silicon nitride layer is formed on the surface of the oxide layer, the trench is filled with silicon oxide, and shallow trench isolation is formed in the substrate; the problem that the existing shallow trench isolation structure is easy to have the defect of deformation of a side wall film in the forming process is solved; the effect of reducing the influence of dark current on the device performance, avoiding the deformation defect of the side wall film of the shallow trench and improving the device performance is achieved.
Because no thermal budget (thermal budget) is introduced into the shallow trench isolation forming method provided by the embodiment of the application, the shallow trench isolation forming method can be applied to the manufacturing process of the CIS device, and the deformation defect of the side wall film of the shallow trench isolation of the CIS device is avoided.
In one example, the shallow trench isolation formed by the method provided by the embodiment of the present application, as shown in fig. 10, has no deformation of the sidewall film of the shallow trench isolation 31.
Another embodiment of the present application provides a method for forming shallow trench isolation, which at least includes the following steps:
in step 201, a pad oxide layer and a hard mask layer are formed on a substrate, wherein the hard mask layer is made of silicon nitride.
This step is explained in step 101 above and will not be described here.
In step 202, a trench is formed in the substrate by a photolithography and etching process.
This step is explained in step 102 above and will not be described here.
In step 203, the substrate is subjected to wet etching to remove a portion of the hard mask layer outside the trench and to smooth the top corners of the hard mask layer.
Optionally, the hard mask layer on the surface of the substrate is subjected to wet etching treatment. And performing pullback on the hard mask layer on the surface of the substrate by a wet etching process, opening part of the hard mask layer outside the groove, and enabling the top angle of the hard mask layer to be smooth.
Optionally, the hard mask layer is subjected to pullback at least once.
Optionally, the hard mask layer and the pad oxide layer on the surface of the substrate are subjected to wet etching treatment. And performing pullback on the hard mask layer on the surface of the substrate by a wet etching process, performing pullback on the pad oxide layer by the wet etching process, opening part of the hard mask layer and part of the pad oxide layer outside the groove to expose the silicon substrate, and smoothening the top angle of the hard mask layer.
Optionally, the hard mask layer is subjected to pullback at least once, and the pad oxide layer is subjected to pullback at least once. Such as: the hard mask layer is subjected to pullback twice, and then the pad oxide layer is subjected to pullback once.
In step 204, an oxide layer is grown by an ISSG process.
An oxide layer 25 is formed on the substrate 21 by an ISSG (in-situ steam generation) process, as shown in fig. 5.
In step 205, the oxide layer is removed to expose the substrate surface outside the trench.
The oxide layer is removed by a wet etching process, the sidewalls and bottom of the trench are not covered with the oxide layer, and at the same time, the substrate surface outside the trench is exposed, as shown in fig. 6.
It should be noted that if the pad oxide layer under the opened hard mask layer is not removed in step 203, the pad oxide layer and the oxide layer 25 under the opened hard mask layer are removed in this step.
In step 206, an oxide layer is formed again by the ISSG process, the sidewalls and bottom of the trench are covered with the oxide layer, and the top corners of the trench are rounded.
In step 207, a silicon nitride layer is formed on the surface of the oxide layer.
Alternatively, a silicon nitride layer 27 is deposited on the surface of the oxide layer 26 by a deposition process, as shown in fig. 8.
Optionally, a silicon nitride layer 27 is grown on the surface of the oxide layer 26 by a thermal furnace process, as shown in fig. 8.
In step 208, silicon oxide is deposited by an HDP process, and the trench is completely filled with silicon oxide to form shallow trench isolation.
In step 209, a CMP process is performed on the substrate.
And after the shallow trench isolation is formed, performing CMP (chemical mechanical polishing) treatment on the substrate to remove redundant silicon oxide on the surface of the substrate.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method for forming shallow trench isolation, the method comprising:
forming a pad oxide layer and a hard mask layer on a substrate, wherein the hard mask layer is made of silicon nitride;
forming a groove in the substrate through photoetching and etching processes;
carrying out wet etching treatment on the substrate, removing part of the hard mask layer outside the groove and smoothing the top angle of the hard mask layer;
forming an oxide layer, wherein the side wall and the bottom of the trench are covered by the oxide layer;
removing the oxide layer to expose the surface of the substrate outside the groove;
forming an oxide layer again, wherein the side wall and the bottom of the groove are covered by the oxide layer, and the top angle of the groove is smooth;
forming a silicon nitride layer, wherein the silicon nitride layer covers the oxide layer;
and filling the groove with silicon oxide to form shallow groove isolation.
2. The method of claim 1, wherein said subjecting said substrate to a wet etch process comprises:
and carrying out wet etching treatment on the hard mask layer on the surface of the substrate.
3. The method of claim 1, wherein said subjecting said substrate to a wet etch process comprises:
and carrying out wet etching treatment on the hard mask layer and the pad oxide layer on the surface of the substrate.
4. The method of claim 1, wherein the forming an oxide layer comprises:
and growing an oxide layer by an ISSG process.
5. The method of claim 1, wherein the forming a silicon nitride layer comprises:
and forming a silicon nitride layer on the surface of the oxide layer by a deposition process or a heat furnace tube process.
6. The method of claim 1, wherein said filling said trench with silicon oxide to form shallow trench isolation comprises:
and depositing silicon oxide by an HDP (high-density plasma) process, and completely filling the groove by using the silicon oxide to form shallow trench isolation.
7. The method of claim 1, wherein the removing the oxide layer to expose the substrate surface outside the trench comprises:
and removing the oxide layer through a wet etching process to expose the surface of the substrate outside the groove.
8. The method of any of claims 1 to 7, wherein after the filling the trench with silicon oxide to form shallow trench isolation, the method further comprises:
and carrying out CMP treatment on the substrate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114864480A (en) * | 2022-07-05 | 2022-08-05 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020060910A (en) * | 2001-01-13 | 2002-07-19 | 삼성전자 주식회사 | Method for forming a trench isolation of semiconductor devices |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020060910A (en) * | 2001-01-13 | 2002-07-19 | 삼성전자 주식회사 | Method for forming a trench isolation of semiconductor devices |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114864480A (en) * | 2022-07-05 | 2022-08-05 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN114864480B (en) * | 2022-07-05 | 2022-10-21 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
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