KR100328265B1 - Shallow trench isolation manufacturing method of semiconductor devices - Google Patents
Shallow trench isolation manufacturing method of semiconductor devices Download PDFInfo
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- KR100328265B1 KR100328265B1 KR1019990020272A KR19990020272A KR100328265B1 KR 100328265 B1 KR100328265 B1 KR 100328265B1 KR 1019990020272 A KR1019990020272 A KR 1019990020272A KR 19990020272 A KR19990020272 A KR 19990020272A KR 100328265 B1 KR100328265 B1 KR 100328265B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000002955 isolation Methods 0.000 title abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 27
- 230000008021 deposition Effects 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 3
- 238000005429 filling process Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000000926 separation method Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
반도체 소자 분리를 위한 트렌치 제조 공정을 간단하게 하며, 그에 따라 종래 각 공정에서 발생할 수 있는 제반 문제점을 효과적으로 방지하기 위하여, 반도체 기판 상부에 반도체 소자 분리를 위한 트렌치 높이의 산화막을 형성하고, 그 상부에 트렌치 패턴을 형성하고, 이를 마스크로 드러난 산화막을 식각한다. 그리고, 트렌치 패턴을 제거하고, 드러난 반도체 기판 상부에 반도체 소자가 형성될 에피 실리콘을 증착한 후, 반도체 기판 전면에 반도체 소자의 임계 전압 조정 등을 위한 이온 주입을 하여 반도체 소자 분리를 위한 트렌치를 제조하는 것으로, 반도체 소자의 격리를 위한 산화막 패턴을 형성한 후, 에피 실리콘 증착에 의해 반도체 소자가 형성될 활성 영역을 형성함으로써 종래 모트 식각 공정, 트렌치 매입 공정, 리벌스 모트 식각 공정, 화학 기계적 연마에 의한 평탄화 공정 등을 생략하여 트렌치 제조 공정을 간단히 할 뿐만 아니라 그에 따라 각 공정에서 발생되었던 문제를 원천적으로 제거할 수 있으며, 에피 실리콘 증착에 의해 트렌치 깊이를 반도체 기판 전면에서 균일하게 하며, 트렌치 상부 폭이 하부 폭보다 좁게 형성하여 반도체 소자가 형성될 활성 영역을 넓게하여 집적도를 높인다.In order to simplify the trench fabrication process for semiconductor device isolation, and to effectively prevent various problems that may occur in each conventional process, an oxide film having a trench height for semiconductor device isolation is formed on the semiconductor substrate, and on the upper portion thereof. A trench pattern is formed, and the oxide film exposed by the mask is etched. Then, the trench is removed, the epitaxial silicon on which the semiconductor device is to be formed is deposited on the exposed semiconductor substrate, and ion implantation is performed on the entire surface of the semiconductor substrate to adjust the threshold voltage of the semiconductor device, thereby manufacturing a trench for semiconductor device isolation. By forming an oxide film pattern for isolation of the semiconductor device, and then forming an active region in which the semiconductor device is to be formed by epi silicon deposition, the conventional mort etching process, trench filling process, rivals mort etching process, chemical mechanical polishing By eliminating the planarization process and the like, the trench manufacturing process can be simplified and the problems caused in each process can be eliminated at the source, and the trench depth is uniformized on the entire surface of the semiconductor substrate by epi silicon deposition. It is formed narrower than the lower width so that the semiconductor device Broadly be the active region to increase the degree of integration.
Description
본 발명은 반도체 소자 분리를 위한 트렌치를 제조하는 방법에 관한 것으로, 더욱 상세하게는 반도체 집적회로 등의 반도체 소자를 제조하는 공정 중 실리콘웨이퍼에 각 반도체 소자를 전기적으로 격리하기 위한 트렌치를 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a trench for semiconductor device isolation, and more particularly, to a trench for electrically isolating each semiconductor device from a silicon wafer during a process of manufacturing a semiconductor device such as a semiconductor integrated circuit. It is about.
일반적으로 반도체 소자를 분리하는 방법으로는 선택적 산화법으로 질화막을 이용하는 LOCOS(local oxidation of silicon) 소자 분리 방법이 이용되어 왔다.In general, a method of separating a semiconductor device has been used a local oxidation of silicon (LOCOS) device separation method using a nitride film as a selective oxidation method.
LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘웨이퍼 자체를 열 산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 큰 이점이 있다.Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is a great advantage that the device stress problem of the oxide film is small, and the oxide film produced is good.
그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생하게 된다.However, when the LOCOS device isolation method is used, the area occupied by the device isolation region is not only limited in miniaturization but also causes a bird's beak.
이러한 것을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(STI ; shallow trench isolation)가 있다. 트렌치 소자 분리에서는 실리콘웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리하다.In order to overcome this, a trench trench isolation (STI) technique is an alternative to the LOCOS isolation scheme. In trench device isolation, since trenches are made in silicon wafers to insulate the insulating material, the area occupied by device isolation regions is small, which is advantageous for miniaturization.
그러면, 이러한 반도체 소자 분리를 위한 트렌치를 제조하는 종래의 방법을 첨부된 도 1a 내지 도 1c를 참조하여 설명한다.Then, a conventional method of manufacturing a trench for separating such semiconductor devices will be described with reference to FIGS. 1A to 1C.
먼저 도 1a에 도시한 바와 같이, 반도체 기판(1) 상부에 에피택셜 증착에 의해 반도체 소자가 형성될 에피 실리콘층(2)을 형성한다. 그리고, 반도체 기판(1)을 열산화하여 에피 실리콘층(2) 상부에 패드 산화막(3)을 형성하고, 그 상부에 화학 기상 증착(chemical vapor deposition, CVD)에 의해 질화막(4)을 증착한다. 이후, 질화막(4) 상부에 트렌치 식각을 위한 모트(moat) 패턴(5)을 형성하고, 모트 패턴(5)을 마스크로 드러난 질화막(4)을 식각하여 제거하고, 다시 드러난 패드 산화막(3)과 에피 실리콘층(2)을 일정 깊이로 식각하여 반도체 소자 분리 영역에 트렌치를 형성한다.First, as shown in FIG. 1A, an epitaxial silicon layer 2 on which a semiconductor device is to be formed is formed on the semiconductor substrate 1 by epitaxial deposition. The semiconductor substrate 1 is thermally oxidized to form a pad oxide film 3 on the epitaxial silicon layer 2, and the nitride film 4 is deposited on the upper layer by chemical vapor deposition (CVD). . Thereafter, a moat pattern 5 for trench etching is formed on the nitride layer 4, the nitride layer 4 exposed by the mask is removed by etching, and the pad oxide layer 3 exposed again. And the epi silicon layer 2 are etched to a predetermined depth to form a trench in the semiconductor device isolation region.
그 다음 도 1b에 도시한 바와 같이, 모트 패턴을 제거하고, 에피 실리콘층(2)을 열산화하여 트렌치 내벽에 라이너(liner) 산화막(6)을 형성한다. 이후, 에피 실리콘층(2) 전면에 화학 기상 증착에 의해 NSG(non-doped silica glass), TEOS(tetraethylorthosilicate)막 등의 절연막(7)을 증착하여 트렌치를 매입한다. 그리고, 트렌치 식각시 사용된 모트 패턴과 반대 형상의 패턴 즉, 리벌스(reverse) 모트 패턴을 절연막(7) 상부에 형성하고, 이를 마스크로 드러난 질화막(4) 상부의 절연막을 식각하여 제거한 후, 리벌스 모트 패턴을 제거한다.Next, as shown in FIG. 1B, the mott pattern is removed, and the epi silicon layer 2 is thermally oxidized to form a liner oxide film 6 on the inner wall of the trench. Subsequently, an insulating film 7 such as non-doped silica glass (NSG) or tetraethylorthosilicate (TEOS) film is deposited on the epi silicon layer 2 by chemical vapor deposition to fill the trench. Then, a pattern having a shape opposite to that of the mort pattern used in the trench etching, that is, a reverse mort pattern is formed on the insulating layer 7, and the insulating layer on the nitride layer 4 exposed as a mask is etched and removed. Remove the Reval's Mort pattern.
그 다음 도 1c에 도시한 바와 같이, 질화막을 버퍼층으로 에피 실리콘층(2) 전면을 화학 기계적 연마(Chemical mechanical polishing, CMP)하여 패터닝된 산화막(7)을 평탄화한다. 그리고, 습식 식각을 통해 에피 실리콘층(2)의 활성화 영역 즉, 반도체 소자가 형성될 영역에 잔류하는 질화막을 제거한 후, 반도체 소자의 임계 전압 조정 등을 위한 이온 주입을 실시함으로써 반도체 소자 분리를 위한 트렌치를 완성한다.1C, the patterned oxide film 7 is planarized by chemical mechanical polishing (CMP) of the entire surface of the epi silicon layer 2 using the nitride film as the buffer layer. Then, the nitride layer remaining in the active region of the epi silicon layer 2, that is, the region where the semiconductor element is to be formed, is removed by wet etching, and then ion implantation is performed to adjust the threshold voltage of the semiconductor element. Complete the trench.
이와 같은 종래의 반도체 소자 분리를 위한 트렌치를 제조하는 방법은 모트 식각 공정, 트렌치 매입 공정, 리벌스 모트 공정, 화학 기계적 연마 공정 등의 사용으로 제조 공정이 복잡하며, 그 제조 시간이 많이 소요된다.The conventional method of manufacturing a trench for semiconductor device isolation is complicated by the use of a mort etching process, a trench embedding process, a rivals mort process, a chemical mechanical polishing process, and the manufacturing process is time consuming.
또한, 모트 식각시 에피 실리콘이 식각되어지는 선폭(critical dimension, CD)이 질화막 마스크에 의해 결정되어질 뿐만 아니라 식각되는 실리콘(에피 실리콘)의 깊이가 균일하게 형성되지 않으며, 리벌스 모트 식각시 질화막 상부의 산화막이 균일하게 제거되지 않으므로 후속 화학 기계적 연마 공정 진행시 파티클 소스로 작용하는 등 각 공정에서 많은 문제점이 발생하므로 반도체 소자 제조 공정의 수율을 저감시키고 있다.In addition, not only the critical dimension (CD) in which epi silicon is etched during mort etching is determined by the nitride mask, but also the depth of silicon (epi silicon) to be etched is not uniformly formed. Since the oxide film is not uniformly removed, many problems occur in each process, such as acting as a particle source during the subsequent chemical mechanical polishing process, thereby reducing the yield of the semiconductor device manufacturing process.
본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 반도체 소자 분리를 위한 트렌치 제조 공정을 간단하게 하며, 그에 따라 종래 각 공정에서 발생할 수 있는 제반 문제점을 효과적으로 방지할 수 있도록 하는 데 있다.The present invention is to solve such a problem, the object is to simplify the trench manufacturing process for semiconductor device separation, thereby effectively preventing all the problems that can occur in each conventional process.
도 1a 내지 도 1c는 종래 반도체 소자 분리를 위한 트렌치 제조하는 방법을 도시한 공정도이고,1A to 1C are flowcharts illustrating a method of manufacturing a trench for separating a conventional semiconductor device,
도 2a와 도 2b는 본 발명에 따라 반도체 소자 분리를 위한 트렌치 제조하는 방법을 도시한 공정도이다.2A and 2B are process diagrams illustrating a method of manufacturing a trench for semiconductor device isolation in accordance with the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 반도체 기판 상부에 반도체 소자 분리를 위한 트렌치 높이의 산화막을 형성하고, 트렌치 패턴을 마스크로 식각한 다음, 드러난 반도체 기판 상부에 반도체 소자가 형성될 에피 실리콘을 증착하고, 반도체 소자의 임계 전압 조정 등을 위한 이온 주입을 하여 반도체 소자 분리를 위한 트렌치를 제조하는 것을 특징으로 한다.In order to achieve the above object, the present invention forms an oxide film having a trench height for semiconductor device isolation on the semiconductor substrate, and etching the trench pattern with a mask, and then the epi silicon on which the semiconductor device is formed on the exposed semiconductor substrate. And depositing ion and implanting an ion for adjusting a threshold voltage of the semiconductor device, thereby manufacturing a trench for semiconductor device separation.
상기에서 산화막은 반도체 기판의 열산화 또는 화학 기상 증착, PE TEOS에 의해 형성하며, 산화막의 식각은 트렌치 패턴에 대해 수직적인 식각 또는 슬로프 식각으로 실시하는 것이 바람직하다.The oxide film is formed by thermal oxidation or chemical vapor deposition, PE TEOS of the semiconductor substrate, and the etching of the oxide film is preferably performed by etching or slope etching perpendicular to the trench pattern.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a와 도 2b는 본 발명에 따라 반도체 소자 분리를 위한 트렌치를 제조하는 방법을 도시한 공정도이다.2A and 2B are process diagrams illustrating a method of manufacturing a trench for semiconductor device isolation in accordance with the present invention.
먼저 도 2a에 도시한 바와 같이, 실리콘웨이퍼 등의 반도체 기판(11) 상부에 반도체 소자 분리를 위한 절연물로 이용하기 위한 산화막(12)을 반도체 소자 분리를 위한 트렌치 높이까지 형성한다. 이때, 산화막(12)은 반도체 기판(11)인 실리콘웨이퍼를 열산화하여 성장하거나, 화학 기상 증착에 의해 증착한다. 또한, 산화막(12)을 PE(plasma enhanced) TEOS막으로 형성할 수도 있다.First, as shown in FIG. 2A, an oxide film 12 is formed on the semiconductor substrate 11, such as a silicon wafer, to form a trench for separating semiconductor devices. At this time, the oxide film 12 is grown by thermally oxidizing a silicon wafer, which is the semiconductor substrate 11, or deposited by chemical vapor deposition. In addition, the oxide film 12 may be formed of a PE (plasma enhanced) TEOS film.
이후, 산화막(12) 상부에 트렌치 패턴(13)을 형성한다. 일예로 산화막 상부에 포지티브 감광막을 도포하고, 트렌치 패턴이 형성된 마스크로 감광막을 노광 현상하여 트렌치 패턴을 형성한다. 그리고, 트렌치 패턴(13)을 마스크로 드러난 산화막(12)을 식각하여 제거한다. 이때 산화막(12)의 식각은 일반적인 식각 공정에 의해 수직적으로 할 수 있으며, 특히 슬로프(slope) 식각으로 산화막(12)을 식각하면 트렌치 사이의 산화막(12)은 상부 폭보다 하부 폭이 넓게 형성되므로 소자 간의 격리를 보다 확실히 할 수 있을 뿐만 아니라 종래에 비해 반도체 소자가 형성될 활성 영역을 넓게 하여 집적도를 높일 수 있다.Thereafter, a trench pattern 13 is formed on the oxide film 12. For example, a positive photosensitive film is coated on the oxide film, and the photosensitive film is exposed to light with a mask having a trench pattern to form a trench pattern. Then, the oxide film 12 exposed through the trench pattern 13 as a mask is etched and removed. In this case, the oxide layer 12 may be etched vertically by a general etching process. In particular, when the oxide layer 12 is etched by the slope etching, the oxide layer 12 between the trenches may have a lower width than the upper width. Not only can isolation between devices be more secure, but also the integration degree can be increased by widening the active area in which semiconductor devices are to be formed.
그 다음 도 2b에 도시한 바와 같이, 식각된 산화막(12) 상부에 잔류하는 트렌치 패턴을 제거하고, 반도체 기판(11)을 세정한 후, 드러난 반도체 기판(11) 상부에 에피 실리콘(14)을 성장시켜 반도체 소자가 형성될 활성 영역을 형성한다.Next, as shown in FIG. 2B, the trench pattern remaining on the etched oxide film 12 is removed, the semiconductor substrate 11 is cleaned, and epi silicon 14 is then deposited on the exposed semiconductor substrate 11. Growing to form an active region in which the semiconductor device will be formed.
이때, 에피 실리콘 성장의 일예를 들면, 용제로 반도체 기판의 지방성분을 제거한 다음, 여러 종류의 산으로 세척하여 건조시킨다. 그리고, 반도체 기판을 에피택셜 시스템에 장입한 후, 시스템 내부의 잔류기체를 질소기체로 청정시킨 다음, 반응로의 가열장치를 동작시킨다. 이때, 시스템내의 기체로는 약 500℃까지는 질소를 사용하며 온도가 더 높아져서 질소가 실리콘을 부식시킬 정도에 이르면 질소기체 대신 수소기체를 사용한다. 그리고, 가열과정이 끝나면 염산을 사용하여 반도체 기판 표면의 손상된 실리콘층을 제거한 후, 진공 증착, 증발 성장 또는 4염화실리콘의 수소환원 등의 방법으로 에피 실리콘을 증착한다. 이때, 증착 두께는 산화막(12)의 높이보다 같거나 조금 낮게 하는 것이 바람직하다.At this time, as an example of epi silicon growth, the fat component of the semiconductor substrate is removed with a solvent, and then washed with various kinds of acids and dried. After charging the semiconductor substrate into the epitaxial system, the remaining gas in the system is cleaned with nitrogen gas, and then the heating device of the reactor is operated. In this case, nitrogen is used as a gas in the system up to about 500 ° C., and when the temperature is higher and nitrogen reaches the degree of corrosive silicon, hydrogen gas is used instead of nitrogen gas. After the heating process, the damaged silicon layer on the surface of the semiconductor substrate is removed using hydrochloric acid, and then epi silicon is deposited by vacuum deposition, evaporation growth, or hydrogen reduction of silicon tetrachloride. At this time, the deposition thickness is preferably equal to or slightly lower than the height of the oxide film 12.
이후, 반도체 기판 전면에 반도체 소자의 임계 전압 조정 등을 위한 이온 주입을 실시함으로써 반도체 소자 분리를 위한 트렌치를 완성한다.Thereafter, an ion implantation is performed on the entire surface of the semiconductor substrate to adjust the threshold voltage of the semiconductor device, thereby completing the trench for semiconductor device isolation.
이와 같이 본 발명은 반도체 소자를 격리하는 트렌치를 매입하기 위한 산화막 패턴을 형성한 후, 에피 실리콘 증착에 의해 반도체 소자가 형성될 활성 영역을 형성함으로써 종래 모트 식각 공정, 트렌치 매입 공정, 리벌스 모트 식각 공정, 화학 기계적 연마에 의한 평탄화 공정 등을 생략하여 트렌치 제조 공정을 간단히 할 수 있으며, 그에 따라 각 공정에서 발생되었던 문제를 원천적으로 제거할 수 있을 뿐만 아니라 에피 실리콘 증착에 의해 트렌치 깊이를 반도체 기판 전면에서 균일하게 할 수 있으며, 트렌치 사이의 산화막 모양을 상부 폭이 하부 폭보다 좁게 형성하여 반도체 소자가 형성될 활성 영역을 넓게 하여 집적도를 높일 수 있다.As described above, the present invention forms an oxide layer pattern for embedding a trench to isolate a semiconductor device, and then forms an active region where a semiconductor device is to be formed by epi silicon deposition, thereby forming a conventional mort etching process, a trench embedding process, and a reversal mort etching. It is possible to simplify the trench fabrication process by omitting the process and the planarization process by chemical mechanical polishing, thereby not only eliminating the problems caused in each process, but also reducing the depth of the trench by epi silicon deposition. The thickness of the oxide film between the trenches may be uniform, and the upper width is narrower than the lower width, thereby widening the active area in which the semiconductor device is to be formed, thereby increasing the degree of integration.
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| JPS6060734A (en) * | 1983-09-14 | 1985-04-08 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS6298742A (en) * | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0621204A (en) * | 1992-07-02 | 1994-01-28 | Nippon Steel Corp | Manufacture of semiconductor device, and semiconductor device |
| JPH10313049A (en) * | 1997-05-13 | 1998-11-24 | Sony Corp | Semiconductor device and manufacture of the same |
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| JPS6060734A (en) * | 1983-09-14 | 1985-04-08 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS6298742A (en) * | 1985-10-25 | 1987-05-08 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0621204A (en) * | 1992-07-02 | 1994-01-28 | Nippon Steel Corp | Manufacture of semiconductor device, and semiconductor device |
| JPH10313049A (en) * | 1997-05-13 | 1998-11-24 | Sony Corp | Semiconductor device and manufacture of the same |
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