KR100276124B1 - Formation method of mos transistor using trench - Google Patents
Formation method of mos transistor using trench Download PDFInfo
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- KR100276124B1 KR100276124B1 KR1019990002269A KR19990002269A KR100276124B1 KR 100276124 B1 KR100276124 B1 KR 100276124B1 KR 1019990002269 A KR1019990002269 A KR 1019990002269A KR 19990002269 A KR19990002269 A KR 19990002269A KR 100276124 B1 KR100276124 B1 KR 100276124B1
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 title claims description 3
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000007517 polishing process Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 15
- 238000000206 photolithography Methods 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims 3
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
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Abstract
반도체 소자의 제조 공정중 트렌치를 이용한 모스 트랜지스터의 제조 방법에 관한 것으로, 트렌치를 이용한 모스 트랜지스터를 제조하는 공정에 있어서, 화학 기계적 연마 공정후 질화막을 두께 500 ~ 3000Å으로 증착하고 에치 백(etch back)하여 트렌치의 가장자리 부분에 질화막을 남게 하여 트렌치와 엑티브 영역을 분리함으로써, 트렌치에서 누설 전류나 쇼트가 발생하는 것을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있다.The present invention relates to a method of manufacturing a MOS transistor using a trench during a manufacturing process of a semiconductor device. In the process of manufacturing a MOS transistor using a trench, a nitride film is deposited to a thickness of 500 to 3000 GPa after a chemical mechanical polishing process and etch back. Thus, the nitride film is left at the edge of the trench to separate the trench from the active region, thereby preventing leakage current or short from occurring in the trench, thereby improving reliability of the semiconductor device.
Description
본 발명은 반도체 소자의 제조 공정에 관한 것으로, 보다 상세하게는 반도체 소자의 제조 공정중 트렌치를 이용한 모스 트랜지스터의 제조 방법에 관한 것이다.The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a manufacturing method of a MOS transistor using a trench during a manufacturing process of a semiconductor device.
일반적으로 모스 트랜지스터(MOS transistor) 제조시 소자 분리 방법으로 LOCOS(local oxidation of silicon) 소자 분리가 이용되어 왔다. LOCOS는 질화막을 마스크로 해서 실리콘 웨이퍼 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 큰 이점이 있다.In general, local oxidation of silicon (LOCOS) device isolation has been used as a device isolation method in manufacturing a MOS transistor. Since LOCOS thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple, and there is a big advantage that the element stress problem of the oxide film is small, and that the resulting oxide film quality is good.
그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생한다.However, when the LOCOS device isolation method is used, the area occupied by the device isolation region is not only limited in miniaturization but also causes bird's beak.
이러한 것을 극복하기 위해 LOCOS를 대체하는 소자 분리 기술로서 트렌치 소자 분리가 있다.To overcome this, trench isolation is a device isolation technology that replaces LOCOS.
트렌치 소자 분리 방법은 반응성 이온 에칭(RIE ; reactive ion etching)이나 플라즈마 에칭과 같은 건식 에칭 기술을 사용하여 좁고 깊은 트렌치를 만들고, 그 속에 산화막을 채우는 방법으로 실리콘 웨이퍼에 트렌치를 만들어 절연물을 집어 넣기 때문에 버즈 비크와 관련된 문제가 없어진다. 또한, 채워진 트렌치는 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리한 방법이다.The trench isolation method uses a dry etching technique such as reactive ion etching (RIE) or plasma etching to form narrow and deep trenches and fills the insulator with trenches in the silicon wafer by filling oxides therein. The problem with Buzz Beek is eliminated. In addition, since the filled trench is flat, the area occupied by the device isolation region is small, which is advantageous for miniaturization.
그러면, 트렌치를 이용한 모스 트랜지스터를 제조하는 종래의 방법을 첨부된 도 1a 내지 도 1d를 참조하여 설명한다.Next, a conventional method of manufacturing a MOS transistor using a trench will be described with reference to FIGS. 1A to 1D.
먼저, 도 1a에 도시된 바와 같이, 실리콘 웨이퍼(1)를 열산화하여 패드 산화막(2)을 열성장시키고, 그 상부에 질화막(3)을 증착한다. 그리고, 포토리소그래피(photolithography) 공정에 의해 질화막(3)과 패드 산화막(2)을 선택적으로 식각하여 제거하고, 드러난 실리콘 웨이퍼(1)를 일정 깊이로 식각하여 실리콘 웨이퍼(1)의 소자 분리 영역에 트렌치를 형성한다. 이후, 트렌치가 형성된 실리콘 웨이퍼(1)를 세정하고, 트렌치의 소자 분리 특성을 강화하기 위하여 실리콘 웨이퍼(1)를 열산화하여 트렌치의 내벽에 라이너(liner) 산화막(4)을 성장시킨다.First, as shown in FIG. 1A, the silicon wafer 1 is thermally oxidized to thermally grow the pad oxide film 2, and the nitride film 3 is deposited thereon. Then, the nitride film 3 and the pad oxide film 2 are selectively etched and removed by a photolithography process, and the exposed silicon wafer 1 is etched to a predetermined depth to the device isolation region of the silicon wafer 1. Form a trench. Thereafter, the silicon wafer 1 having the trench formed therein is cleaned and the silicon wafer 1 is thermally oxidized to enhance the device isolation characteristics of the trench, thereby growing a liner oxide film 4 on the inner wall of the trench.
그리고, 실리콘 웨이퍼(1) 전면에 산화막(5)을 두껍게 증착하여 트렌치(4)를 매립하고, 포토리소그래피 공정에 의해 산화막(5)을 선택적으로 식각하여 실리콘 웨이퍼(1)의 트렌치 영역 및 그 상부에만 산화막(5)이 남도록 한다.Then, the oxide film 5 is thickly deposited on the entire surface of the silicon wafer 1 to fill the trench 4, and the oxide film 5 is selectively etched by a photolithography process to form a trench region of the silicon wafer 1 and an upper portion thereof. Only the oxide film 5 remains.
그 다음, 도 1b에 도시된 바와 같이, 화학 기계적 연마(CMP ; chemical mechanical polishing) 공정에 의해 산화막(5)의 상부가 질화막(3) 상부와 평행이 되도록 평탄화하고, 질화막(3)과 실리콘 웨이퍼 표면에 남아 있는 패드 산화막(2)을 순차적으로 제거한다.Then, as shown in FIG. 1B, the upper portion of the oxide film 5 is planarized so as to be parallel to the upper portion of the nitride film 3 by a chemical mechanical polishing (CMP) process, and the nitride film 3 and the silicon wafer are The pad oxide film 2 remaining on the surface is sequentially removed.
그 다음, 도 1c에 도시된 바와 같이, 소자 분리 영역이 정의된 실리콘 웨이퍼(1)의 모스 트랜지스터 영역에 게이트 산화막(6)을 열성장시키고, 그 상부에 폴리 실리콘(poly Si)(7)을 증착시킨다. 그리고, 포토리소그래피 공정에 의해 게이트 영역을 제외한 부분의 폴리 실리콘을 제거하고, 게이트를 마스크로 하여 소소/드레인 형성을 위한 불순물을 이온 주입을 한 후, 산화막(6)을 제거하여 실리콘 웨이퍼를 노출시킨다.Then, as shown in FIG. 1C, the gate oxide film 6 is thermally grown in the MOS transistor region of the silicon wafer 1 in which the device isolation region is defined, and polysilicon 7 is deposited on top thereof. Deposit. Then, the polysilicon in the portion excluding the gate region is removed by a photolithography process, an ion implanted with impurities for forming a source / drain using the gate as a mask, and then the oxide film 6 is removed to expose the silicon wafer. .
그 다음, 도 1d에 도시된 바와 같이, 실리콘 웨이퍼(1) 전면에 티타늄, 티타늄/질화티타늄 등의 실리사이드(8) 형성을 위한 박막을 증착하고, 실리사이드(8) 형성에 이용되지 않고 잔류하는 박막을 제거한다. 그리고, 절연막(9)을 형성하고, 금속막과 소스/드레인 또는 게이트의 소자 전극 연결을 위해 포토리소그래피 공정에 의해 절연막(9)을 식각한 후, 금속막(10)을 증착한다.Next, as shown in FIG. 1D, a thin film for forming silicide 8, such as titanium and titanium / titanium nitride, is deposited on the entire surface of the silicon wafer 1, and the remaining thin film is not used for forming the silicide 8. Remove it. Then, the insulating film 9 is formed, the insulating film 9 is etched by a photolithography process for connecting the metal film and the device electrode of the source / drain or the gate, and then the metal film 10 is deposited.
이와 같이 종래의 방법에 의해 트렌치를 이용한 모스 트랜지스터의 제조하면 게이트 형성을 위한 폴리 실리콘 식각시 폴리 실리콘이나, 실리사이드를 형성시 실리사이드가 트렌치의 가장자리 부분에 남는 경우에 누설 전류(leakage current)나 쇼트(short)가 발생할 수 있다.As described above, when a MOS transistor using a trench is manufactured by a conventional method, when the polysilicon is etched to form a gate, polysilicon may be formed, or when silicide is formed at the edge of the trench, leakage current or short ( short) may occur.
또한, 엑티브와 필드 사이가 작아지면서 콘택 공정에서도 누설 전류가 발생하는 문제점이 있다.In addition, there is a problem in that leakage current occurs in the contact process as the active and the field become smaller.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 트렌치와 엑티브 영역을 분리함으로써 누설 전류와 쇼트가 발생하는 것을 방지하는 데 있다.The present invention has been made to solve such a problem, and its object is to prevent leakage current and short from occurring by separating the trench and the active region.
도 1a 내지 도 1d는 종래의 트렌치를 이용한 모스 트랜지스터 제조 방법을 도시한 공정도이고,1A to 1D are process diagrams illustrating a MOS transistor manufacturing method using a conventional trench,
도 2a 내지 도 2d는 본 발명에 따른 트렌치를 이용한 모스 트랜지스터 제조 방법을 도시한 공정도이다.2A to 2D are process diagrams illustrating a MOS transistor manufacturing method using trenches according to the present invention.
상기와 같은 목적을 달성하기 위하여, 본 발명은 트렌치를 이용한 모스 트랜지스터를 제조하는 공정에 있어서, 화학 기계적 연마 공정후 질화막을 증착하고 에치 백(etch back)하여 트렌치의 가장자리 부분에 질화막을 남게 하여 트렌치와 엑티브 영역을 분리하는 것을 특징으로 한다.In order to achieve the above object, the present invention in the process of manufacturing a MOS transistor using a trench, after the chemical mechanical polishing process by depositing a nitride film and etch back (etch back) to leave a nitride film on the edge of the trench trench And the active region is separated.
상기 질화막의 두께는 500 ~ 3000Å으로 하는 것이 바람직하다.It is preferable that the thickness of the said nitride film is 500-3000 GPa.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따라 트렌치를 이용한 모스 트랜지스터의 제조 방법을 도시한 공정도이다.2A to 2D are flowcharts illustrating a method of manufacturing a MOS transistor using trenches according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 실리콘 웨이퍼(11)를 열산화하여 패드 산화막(12)을 열성장시키고, 그 상부에 화학 기상 증착법(CVD ; chemical vapor deposition)에 의해 질화막(13)을 증착한다. 그리고, 포토리소그래피 공정에 의해 질화막(13)과 패드 산화막(12)을 선택적으로 식각하여 제거하고, 드러난 실리콘 웨이퍼(11)를 일정 깊이로 식각하여 실리콘 웨이퍼(11)의 소자 분리 영역에 트렌치를 형성한다. 이후, 트렌치가 형성된 실리콘 웨이퍼(11)를 세정하고, 트렌치의 소자 분리 특성을 강화하기 위하여 실리콘 웨이퍼(11)를 열산화하여 트렌치의 내벽에 라이너 산화막(14)을 성장시킨다.First, as shown in FIG. 2A, the silicon oxide wafer 11 is thermally oxidized to thermally grow the pad oxide film 12, and the nitride film 13 is deposited on top thereof by chemical vapor deposition (CVD). do. The nitride film 13 and the pad oxide film 12 are selectively etched and removed by a photolithography process, and the exposed silicon wafer 11 is etched to a predetermined depth to form trenches in the device isolation region of the silicon wafer 11. do. Subsequently, the silicon wafer 11 having the trench formed therein is cleaned, and the silicon wafer 11 is thermally oxidized to enhance the device isolation characteristics of the trench, thereby growing the liner oxide layer 14 on the inner wall of the trench.
그리고, 실리콘 웨이퍼(11) 전면에 상압 화학 기상 증착법(APCVD ; atmospheric pressure chemical vapor deposition)에 의해 산화막(15)을 두껍게 증착하여 트렌치(14)를 매립하고, 포토리소그래피 공정에 의해 산화막(15)을 선택적으로 식각하여 실리콘 웨이퍼(11)의 트렌치 영역 및 그 상부에만 산화막(15)이 남도록 한다.The oxide film 15 is thickly deposited on the entire surface of the silicon wafer 11 by atmospheric pressure chemical vapor deposition (APCVD) to fill the trench 14, and the oxide film 15 is formed by a photolithography process. It is selectively etched so that the oxide film 15 remains only in the trench region and the upper portion of the silicon wafer 11.
그 다음, 도 2b에 도시된 바와 같이, 화학 기계적 연마 공정에 의해 산화막(15)의 상부가 질화막(13) 상부와 평행이 되도록 평탄화하고, 질화막(13)을 습식 식각에 의해 제거한 후, 실리콘 웨이퍼 표면에 남아 있는 패드 산화막(12)을 습식 세정하여 제거한다. 그리고, 퍼니스(furnace)에서 온도 500 ~ 800℃로 5 ~ 60min 동안 실시하여 실리콘 웨이퍼(11)의 전면에 질화막(16)이 두께 500 ~ 3000Å가 형성되도록 한다.Next, as shown in FIG. 2B, the upper portion of the oxide film 15 is planarized so as to be parallel to the upper portion of the nitride film 13 by a chemical mechanical polishing process, and the nitride film 13 is removed by wet etching, followed by a silicon wafer. The pad oxide film 12 remaining on the surface is removed by wet cleaning. In the furnace, the temperature is 500 to 800 ° C. for 5 to 60 minutes to form a nitride film 16 having a thickness of 500 to 3000 μm on the entire surface of the silicon wafer 11.
그 다음, 도 2c에 도시된 바와 같이, 마스크 없이 플라즈마 식각에 의해 전면 식각(etch back)을 하부 산화막이 노출될 때까지 실시하여 트렌치의 가장자리 부분에 질화막(16)이 남도록 한다. 이 질화막(16)은 트렌치와 엑티브 영역을 분리함으로써 누설 전류나 쇼트와 같은 문제점을 방지하는 역할을 한다. 그리고, 소자 분리 영역이 정의된 실리콘 웨이퍼(11)의 모스 트랜지스터 영역에 게이트 산화막(17)을 열성장시키고, 그 상부에 폴리 실리콘(18)을 화학 기상 증착법에 의해 증착시킨다. 이후, 포토리소그래피 공정에 의해 게이트 영역을 제외한 부분의 폴리 실리콘을 플라즈마 식각에 의해 제거하고, 게이트를 마스크로 하여 소소/드레인 형성을 위한 불순물을 이온 주입을 한 후, 산화막(17)을 습식 세정을 통하여 제거하여 실리콘 웨이퍼를 노출시킨다.Next, as shown in FIG. 2C, a etch back is performed by plasma etching without a mask until the lower oxide layer is exposed so that the nitride layer 16 remains at the edge portion of the trench. The nitride film 16 serves to prevent problems such as leakage current and short by separating the trench and the active region. The gate oxide film 17 is thermally grown in the MOS transistor region of the silicon wafer 11 in which the element isolation region is defined, and the polysilicon 18 is deposited on the upper portion by the chemical vapor deposition method. Subsequently, the polysilicon of the portion excluding the gate region is removed by plasma etching by a photolithography process, ion implantation of impurities for forming a source / drain using the gate as a mask, and then wet cleaning the oxide film 17 is performed. Removed through to expose the silicon wafer.
그 다음, 도 2d에 도시된 바와 같이, 실리콘 웨이퍼(11) 전면에 티타늄, 티타늄/질화티타늄 등의 실리사이드(19) 형성을 위한 박막을 스퍼터법에 의해 증착하고, 어닐링을 하여 실리사이드(19)를 형성하며, 실리사이드(19) 형성에 이용되지 않고 잔류하는 박막을 제거한다. 그리고, 절연막(20)을 상압 화학 기상 증착법으로 형성하고, 금속막과 소스/드레인 또는 게이트의 소자 전극 연결을 위해 포토리소그래피 공정에 의해 절연막(20)을 식각한 후, 금속막(21)을 증착한다.Next, as shown in FIG. 2D, a thin film for forming silicide 19, such as titanium or titanium / titanium nitride, is deposited on the entire surface of the silicon wafer 11 by sputtering, followed by annealing to form the silicide 19. It forms and removes the thin film which is not used for silicide 19 formation. Then, the insulating film 20 is formed by an atmospheric pressure chemical vapor deposition method, the insulating film 20 is etched by a photolithography process for connecting the metal film and the device electrode of the source / drain or the gate, and then the metal film 21 is deposited. do.
이와 같이 본 발명은 트렌치의 가장자리에 질화막을 형성함으로써, 트렌치에서 누설 전류나 쇼트가 발생하는 것을 방지하여 반도체 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, a nitride film is formed at the edge of the trench to prevent leakage current or short from occurring in the trench, thereby improving reliability of the semiconductor device.
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| KR20040001907A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Semiconductor device for inducing junction leakage and method for fabricating the same |
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