CN114864480B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN114864480B CN114864480B CN202210783243.1A CN202210783243A CN114864480B CN 114864480 B CN114864480 B CN 114864480B CN 202210783243 A CN202210783243 A CN 202210783243A CN 114864480 B CN114864480 B CN 114864480B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 72
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- 239000010410 layer Substances 0.000 claims abstract description 97
- 238000005530 etching Methods 0.000 claims abstract description 59
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- 238000002955 isolation Methods 0.000 claims abstract description 46
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- 238000011049 filling Methods 0.000 claims abstract description 11
- 238000002360 preparation method Methods 0.000 claims abstract description 8
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- 238000001312 dry etching Methods 0.000 claims description 21
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- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 14
- NBVXSUQYWXRMNV-UHFFFAOYSA-N monofluoromethane Natural products FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
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- 238000007254 oxidation reaction Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
The application discloses a semiconductor device and a preparation method thereof, which are used for reducing cavities and optimizing the electrical property and the yield of the semiconductor device. The preparation method comprises the following steps: providing a substrate, wherein the upper surface of the substrate forms a first functional layer and a second functional layer positioned on the upper surface of the first functional layer; forming an opening penetrating through the first functional layer and the second functional layer, wherein the opening exposes the upper surface of the substrate; etching the substrate along the opening to form a groove positioned in the substrate; carrying out retraction treatment on each functional layer along the side wall of the opening, so that each functional layer retracts towards the outer side direction of the groove relative to the groove opening edge of the groove, exposing part of the substrate surface at the top edge of the groove, and the retraction amount of the second functional layer is larger than that of the first functional layer; performing circular arc treatment on an upper rotation angle formed by the connection of the side wall of the groove and the surface of the substrate, and corroding the first functional layer to enable the final backset of the first functional layer to be less than or equal to the final backset of the second functional layer; and filling an isolation material layer in the groove and the opening to form an isolation structure.
Description
Technical Field
The application relates to the field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof.
Background
Shallow Trench Isolation (STI) is a very important process step in the initial stage of wafer fabrication. When a High-density Plasma (HDP) deposition step is performed in the trench of the shallow trench isolation structure, the requirement on the profile of the STI trench is High. If the topography in the trench is not smooth enough, voids (void) may be easily formed in the isolation material layer subsequently formed in the trench. As shown in fig. 1, is a typical void phenomenon.
In the prior art, two depositions of HTO (High Temperature Oxide) and HDP are required to fill the STI trench. The two depositions of HDP and HTO further cause the STI trench to have a shape bias, causing the aspect ratio of the STI trench to be large, resulting in the void 109.
The STI voids 109 may affect the electrical performance and yield of the final semiconductor device, resulting in wafer scrap. It is desirable to provide a new method for fabricating an STI structure that reduces the occurrence of voids 109.
Disclosure of Invention
In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same, which can reduce the occurrence of voids, thereby optimizing the electrical performance and yield of the semiconductor device.
The application provides a preparation method of a semiconductor device, which comprises the following steps: providing a substrate, wherein a first functional layer and a second functional layer positioned on the upper surface of the first functional layer are formed on the upper surface of the substrate; forming an opening through the first functional layer and the second functional layer, the opening exposing the upper surface of the substrate; etching the substrate along the opening to form a groove in the substrate; carrying out retraction treatment on each functional layer along the side wall of the opening, so that each functional layer retracts towards the outer side direction of the groove relative to the edge of the groove opening of the groove, exposing part of the surface of the substrate at the edge of the top of the groove, and the retraction amount of the second functional layer is larger than that of the first functional layer; performing arc treatment on an upper turning angle formed by the connection of the side wall of the groove and the surface of the substrate, wherein the arc treatment process corrodes the first functional layer, so that the final backset of the first functional layer is less than or equal to that of the second functional layer; and filling an isolation material layer in the groove and the opening to form an isolation structure.
Optionally, the arc treatment includes the following steps: forming a first oxidation layer in the groove, wherein the first oxidation layer at least covers the side wall of the groove and the surface of the upper rotation angle jointed with the surface of the substrate; and removing the first oxide layer by adopting an etching process, wherein the etching process backs the first functional layer along the side wall of the opening.
Optionally, the first oxide layer is removed by a wet etching process.
Optionally, the arc treatment further includes the following steps: and after removing the first oxidation layer, forming a second oxidation layer on the bottom and the side wall surface of the groove, wherein the second oxidation layer at least covers the upper corner of the groove.
Optionally, the first oxide layer and/or the second oxide layer are formed on the bottom and the sidewall surface of the trench by at least one of a high-concentration plasma deposition method or a high-temperature oxide deposition method.
Optionally, a dry etching process is adopted to perform rollback processing on each functional layer, and the number of hydrogen atoms of gas molecules in etching gas used in the dry etching is greater than or equal to 2.
Optionally, an etching rate ratio of the etching gas used for the dry etching to the second functional layer to the first functional layer is greater than 500; and/or the etching gas comprises at least one of monofluoromethane or difluoromethane.
Optionally, the performing, by using a dry etching process, a rollback process on each functional layer includes: determining the etching duration of the dry etching according to the preset backspacing of each functional layer; and providing etching gas for each functional layer for the etching duration, wherein the etching gas carries non-directional plasma.
Optionally, before performing the rounding treatment on the upper corner where the trench sidewall and the substrate surface are joined, the method further includes the following steps: and forming a protective layer on the surface of one side of the first functional layer distributed along the opening, wherein the protective layer can be removed by the arc treatment process.
Optionally, the forming a protective layer on a surface of the first functional layer on a side along the opening includes: and taking a byproduct formed in the process of the rollback treatment as the protective layer.
Optionally, the byproduct comprises a polymer.
Optionally, filling an isolation material layer in the trench and the opening to form an isolation structure includes: forming a first isolation layer on the bottom and the surface of the side wall of the groove, wherein the first isolation layer also covers the side wall of the opening and the upper surface of the second functional layer; and filling a second isolation layer in the residual space of the groove and the opening, wherein the second isolation layer also covers the upper surface of the second functional layer.
Optionally, the material of the first functional layer includes at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide, and the material of the second functional layer includes at least silicon nitride.
The present application provides a semiconductor device including: a substrate; the first functional layer is positioned on the surface of the substrate, and the second functional layer is positioned on the surface of the first functional layer; openings are formed in the first functional layer and the second functional layer and penetrate through the first functional layer and the second functional layer; a groove which is positioned below the opening and communicated with the opening is formed in the substrate, and the bottom of the opening is exposed out of part of the surface of the substrate at the edge of the opening at the top of the groove; the edges of the first functional layer and the second functional layer on the side wall of the opening are flush, or the edge of the second functional layer protrudes inwards the opening; and the isolation material layer is filled in the groove and the opening.
Optionally, an upper corner of the groove is arc-shaped.
Optionally, the edge of the second functional layer is arc-shaped.
Optionally, the trench further includes a second oxide layer formed on the bottom surface and the sidewall surface of the trench, and the isolation material layer is formed on the upper surface of the second oxide layer.
According to the semiconductor device and the manufacturing method thereof, as each functional layer is positioned on one side of the opening and retreats compared with the opening, and the retreating amount of the second functional layer is larger than the retreating amount of the first functional layer, even if the retreating amount of the first functional layer is influenced to a certain extent in the process of forming and removing the first oxide layer in the groove, the possibility that a gap interlayer is formed between the second functional layer and the upper surface of the substrate is greatly reduced because the retreating amount of the second functional layer is larger than that of the first functional layer, the retreating amount of the first functional layer is still smaller than or equal to that of the second functional layer, and the gap interlayer is not completely filled by the film layer when other film layers are deposited in the groove is avoided, so that the electrical property and the yield of the finally formed semiconductor device are optimized, and the yield of wafers is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device forming a Void (Void) in the prior art.
Fig. 2 is a schematic flow chart illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 3 to 13 are schematic structural diagrams formed in the steps of the process of manufacturing the semiconductor device according to an embodiment of the present application.
Detailed Description
The conventional STI structure is prone to voids because, after the trench is formed, the functional layer on the surface of the substrate is subjected to a rollback treatment along a side where the trench opening is distributed, but the rollback treatment usually results in an excessive rollback amount of the first functional layer, and a small rollback amount of the second functional layer, which results in a void interlayer formed between the second functional layer and the first functional layer, and in a subsequent isolation material filling process, an isolation material is also difficult to fill in the void interlayer, thereby resulting in subsequent voids.
The following provides a new semiconductor device and method of fabrication that overcomes the void problem of the STI structure.
The semiconductor device and the method for manufacturing the same are further described below with reference to the accompanying drawings and examples.
Referring to fig. 2 to 13, fig. 2 is a schematic flow chart illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, and fig. 3 to 13 are schematic structural diagrams formed in steps of a process for manufacturing the semiconductor device according to an embodiment of the present disclosure.
The preparation method comprises the following steps:
step S1, providing a substrate 100, wherein a first functional layer 102 and a second functional layer 103 positioned on the upper surface of the first functional layer 102 are formed on the upper surface of the substrate 100, and reference can be made to FIG. 3.
Step S2: an opening 1011 is formed through the first functional layer 102 and the second functional layer 103, and the opening 1011 exposes the upper surface of the substrate 100, as shown in fig. 6.
And step S3: the substrate 100 is etched along the opening 1011 to form a trench 101 located inside the substrate 100, as shown in fig. 7.
And step S4: and performing retraction processing on each functional layer along the side wall of the opening 1011, so that each functional layer retracts in the direction outside the trench 101 relative to the edge of the trench opening of the trench 101, a part of the surface of the substrate 100 at the top edge of the trench 101 is exposed, and the retraction amount of the second functional layer 103 is greater than that of the first functional layer 102.
Step S5: and performing arc treatment on an upper corner where the side wall of the groove 101 and the surface of the substrate 100 are joined, wherein the arc treatment process corrodes the first functional layer 102, so that the final back-off amount of the first functional layer 102 is less than or equal to the final back-off amount of the second functional layer 103.
Step S6: an isolation material layer is filled in the trench 101 and the opening 1011 to form an isolation structure.
In this embodiment, since each functional layer retracts from the side of the opening 1011 compared to the opening 1011, and the retraction amount of the second functional layer 103 is greater than that of the first functional layer 102, even if the retraction amount of the first functional layer 102 is affected to a certain extent in the process of forming and removing the first oxide layer 105 in the trench 101, the retraction amount of the first functional layer 102 is still less than or equal to that of the second functional layer 103 because the retraction amount of the second functional layer 103 is greater than that of the first functional layer 102, and the possibility of forming a void interlayer between the second functional layer 103 and the upper surface of the substrate 100 is greatly reduced, thereby avoiding the void problem that the void interlayer cannot be completely filled by other film layers deposited in the trench 101, optimizing the electrical property and yield of the finally formed semiconductor device, and improving the yield of wafers.
Referring to fig. 3, in the embodiment shown in fig. 3, a substrate 100 is provided, a first functional layer 102 is formed on the upper surface of the substrate 100, and a second functional layer 103 is formed on the upper surface of the first functional layer 102.
The substrate 100 includes a silicon substrate 100, a silicon-on-insulator substrate 100, a germanium substrate 100, etc., and those skilled in the art can replace them as needed.
In some embodiments, the material of the first functional layer 102 includes at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide.
In some embodiments, the trench 101 is used to form a shallow trench isolation structure in a semiconductor memory structure, and at this time, the material of the first functional layer 102 is silicon oxide.
In some embodiments, the material of the second functional layer 103 comprises at least silicon nitride. In some other embodiments, the second functional layer 103 includes a plurality of film layers, such as a silicon nitride layer and a silicon oxide layer, and each of the film layers is stacked in sequence in a direction perpendicular to the upper surface of the substrate 100.
In some embodiments, the first functional layer 102 has a thickness of at least 450 a, and/or the second functional layer 103 has a thickness of at least 1200 a. In fact, the specific materials and thicknesses of the first functional layer 102 and the second functional layer 103 may be set according to the needs.
In some embodiments, the second functional layer 103 is a silicon nitride layer having a thickness of 1400 a, and the first functional layer 102 is a silicon oxide layer having a thickness of 475 a.
Referring to fig. 6, an opening 1011 is formed on the surface of the first functional layer 102 and the second functional layer 103, the opening 1011 exposes the expected forming area of the trench 101, and the trench 101 is formed in the exposed area of the opening 1011, and has a size equal to or smaller than the exposed area of the opening 1011.
In some embodiments, the step of forming the opening 1011 is as follows: a mask layer 104 is formed on the surface of the second functional layer 103, as shown in fig. 4. Then, patterning is performed on the mask layer 104 to expose the second functional layer 103, as shown in fig. 5. Then, the second functional layer 103 exposed by the mask layer 104 after the patterning process is etched, and the first functional layer 102 is etched downward from the upper surface of the second functional layer 103 to expose the surface of the substrate 100, so as to form the opening 1011, as shown in fig. 6.
In some embodiments, as shown in fig. 7, after the opening 1011 is formed, the substrate 100 is etched continuously down the opening 1011 to form the trench 101 inside the substrate 100.
In some embodiments, as shown in fig. 8, the functional layers are retreated along the sidewall of the opening 1011. In the process of the retraction process, the functional layers are retracted towards the outside of the trench 101 relative to the edge of the trench opening of the trench 101, exposing a portion of the surface of the substrate 100 at the top edge of the trench 101. In addition, the roll-back process needs to keep the roll-back amount of the second functional layer 103 greater than that of the first functional layer 102, which is beneficial to the deposition of the isolation material layer in the subsequent process, and is convenient for the high-concentration plasma deposition process and the high-temperature oxide deposition process.
The receding amount refers to a minimum distance between the side of the first functional layer 102/the second functional layer 103 constituting the sidewall of the opening 1011 and the groove opening edge of the groove 101 in a direction parallel to the upper surface of the substrate 100. Referring here to the backset d1 and backset d2 in fig. 8, it can be seen that the backset d1 of the first functional layer 102 is less than the backset d2 of the second functional layer 103.
In some embodiments, a dry etching process is adopted to perform rollback processing on each functional layer, and the number of hydrogen atoms of gas molecules in etching gas used in the dry etching is greater than or equal to 2.
In this embodiment, by controlling the flow rate, the introduction time length, and the introduction direction of the etching gas during the dry etching, the backset of each functional layer can be accurately controlled. It has been found that it is difficult to control the amount of roll-back of the first functional layer 102 when wet etching is used to control the roll-back of the functional layer. The dry etching can well overcome the defects of the wet etching.
In addition, in this embodiment, the number of hydrogen atoms of gas molecules in the etching gas is greater than or equal to 2, so that the hydrogen atom content of the etching gas is increased, when the second functional layer 103 is a silicon nitride layer, silicon nitride reacts with the etching gas to form a large number of polymer byproducts, and these polymer byproducts can stay on the surface of the first functional layer 102, and in the subsequent arc process, the polymer byproducts can protect the first functional layer 102, so as to reduce the etched amount of the first functional layer 102.
In some embodiments, the etching gas comprises at least one of monofluoromethane or difluoromethane. The two etching gases have more than two hydrogen atoms in the gas molecules, so that the effect of generating more polymer byproducts can be achieved. Moreover, when the material of the second functional layer 103 is silicon nitride and the material of the first functional layer 102 is silicon oxide, the etching rate of monofluoromethane and difluoromethane to the second functional layer 103 is greater than that to the first functional layer 102, which helps to make the backset of the second functional layer 103 greater than that of the first functional layer 102.
In some embodiments, the performing, by using a dry etching process, a rollback process on each functional layer includes: determining the etching duration of the dry etching according to the preset backspacing of each functional layer; and providing etching gas for each functional layer for the etching duration, wherein the etching gas carries non-directional plasma.
In some embodiments, the predetermined backset of the first functional layer 102 and the second functional layer 103 is about 50 a to 500 a.
In some embodiments, the etching rate ratio of the etching gas used for the dry etching to the second functional layer 103 and the first functional layer 102 is greater than 500.
In some embodiments, the time duration for performing the backspacing treatment on the functional layers is determined by controlling the introduction time duration of the etching gas, so as to determine the backspacing of each functional layer. In some embodiments, the specific required rollback treatment time length is determined according to the rollback amount of each functional layer needing to be rolled back and the preparation material of each functional layer.
Since the rounding process is required for the upper corner, the difference between the back-off amount of the second functional layer 103 and the back-off amount of the first functional layer 102 needs to be determined according to the degree of influence of the rounding process on the first functional layer 102. And determining the etching duration in the dry etching process according to the difference, the etching rate ratio of the etching gas to the first functional layer 102 and the second functional layer 103 in the dry etching process, and the flow rate of the etching gas introduced into the reaction chamber.
In some embodiments, when performing the rollback processing on each functional layer by using monofluoromethane or difluoromethane in the above embodiments, if it is required that the second functional layer 103 is backed by 15 microns compared with the edge of the trench opening, the first functional layer 102 is backed by 10 microns compared with the edge of the trench opening, and the flow rate of the etching gas is about 50sccm, the required etching time is about 15s. In fact, parameters such as the etching time and the specific types and flow rates of etching gases can be set according to requirements.
In some embodiments, when performing the back-off process using the dry etching process, the flow rate of the etching gas is about 10 to 100sccm, and the introduction time period is about 5 to 30s.
In some embodiments, the structure formed after the rollback process is shown in fig. 8. In some embodiments, after the arc process, the finally formed structure is as shown in fig. 10, the recession amount of the first functional layer 102 and the recession amount of the second functional layer 103 are equal compared to the groove opening, and the edges of the first functional layer 102 and the second functional layer 103 on the side of the groove opening are flush. Based on the structure shown in fig. 10, the probability that the finally formed semiconductor device has voids is greatly reduced.
In fact, in some embodiments, after the arc treatment, the finally formed structure is as shown in fig. 8 for the first functional layer 102 and the second functional layer 103, and the recession of the second functional layer 103 is still larger than that of the first functional layer 102, and based on this structure, the possibility that the finally formed semiconductor device has voids is also greatly reduced.
In some embodiments, the etching gas carries non-directional plasma, so that a uniform etching effect can be achieved, the plasma in the etching gas stays on the surface of a semiconductor device or in an exposed edge region of a trench opening below the functional layer, the influence of the plasma on the inside of the trench 101 is reduced, the rounding effect of the etching gas on an upper corner of the upper functional layer is retained, and the shape of the trench 101 below is not influenced. In the process of performing the rollback processing on the functional layer by using the dry etching, the direction of the plasma in the etching gas is not controlled, so that the formation of the directional plasma beam is avoided, and the influence of the directional plasma beam on the internal shape of the groove 101 is avoided.
In some embodiments, the plasma is provided by a plasma providing device. And, turning on the RF output of the plasma providing device to initiate the provision of the plasma. In some embodiments, the plasma concentration and the supply time of the plasma are controlled, and the direction of the plasma is not controlled, so that the non-directional etching of the functional layers is realized.
The plasma supply device controls the plasma concentration of the plasma through a power supply (source power) of the radio frequency output and controls the emission direction of the plasma through a bias power supply (bias power), so that in some embodiments, only the power supply is turned on to control the plasma concentration of the plasma, and the bias switch is turned off, thereby preventing the plasma from forming a plasma beam with a fixed emission direction and affecting the shape of the lower trench 101.
In some embodiments, the rounding process comprises the steps of: forming a first oxide layer 105 in the trench 101, wherein the first oxide layer 105 covers at least the surface of the upper corner where the sidewall of the trench 101 meets the surface of the substrate 100, as shown in fig. 9; the first oxide layer 105 is removed by an etching process, and the etching process retreats the first functional layer 102 along the sidewall of the opening 1011, as shown in fig. 10.
The formation and removal of the first oxide layer 105 can effectively achieve the rounding effect of the upper corner, wherein the formation of the first oxide layer 105 can cover the sharp top corner of the upper corner, and the removal of the first oxide layer 105 can additionally remove the sharp top corner of the upper corner, so that the rounding treatment of the upper corner is achieved.
In some embodiments, the material of the first oxide layer 105 includes at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide.
The arc treatment makes the upper corner of the groove 101 rounded, and reduces the probability of the point discharge problem caused by the excessively sharp upper corner of the groove 101.
In some embodiments, the first oxide layer 105 is removed using a wet etch process. The wet etching process may remove the first oxide layer 105 and also remove a protective layer attached to the surface of the first functional layer 102. In some embodiments, the etching liquid used in the wet etching process has similar or identical etching rate ratio to the first oxide layer and to the protective layer.
In some embodiments, the arcing process further comprises the steps of: after removing the first oxide layer 105, a second oxide layer 106 is formed on the bottom and sidewall surfaces of the trench 101, where the second oxide layer 106 covers at least the upper corner of the trench 101, as shown in fig. 12.
The second oxide layer 106 can further cover the sharp top corner of the upper corner, which is beneficial to realizing the arc of the upper corner and preventing the point discharge.
In some embodiments, the material of the second oxide layer 106 includes at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide. The second oxide layer 106 also helps to achieve insulating properties on the sidewalls and bottom of the trench 101.
In fact, the specific material and thickness of the first oxide layer 105 and the second oxide layer 106 can also be set as desired.
In some embodiments, the first oxide layer 105 and/or the second oxide layer 106 are formed on the bottom and sidewall surfaces of the trench 101 by at least one of a high concentration plasma deposition method or a high temperature oxide deposition method.
In some embodiments, before the rounding the upper corner where the sidewall of the trench 101 meets the surface of the substrate 100, the method further includes the following steps: a protective layer is formed on the surface of the first functional layer 102 on the side where the openings 1011 are located, and the protective layer can be removed by the arc treatment process, so that the protective layer does not need to be additionally treated, and the protective layer does not need to be removed by an additional process while the first functional layer 102 is protected.
In some embodiments, forming a protective layer on a surface of the first functional layer 102 on a side along the opening 1011 includes: and taking a byproduct formed in the process of the rollback treatment as the protective layer. Therefore, no additional process is required to prepare the passivation layer.
In some embodiments, the byproduct comprises a polymer. In fact, other kinds of byproducts can be generated as the protective layer according to actual needs.
In some embodiments, during the rollback treatment of the first functional layer 102 and the second functional layer 103 using monofluoromethane or difluoromethane, due to the higher hydrogen atom content in monofluoromethane or difluoromethane, more polymer byproducts can be effectively generated in the reaction process, and these byproducts are formed on the surface and the sidewall of the first functional layer 102, and in the subsequent arc treatment of the upper corner, the arc treatment corrodes the byproducts first and then corrodes the first functional layer 102, so that the corrosion amount of the first functional layer 102 is reduced, and the possibility of forming a void interlayer under the second functional layer 103 is reduced.
The filling of the isolation material layer in the trench 101 and the opening 1011 to form an isolation structure includes: forming a first isolation layer 107 on the bottom and sidewall surfaces of the trench 101, wherein the first isolation layer 107 further covers the sidewall of the opening 1011 and covers the upper surface of the second functional layer 103; the remaining space of the trench 101 and the opening 1011 is filled with a second isolation layer 108, and the second isolation layer 108 also covers the upper surface of the second functional layer 103.
In some embodiments, referring to fig. 13, since the second isolation layer 108 needs to fill the trench 101, the second isolation layer 108 forms a peak-shaped stacked structure on the surface of the second functional layer 103. In fact, if other film formation methods are used, the second isolation layer 108 may also be formed flatly on the first isolation layer 107.
In some embodiments, a High density Plasma (High density Plasma) deposition method and/or a High Temperature oxide (High Temperature oxide) deposition method are used to sequentially form the first isolation layer 107 and the second isolation layer 108 in the trench 101.
In some embodiments, the high density plasma deposition process is HDPCVD, which is an addition of sputtering (sputter) to conventional CVD, which helps to increase the deposition density and also eliminates the protrusions of corner features during deposition, thereby improving the deposition effect, wherein the power supply wattage of the plasma apparatus is about 50 to 1000W.
The high temperature oxide deposition process refers to an oxide deposition process at a temperature above 300 ℃.
In some embodiments, the retreating of the second functional layer 103 also helps to round the top of the second functional layer 103, enlarge the size of the opening 1011, and enable the isolation material to enter the opening 1011 and the trench 101 better when filling the isolation material layer, thereby achieving better filling effect and better electrical characteristics.
The present application also provides a semiconductor device including: a substrate 100; a first functional layer 102 positioned on the surface of the substrate 100 and a second functional layer 103 positioned on the surface of the first functional layer 102; an opening 1011 is formed in the first functional layer 102 and the second functional layer 103, and the opening 1011 penetrates through the first functional layer 102 and the second functional layer 103; a groove 101 is formed in the substrate 100 and is located below the opening 1011 and is communicated with the opening 1011, and the bottom of the opening 1011 exposes a part of the surface of the substrate 100 at the edge of the opening 1011 at the top of the groove 101; the edges of the first functional layer 102 and the second functional layer 103 on the side wall of the opening 1011 are flush, or the edge of the second functional layer 103 protrudes inwards the opening 1011; and an isolation material layer filling the trench 101 and the opening 1011.
In this embodiment, since each functional layer retracts from the side of the opening 1011 compared to the opening 1011, and the retraction amount of the second functional layer 103 is greater than that of the first functional layer 102, even if the retraction amount of the first functional layer 102 is affected to a certain extent during the process of forming and removing the first oxide layer 105 in the trench 101, since the retraction amount of the second functional layer 103 is greater than that of the first functional layer 102, the retraction amount of the first functional layer 102 is still less than or equal to that of the second functional layer 103, and the possibility of forming a void interlayer between the second functional layer 103 and the upper surface of the substrate 100 is greatly reduced, thereby avoiding the void problem that the void interlayer cannot be completely filled by other film layers deposited in the trench 101, optimizing the electrical property and yield of the finally formed semiconductor device, and improving the yield of wafers.
In some embodiments, the upper corner of the groove 101 is rounded, and the rounded upper corner is processed.
In some embodiments, the edge of the second functional layer 103 is arc-shaped, which is formed after the rollback treatment, and facilitates the deposition and preparation of the isolation material layer.
In some embodiments, the trench structure further includes a second oxide layer 106 formed on the bottom surface and the sidewall surface of the trench 101, and the isolation material layer is formed on the upper surface of the second oxide layer 106. The second oxide layer 106 is advantageous to help achieve the insulating property of the sidewall and bottom of the trench 101.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate, wherein a first functional layer and a second functional layer positioned on the upper surface of the first functional layer are formed on the upper surface of the substrate;
forming an opening through the first functional layer and the second functional layer, the opening exposing the upper surface of the substrate;
etching the substrate along the opening to form a groove positioned in the substrate;
carrying out retraction treatment on each functional layer along the side wall of the opening, so that each functional layer retracts towards the outer side direction of the groove relative to the edge of the groove opening of the groove, exposing part of the surface of the substrate at the edge of the top of the groove, and the retraction amount of the second functional layer is greater than that of the first functional layer;
performing arc treatment on an upper corner connected between the side wall of the groove and the surface of the substrate, wherein the arc treatment process corrodes the first functional layer, so that the final backset of the first functional layer is less than or equal to that of the second functional layer;
filling an isolation material layer in the groove and the opening to form an isolation structure;
the arc treatment comprises the following steps: forming a first oxidation layer in the groove, wherein the first oxidation layer at least covers the side wall of the groove and the surface of the upper rotation angle jointed with the surface of the substrate; removing the first oxide layer by adopting an etching process, wherein the etching process backs the first functional layer along the side wall of the opening; the first oxide layer is formed to cover the sharp top angle of the upper corner, and the removal of the first oxide layer can additionally remove the sharp top angle of the upper corner, so that the circular arc treatment of the upper corner is realized;
and performing rollback treatment on each functional layer by adopting a dry etching process, wherein the number of hydrogen atoms of gas molecules in etching gas used in the dry etching process is more than or equal to 2 so as to improve the hydrogen atom content of the etching gas, the second functional layer is a silicon nitride layer, silicon nitride can generate more polymer byproducts through reaction with the etching gas, the polymer byproducts are used for staying on the surface and the side wall of the first functional layer, and the first functional layer is protected in subsequent arc treatment so as to reduce the etched amount of the first functional layer.
2. The method according to claim 1, wherein the first oxide layer is removed by a wet etching process.
3. The method of claim 1, wherein the arcing process further comprises the steps of:
and after removing the first oxidation layer, forming a second oxidation layer on the bottom and the surface of the side wall of the groove, wherein the second oxidation layer at least covers the upper corner of the groove.
4. The method of claim 3, wherein the first oxide layer and/or the second oxide layer is formed on the bottom and sidewall surfaces of the trench by at least one of a high-concentration plasma deposition method or a high-temperature oxide deposition method.
5. The production method according to claim 1, wherein an etching rate ratio of an etching gas used for the dry etching to the second functional layer to the first functional layer is greater than 500; and/or the presence of a gas in the atmosphere,
the etching gas includes at least one of monofluoromethane or difluoromethane.
6. The preparation method according to claim 1, wherein the performing of the rollback treatment on each functional layer by using the dry etching process comprises:
determining the etching duration of the dry etching according to the preset backspacing of each functional layer;
and providing etching gas for each functional layer for the etching duration, wherein the etching gas carries non-directional plasma.
7. The method according to claim 1, further comprising, before the rounding of the upper corner where the trench sidewall meets the substrate surface, the steps of:
and forming a protective layer on the surface of one side of the first functional layer distributed along the opening, wherein the protective layer can be removed by the arc treatment process.
8. The method according to claim 7, wherein forming a protective layer on a surface of the first functional layer on a side along the opening comprises:
and taking a byproduct formed in the process of the rollback treatment as the protective layer.
9. The method of claim 1, wherein the filling the trench and the opening with an isolation material layer to form an isolation structure comprises:
forming a first isolation layer on the bottom and the surface of the side wall of the groove, wherein the first isolation layer also covers the side wall of the opening and the upper surface of the second functional layer;
and filling a second isolation layer in the residual space of the groove and the opening, wherein the second isolation layer also covers the upper surface of the second functional layer.
10. The production method according to claim 1, wherein the material of the first functional layer comprises at least one of silicon oxide, silicon oxynitride, and silicon oxycarbide, and the material of the second functional layer comprises at least silicon nitride.
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| CN101459115A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
| CN104347473A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | Shallow-trench isolation structure and forming method thereof |
| CN112928059A (en) * | 2021-01-21 | 2021-06-08 | 华虹半导体(无锡)有限公司 | Method for forming shallow trench isolation |
| CN114496902A (en) * | 2022-01-10 | 2022-05-13 | 上海华虹宏力半导体制造有限公司 | Method for fabricating STI structure with TCR |
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| CN101459115A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
| CN104347473A (en) * | 2013-08-05 | 2015-02-11 | 中芯国际集成电路制造(北京)有限公司 | Shallow-trench isolation structure and forming method thereof |
| CN112928059A (en) * | 2021-01-21 | 2021-06-08 | 华虹半导体(无锡)有限公司 | Method for forming shallow trench isolation |
| CN114496902A (en) * | 2022-01-10 | 2022-05-13 | 上海华虹宏力半导体制造有限公司 | Method for fabricating STI structure with TCR |
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