CN114496902A - Method for fabricating STI structure with TCR - Google Patents

Method for fabricating STI structure with TCR Download PDF

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Publication number
CN114496902A
CN114496902A CN202210021181.0A CN202210021181A CN114496902A CN 114496902 A CN114496902 A CN 114496902A CN 202210021181 A CN202210021181 A CN 202210021181A CN 114496902 A CN114496902 A CN 114496902A
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China
Prior art keywords
etching
hard mask
groove
mask layer
substrate
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Pending
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CN202210021181.0A
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Chinese (zh)
Inventor
张振兴
熊磊
谭理
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp, Hua Hong Semiconductor Wuxi Co Ltd filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202210021181.0A priority Critical patent/CN114496902A/en
Publication of CN114496902A publication Critical patent/CN114496902A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The application discloses a manufacturing method of an STI structure with TCR, which comprises the following steps: carrying out first etching, removing the hard mask layer and the insulating layer of the target area, and forming a first groove, wherein the insulating layer is formed on the substrate, and the hard mask layer is formed on the insulating layer; performing second etching, wherein in the process of performing the second etching, the introduced reaction gas forms a polymer on the side wall of the first groove, so that the cross-sectional appearance of the substrate at the bottom of the side wall of the first groove is a rounded angle, and the ratio of the deposition rate of the polymer to the etching rate of the second etching is 1.5-2.5; and carrying out third etching to extend the first groove to the bottom of the substrate to form a second groove. The polymer is formed by introducing the reaction gas in the etching process, and the fillet appearance at the top of the substrate in the groove is better by controlling the forming rate of the polymer and the etching rate of the second etching, so that the reliability of the device is improved.

Description

Method for fabricating STI structure with TCR
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a Shallow Trench Isolation (STI) structure with top rounded corner (TCR).
Background
In semiconductor manufacturing, STI structures are commonly used to isolate Active Areas (AA) of semiconductor devices. In order to improve the isolation effect and the leakage current performance of the device, when a trench of an STI structure is formed, the top corner of the trench is usually rounded to form a TCR profile.
For TCRs, rounded corners are generally required to be large in diameter (preferably greater than 20 nanometers (nm)) and have rounded features. However, in the trench of the STI structure formed according to the manufacturing method provided in the related art, the TCR profile is poor, and is generally represented by a small diameter of the fillet, which meets the requirement but has a severe warpage, or the fillet is not smooth.
Accordingly, it is desirable to provide a method for fabricating an STI structure having a TCR with a rounded profile and a large corner size.
Disclosure of Invention
The application provides a manufacturing method of an STI structure with TCR, which can solve the problem that the TCR formed by the manufacturing method of the STI structure provided in the related technology has poor appearance, and the method comprises the following steps:
carrying out first etching, removing a hard mask layer and an insulating layer of a target area, and forming a first groove, wherein the insulating layer is formed on a substrate, and the hard mask layer is formed on the insulating layer;
performing second etching, wherein in the process of performing the second etching, introduced reaction gas forms a polymer on the side wall of the first groove, so that the cross section appearance of the substrate at the bottom of the side wall of the first groove is a round angle, and the ratio of the deposition rate of the polymer to the etching rate of the second etching is 1.5-2.5;
and carrying out third etching to extend the first groove to the bottom of the substrate to form a second groove.
In some embodiments, the rounded corners have a diameter greater than 20 nanometers.
In some embodiments, the reaction gas introduced in the second etching includes at least one of trifluoromethane, difluoromethane, fluoromethane and octafluorocyclobutane.
In some embodiments, the performing the first etching includes:
covering a photoresist on the hard mask layer through a photoetching process to expose the hard mask layer of the target area;
carrying out first etching to remove the hard mask layer and the insulating layer of the target area until the substrate of the target area is exposed;
and removing the photoresist.
In some embodiments, the forming an oxide layer on the hard mask layer comprises:
and depositing a silicon dioxide film on the hard mask layer through a CVD (chemical vapor deposition) process to form the oxide layer.
In some embodiments, the hard mask layer comprises a silicon nitride film.
In some embodiments, the insulating layer comprises a silicon dioxide film.
The technical scheme at least comprises the following advantages:
after the first groove is formed by opening the hard mask layer and the insulating layer of the target area, when the first groove is further etched downwards, the polymer is formed on the side wall of the first groove by introducing the reaction gas, so that the appearance of the fillet at the top of the substrate is better by controlling the forming rate of the polymer and the etching rate of the second etching, and the reliability of the device is further improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for fabricating an STI structure with a TCR according to an exemplary embodiment of the present application;
fig. 2 to 4 are schematic views illustrating a process for fabricating an STI structure having a TCR according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a method for fabricating an STI structure having a TCR according to an exemplary embodiment of the present application is shown, as shown in fig. 1, the method including:
step S1, performing a first etching to remove the hard mask layer and the insulating layer in the target region, and forming a first trench, where the insulating layer is formed on the substrate and the hard mask layer is formed on the insulating layer.
Referring to fig. 2, a schematic cross-sectional view after a first etch is performed is shown. Illustratively, as shown in fig. 2, an insulating layer 220 is formed on the substrate 210, and a Hard Mask (HM) layer 230 is formed on the insulating layer 220, and the step S1 includes, but is not limited to: covering a photoresist (not shown in fig. 2) on the hard mask layer 230 by a photolithography process, exposing the hard mask layer 230 in a target region (the target region is a projection of the first trench 301 on a plane of the upper surface of the hard mask layer 230); performing first etching to remove the hard mask layer 230 and the insulating layer 220 in the target region until the substrate 210 in the target region is exposed to form a first trench 301; and removing the photoresist.
The hard mask layer 230 may include a silicon nitride (SiN) film, and the insulating layer 220 may include silicon dioxide (SiO)2) A film. Before step S1, the insulating layer 220 may be formed by forming a silicon oxide film on the substrate 210 through a thermal oxidation (thermal oxidation) process, and the hard mask layer 230 may be formed by depositing a silicon nitride film on the insulating layer 220 through a Chemical Vapor Deposition (CVD) process.
And step S2, performing second etching, wherein in the process of performing the second etching, the introduced reaction gas forms a polymer on the side wall of the first groove, so that the cross-sectional appearance of the substrate at the bottom of the side wall of the first groove is a rounded angle, and the ratio of the deposition rate of the polymer to the etching rate of the second etching is 1.5-2.5.
Referring to fig. 3, a schematic cross-sectional view of the second etching is shown. As shown in fig. 3, during the second etching, the polymer (polymer)400 is formed on the sidewall of the first trench 301 by the introduced reaction gas, so that the cross-sectional profile of the substrate 210 at the bottom of the sidewall of the first trench 301 is rounded (i.e., TCR 241).
By controlling the deposition of polymer 400Controlling the size of the TCR241 and the arc curvature thereof by the rate and the etching rate of the second etching, wherein the ratio of the deposition rate of the polymer 400 to the etching rate of the second etching is set to be in the range of 1.5 to 2.5, and the introduced reaction gas comprises trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Fluoromethane (CH)3F) And octafluorocyclobutane (C)4F8) At least one of (1).
And step S3, carrying out a third etching to extend the first trench to the bottom of the substrate to form a second trench.
Referring to fig. 4, a schematic cross-sectional view of the third etching is shown. Illustratively, as shown in fig. 3, the first trench 301 extends downward into the substrate 210 by a third etching, and the second trench 302 is formed to a predetermined depth in the substrate 210.
To sum up, in the embodiment of the present application, after the first trench is formed by opening the hard mask layer and the insulating layer in the target region, when the first trench is further etched downward, a polymer is formed on the surface of the hard mask layer and the sidewall of the first trench by introducing a reaction gas, so that the shape of the fillet at the top of the substrate can be better by controlling the formation rate of the polymer and the etching rate of the second etching, and the reliability of the device is further improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (7)

1. A method for fabricating a STI structure with a TCR, comprising:
carrying out first etching, removing a hard mask layer and an insulating layer of a target area, and forming a first groove, wherein the insulating layer is formed on a substrate, and the hard mask layer is formed on the insulating layer;
performing second etching, wherein in the process of performing the second etching, introduced reaction gas forms a polymer on the side wall of the first groove, so that the cross-sectional appearance of the substrate at the bottom of the side wall of the first groove is a rounded angle, and the ratio of the deposition rate of the polymer to the etching rate of the second etching is 1.5-2.5;
and carrying out third etching to extend the first groove to the bottom of the substrate to form a second groove.
2. The method of claim 1, wherein the rounded corners have a diameter greater than 20 nanometers.
3. The method according to claim 2, wherein the reaction gas introduced in the second etching includes at least one of trifluoromethane, difluoromethane, fluoromethane and octafluorocyclobutane.
4. The method of any of claims 1 to 3, wherein the performing a first etch comprises:
covering a photoresist on the hard mask layer through a photoetching process to expose the hard mask layer of the target area;
carrying out first etching to remove the hard mask layer and the insulating layer of the target area until the substrate of the target area is exposed;
and removing the photoresist.
5. The method of claim 4, wherein said forming an oxide layer on said hard mask layer comprises:
and depositing a silicon dioxide film on the hard mask layer through a CVD (chemical vapor deposition) process to form the oxide layer.
6. The method of claim 5, wherein the hard mask layer comprises a silicon nitride film.
7. The method of claim 6, wherein the insulating layer comprises a silicon dioxide film.
CN202210021181.0A 2022-01-10 2022-01-10 Method for fabricating STI structure with TCR Pending CN114496902A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864480A (en) * 2022-07-05 2022-08-05 广州粤芯半导体技术有限公司 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114864480A (en) * 2022-07-05 2022-08-05 广州粤芯半导体技术有限公司 Semiconductor device and method for manufacturing the same
CN114864480B (en) * 2022-07-05 2022-10-21 广州粤芯半导体技术有限公司 Semiconductor device and method for manufacturing the same

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