CN111524854A - Etching method applied to subsequent process - Google Patents
Etching method applied to subsequent process Download PDFInfo
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- CN111524854A CN111524854A CN202010342342.7A CN202010342342A CN111524854A CN 111524854 A CN111524854 A CN 111524854A CN 202010342342 A CN202010342342 A CN 202010342342A CN 111524854 A CN111524854 A CN 111524854A
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- hard mask
- mask layer
- dielectric layer
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- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Abstract
The application discloses an etching method applied to a subsequent procedure, which comprises the following steps: covering a photoresist in a target area of a second hard mask layer through a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a second medium layer, the second medium layer is formed on a first medium layer, the first medium layer is formed on an interlayer medium and a metal through hole formed in the interlayer medium, and the target area is other areas except an area above the metal through hole on the second hard mask layer; removing the second hard mask layer, the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by etching; carbonizing the photoresist; and etching to remove the second dielectric layer with the second preset depth. According to the method, the light resistor is subjected to carbonization treatment, then the second dielectric layer with the second preset depth is removed through etching, the surface of the light resistor can be firm after the light resistor is subjected to carbonization treatment, and the light resistor with the firm surface can keep a better appearance in the etching process.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to an etching method applied to a subsequent procedure.
Background
Fig. 1 and 2 are schematic diagrams illustrating an M1 metal etching process in a back end of line (BEOL) of a semiconductor manufacturing industry provided in the related art.
Referring to fig. 1, which shows a cross-sectional view of a photoresist covering an interconnect structure by a photolithography process, as shown in fig. 1, a metal via 112 is formed in an interlayer dielectric 111, a first dielectric layer 120, a second dielectric layer 130, a first hard mask layer 140 and a second hard mask layer 150 are sequentially formed on the interlayer dielectric 111 and the metal via 112, and a photoresist 160 is covered on the second hard mask layer 150 except for a region above the metal via 112 by a photolithography process.
Referring to fig. 2, a schematic cross-sectional view of etching a dielectric layer over a metal via 112 is shown. As shown in fig. 2, the exposed region is etched to a target depth in the second dielectric layer 130 using the photoresist 160 as a mask, thereby forming a trench (trench) 101.
However, the M1 metal etching process provided by the related art generally results in poor profile of the etched trench due to insufficient photoresist, thereby reducing the yield of the product.
Disclosure of Invention
The application provides an etching method applied to a subsequent procedure, which can solve the problem that the etching method in the subsequent procedure in the related technology can cause poor side appearance of a groove formed by etching due to insufficient photoresist amount, so that the yield of products is reduced.
In one aspect, an embodiment of the present application provides an etching method applied in a subsequent process, including:
covering a photoresist in a target area of a second hard mask layer through a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a second dielectric layer, the second dielectric layer is formed on a first dielectric layer, the first dielectric layer is formed on an interlayer dielectric and a metal through hole formed in the interlayer dielectric, and the target area is other areas on the second hard mask layer except for the area above the metal through hole;
removing the second hard mask layer, the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by etching;
carbonizing the light resistance;
and etching to remove the second dielectric layer with the second preset depth.
Optionally, the removing, by etching, the second hard mask layer, the first hard mask layer and the second dielectric layer with the first predetermined depth above the metal via includes:
removing the second hard mask layer above the metal through hole by first dry etching;
and removing the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by using a second dry etching method, wherein the reaction gas of the first dry etching method is different from that of the second dry etching method.
Optionally, the second hard mask layer comprises a bottom anti-reflective coating (BARC).
Optionally, the reaction gas for the first dry etching includes carbon tetrafluoride (CF)4) Oxygen (O)2) And argon (Ar).
Optionally, the first hard mask layer includes a dielectric anti-reflective coating (DARC).
Optionally, the second dielectric layer includes a Plasma Enhanced Oxide (PEOX).
Optionally, the reaction gas for the second dry etching includes trifluoromethane (CHF)3) And carbon tetrafluoride.
Optionally, the carbonizing the photoresist includes:
by containing carbon tetrafluoride, hydrogen (H)2) And carrying out carbonization treatment on the light resistor by using reaction gas of argon gas to form a hard protective layer on the surface of the light resistor.
Optionally, the etching to remove the second dielectric layer with the second predetermined depth includes:
and removing the second dielectric layer with the second preset depth through third dry etching.
Optionally, the first dielectric layer includes nitride doped silicon carbide (NDC).
Optionally, the reaction gas for the third dry etching includes trifluoromethane and carbon tetrafluoride.
The technical scheme at least comprises the following advantages:
after the second hard mask layer, the first hard mask layer and the second medium layer with the first preset depth above the metal through hole are removed through etching, the photoresist is carbonized, then the second medium layer with the second preset depth is removed through etching, the surface of the photoresist can be firm after the carbonization treatment is carried out on the photoresist, and the photoresist with the firm surface can keep a better appearance in the etching process, so that the problem that the appearance of the side edge of the groove formed through etching is poor due to insufficient photoresist is solved, and the yield is improved to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIGS. 1 and 2 are schematic diagrams of a M1 metal etching process in a subsequent step of semiconductor manufacturing provided in the related art;
FIG. 3 is a flow chart of an etching method applied in a subsequent process according to an exemplary embodiment of the present application;
fig. 4 to 7 are schematic diagrams of an etching method applied in a subsequent process according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 3, a flow chart of an etching method applied in a subsequent process according to an exemplary embodiment of the present application is shown, where the method includes:
Referring to fig. 4, a cross-sectional view of a photoresist overlay on an interconnect structure by a photolithographic process is shown. As shown in fig. 4, a metal via 412 is formed in the interlayer dielectric 411, a first dielectric layer 420 is formed on the interlayer dielectric 411 and the metal via 412, a second dielectric layer 430 is formed on the first dielectric layer 420, a first hard mask layer 440 is formed on the second dielectric layer 430, a second hard mask layer 450 is formed on the first hard mask layer 440, and a photoresist 460 may be covered on the target region by a photolithography process. Wherein the target area is the area on second hard mask layer 450 other than the area above metal via 412.
Exemplary "cover photoresist 460 in the target area by a photolithography process" includes, but is not limited to: coating a photoresist 460 on the second hard mask layer 450; exposing the photoresist 460 in the area above the metal via 412; the photoresist 460 is removed by development in the area above the metal via 412.
Optionally, in this embodiment, the interlayer dielectric layer 411 includes a low dielectric constant (low-K) material, and the low dielectric constant material may be a material with a dielectric constant K lower than 4 (e.g. silicon oxide SiO or silicon dioxide SiO)2) (ii) a Optionally, in the embodiment of the present application, the metal via 412 includes tungsten (W).
Optionally, in the embodiment of the present application, the first dielectric layer 420 includes NDC, which includes, but is not limited to, nitrogen-doped silicon carbide (SiC); optionally, in the embodiment of the present application, the second dielectric layer 430 includes PEOX, which includes, but is not limited to, plasma enhanced silicon oxide (e.g., silicon oxide or silicon dioxide); optionally, in the embodiment of the present application, the first hard mask layer 440 includes DARC, which includes, but is not limited to, nitrogen-doped silicon oxide (e.g., silicon oxide or silicon dioxide); optionally, in the embodiment of the present application, the second hard mask layer 450 includes a BARC.
And 302, removing the second hard mask layer, the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by etching.
Referring to fig. 5, a schematic cross-sectional view of the second hard mask layer, the first hard mask layer and the second dielectric layer at the first predetermined depth over the metal via removed by etching is output. As shown in fig. 5, the second hard mask layer and the first hard mask layer above the metal via 412 are removed, and the second dielectric layer 430 is etched to a first predetermined depth h1 to form a first trench 401.
Optionally, in step 302, "removing the second hard mask layer, the first hard mask layer and the second dielectric layer at the first predetermined depth above the metal via by etching" includes but is not limited to: removing the second hard mask layer over the metal via 412 by a first dry etch (this etch step may be referred to as a BARC open etch); the first hard mask layer and the second dielectric layer 430 of the first predetermined depth h1 above the metal via 412 are removed by a second dry etch (this etch step may be referred to as a top critical dimension definition etch). Wherein, the reaction gas of the first dry etching and the second dry etching is different.
For example, the reaction gas for the first dry etching includes carbon tetrafluoride, oxygen, and argon; the reaction gas for the second dry etching includes trifluoromethane and carbon tetrafluoride.
Referring to fig. 6, a schematic cross-sectional view of a photoresist carbonized is shown. As shown in fig. 6, a hard protective layer 461 is formed on the surface of the photoresist 460 by the carbonization process.
Optionally, in step 303, "carbonizing the photoresist" includes but is not limited to: the photoresist 460 is subjected to the carbonization process by a reaction gas including carbon tetrafluoride, hydrogen, and argon, and a hard protective layer 461 is formed on the surface of the photoresist 460.
And 304, etching to remove the second dielectric layer with a second preset depth.
Referring to fig. 7, a schematic cross-sectional view of the second dielectric layer etched to a second predetermined depth is shown. As shown in fig. 7, the second dielectric layer 430 is etched to a target depth h (the target depth h2 is the sum of the first predetermined depth h1 and the second predetermined depth h 2) using the carbonized photoresist 460 as a mask, thereby forming a second trench 402.
Optionally, in step 304, the "etching to remove the second dielectric layer at the second predetermined depth" includes but is not limited to: and removing the second dielectric layer with the second preset depth h2 by third dry etching. Illustratively, the reaction gas for the third dry etching includes trifluoromethane and carbon tetrafluoride.
To sum up, in the embodiment of the present application, after the second hard mask layer, the first hard mask layer and the second dielectric layer with the first predetermined depth above the metal through hole are removed by etching, the photoresist is carbonized, and then the second dielectric layer with the second predetermined depth is removed by etching.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (11)
1. An etching method applied to a subsequent process is characterized by comprising the following steps:
covering a photoresist in a target area of a second hard mask layer through a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a second dielectric layer, the second dielectric layer is formed on a first dielectric layer, the first dielectric layer is formed on an interlayer dielectric and a metal through hole formed in the interlayer dielectric, and the target area is other areas on the second hard mask layer except for the area above the metal through hole;
removing the second hard mask layer, the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by etching;
carbonizing the light resistance;
and etching to remove the second dielectric layer with the second preset depth.
2. The method of claim 1, wherein removing the second hard mask layer, the first hard mask layer and the second dielectric layer at the first predetermined depth over the metal via by etching comprises:
removing the second hard mask layer above the metal through hole by first dry etching;
and removing the first hard mask layer and the second dielectric layer with the first preset depth above the metal through hole by using a second dry etching method, wherein the reaction gas of the first dry etching method is different from that of the second dry etching method.
3. The method of claim 2, wherein the second hard mask layer comprises a BARC.
4. The method of claim 3, wherein the reaction gas of the first dry etching comprises carbon tetrafluoride, oxygen and argon.
5. The method of claim 2, wherein the first hard mask layer comprises DARC.
6. The method of claim 5, wherein the second dielectric layer comprises PEOX.
7. The method according to claim 6, wherein the reaction gas for the second dry etching comprises trifluoromethane and carbon tetrafluoride.
8. The method of claim 1, wherein the carbonizing the photoresist comprises:
and carrying out carbonization treatment on the photoresist by using reaction gas containing carbon tetrafluoride, hydrogen and argon, and forming a hard protective layer on the surface of the photoresist.
9. The method of claim 1, wherein the etching to remove the second dielectric layer to a second predetermined depth comprises:
and removing the second dielectric layer with the second preset depth through third dry etching.
10. The method of claim 9, wherein the first dielectric layer comprises NDC.
11. The method according to claim 10, wherein the reaction gas for the third dry etching comprises trifluoromethane and carbon tetrafluoride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010342342.7A CN111524854B (en) | 2020-04-27 | 2020-04-27 | Etching method applied to subsequent process |
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| CN202010342342.7A CN111524854B (en) | 2020-04-27 | 2020-04-27 | Etching method applied to subsequent process |
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| CN111524854A true CN111524854A (en) | 2020-08-11 |
| CN111524854B CN111524854B (en) | 2022-08-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670174A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN113506768A (en) * | 2021-06-22 | 2021-10-15 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565216A (en) * | 2018-05-31 | 2018-09-21 | 上海华力集成电路制造有限公司 | The reworking method of dual damascene via technique |
| CN110854073A (en) * | 2019-11-26 | 2020-02-28 | 上海华力集成电路制造有限公司 | Method for manufacturing grid |
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2020
- 2020-04-27 CN CN202010342342.7A patent/CN111524854B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108565216A (en) * | 2018-05-31 | 2018-09-21 | 上海华力集成电路制造有限公司 | The reworking method of dual damascene via technique |
| CN110854073A (en) * | 2019-11-26 | 2020-02-28 | 上海华力集成电路制造有限公司 | Method for manufacturing grid |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670174A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN112670174B (en) * | 2020-12-23 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN113506768A (en) * | 2021-06-22 | 2021-10-15 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
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| CN111524854B (en) | 2022-08-16 |
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