CN111696917A - Etching method of metal interconnection structure - Google Patents
Etching method of metal interconnection structure Download PDFInfo
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- CN111696917A CN111696917A CN202010679473.4A CN202010679473A CN111696917A CN 111696917 A CN111696917 A CN 111696917A CN 202010679473 A CN202010679473 A CN 202010679473A CN 111696917 A CN111696917 A CN 111696917A
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- layer
- hard mask
- metal
- mask layer
- photoresist
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 67
- 239000002184 metal Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000005530 etching Methods 0.000 title claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 238000009966 trimming Methods 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 239000000460 chlorine Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052801 chlorine Inorganic materials 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 102100022717 Atypical chemokine receptor 1 Human genes 0.000 claims 1
- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000012495 reaction gas Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses an etching method of a metal interconnection structure, which comprises the following steps: covering the photoresist in other areas except the target area of a second hard mask layer by a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a metal layer, and the metal layer is formed on a dielectric layer and a metal connecting wire formed in the dielectric layer; trimming the photoresist to thin the photoresist; etching and removing the second hard mask layer and the first hard mask layer in the target region until the metal layer in the target region is exposed; and removing the photoresist. According to the method, before the hard mask layer of the metal interconnection structure is etched, the photoresist is trimmed, so that the key size of the photoresist can be reduced in the initial process of subsequent etching, the size of the bottom of the photoresist can be reduced, the roughness of the side wall of the photoresist is reduced, the subsequent etched structure has a good appearance, and the stability and the manufacturing yield of a device are improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to an etching method of a metal interconnection structure.
Background
In the back end of line (BEOL) process of semiconductor manufacturing, a damascene process is usually adopted, in which a trench of a metal connection line is formed on a dielectric layer by etching, then metal is filled, and after the metal is planarized, the above processes are repeated until a metal interconnection structure is formed.
Referring to fig. 1, there is shown a schematic cross-sectional view of a photoresist covering a hard mask layer during etching of a metal interconnect structure provided in the related art; referring to fig. 2, a schematic cross-sectional view of a hard mask layer after etching during etching of a metal interconnect structure provided in the related art is shown.
As shown in fig. 1, a metal line 111 is formed in a dielectric layer 110, a metal layer 120, a first hard mask layer 130 and a second hard mask layer 140 are sequentially formed on the dielectric layer 110 and the metal line 111, and a photoresist 101 is covered on the second hard mask layer 140 except for a target region by a photolithography process.
As shown in fig. 2, the second hard mask layer 140 and the first hard mask layer 130 are sequentially etched to expose the metal layer 120 of the target region.
As shown in fig. 2, the structure formed by the etching method provided in the related art (as shown by the dotted line in fig. 2) has a poor morphology, and the width of the bottom of the structure is greater than the width of the top of the structure, so that there is a greater probability of voids (void) in the subsequent process, which results in a leakage phenomenon caused by metal bridges between metal lines, and reduces the manufacturing yield of semiconductor devices.
Disclosure of Invention
The application provides an etching method of a metal interconnection structure, which can solve the problems of high probability of electric leakage and low manufacturing yield caused by the etching method of a metal interconnection mechanism provided in the related technology.
In one aspect, an embodiment of the present application provides an etching method for a metal interconnection structure, which is characterized by including:
covering a photoresist in other areas except a target area of a second hard mask layer by a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a metal layer, and the metal layer is formed on a dielectric layer and a metal connecting line formed in the dielectric layer;
trimming the light resistor to thin the light resistor;
etching and removing the second hard mask layer and the first hard mask layer of the target region until the metal layer of the target region is exposed;
and removing the photoresist.
Optionally, the metal layer sequentially includes, from bottom to top, a first metal multilayer film, an aluminum layer, and a second metal multilayer film.
Optionally, the first metal multilayer film includes a composite layer composed of at least one titanium (Ti) layer and a titanium nitride (TiN) layer.
Optionally, the second metal multilayer film includes a composite layer composed of at least one titanium layer and a titanium nitride layer.
Optionally, the first hard mask layer includes a dielectric anti-reflective coating (DARC).
Optionally, the second hard mask layer comprises an oxide.
Optionally, the metal line includes tungsten (W).
Optionally, the trimming process performed on the photoresist includes:
and trimming the light resistor through a dry etching process.
Optionally, the reaction gas of the dry etching process includes oxygen (O)2) And/or chlorine (Cl)2)。
Optionally, the etching removes a reactive gas in the second hard mask layer and the first hard mask layer of the target region, the reactive gas including trifluoromethane (CHF)3) At least one of argon (Ar) and chlorine.
The technical scheme at least comprises the following advantages:
by trimming the photoresist before etching the hard mask layer of the metal interconnection structure, the key size of the photoresist can be reduced in the initial process of subsequent etching, the size of the bottom of the photoresist can be reduced, and the roughness of the side wall of the photoresist is reduced, so that the subsequent etched structure has better appearance, and the stability and the manufacturing yield of a device are improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 2 are flow charts of etching of a metal interconnect structure provided in the related art;
FIG. 3 is a flow chart of a method for etching a metal interconnect structure provided in an exemplary embodiment of the present application;
fig. 4 to 6 are flow charts of etching a metal interconnect structure according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 3, a flow chart of a method for etching a metal interconnect structure according to an exemplary embodiment of the present application is shown, the method including:
Referring to fig. 4, a cross-sectional view of a photoresist overlying a hard mask layer in an exemplary embodiment of the present application is shown. As shown in fig. 4, a metal line 411 is formed in the dielectric layer 410, a metal layer 420 is formed on the dielectric layer 410 and the metal line 411, a first hard mask layer 430 is formed on the metal layer 420, a second hard mask layer 440 is formed on the first hard mask layer 430, and the photoresist 401 covers the second hard mask layer 440 except the target region.
Optionally, in this embodiment, the dielectric layer 410 is made of Tetraethoxysilane (TEOS); optionally, the metal line 411 may be made of tungsten.
Optionally, in this embodiment of the application, the metal layer 420 sequentially includes, from bottom to top, a first metal multilayer film 421, an aluminum layer 422, and a second metal multilayer film 423. Wherein:
the first metal multilayer film 421 may include a composite layer of at least a titanium layer 4211 and a titanium nitride layer 4212 (fig. 4 exemplifies that the first metal multilayer film 421 includes one composite layer). Optionally, titanium layer 4211 has a thickness of 50 to 150 angstroms (e.g., may be 100 angstroms); optionally, titanium nitride layer 4212 has a thickness of 150 angstroms to 250 angstroms (e.g., may be 200 angstroms).
The aluminum layer 422 has a thickness of 3000 angstroms to 5000 angstroms (e.g., may be 4350 angstroms).
The second metal multilayer film 423 may include at least one composite layer of a titanium layer 4231 and a titanium nitride layer 4232 (fig. 4 illustrates that the second metal multilayer film 423 includes one composite layer). Optionally, titanium layer 4231 is 50 to 150 angstroms (e.g., may be 100 angstroms) thick; optionally, titanium nitride layer 4232 is 300 angstroms to 400 angstroms (e.g., may be 350 angstroms) thick.
Optionally, in the embodiment of the present application, the first hard mask layer 430 includes DARC (which may be silicon oxynitride SiON); optionally, the first hard mask layer 430 has a thickness of 230 to 330 angstroms (e.g., it may be 280 angstroms).
Optionally, in the present embodiment, the second hard mask layer 440 includes an oxide (which may be silicon dioxide, SiO)2) (ii) a Optionally, the second hard mask layer 440 has a thickness of 25 to 75 angstroms (e.g., it may be 50 angstroms).
Referring to fig. 5, a cross-sectional view of the photo resist after trimming is shown. As shown in fig. 5, after trimming the photoresist 401, the photoresist 401 is reduced in size and the sidewalls thereof are smoother.
Optionally, in step 302, trimming the photoresist 401 by a dry etching process; optionally, the reaction gas of the dry etching process includes oxygen and/or chlorine. By setting the reaction gas of the etching process to be oxygen and nitrogen, the shape of the trimmed photoresistance can be better.
Referring to fig. 6, a schematic cross-sectional view after etching the target area is shown. Illustratively, as shown in fig. 6, in the embodiment of the present application, the etching of the second hard mask layer 440 and the first hard mask layer 430 is performed in the same etching step, and the reaction gas during the etching process includes at least one of trifluoromethane, argon and chlorine. The resulting structure (shown by the dotted line in fig. 6) formed after the etching in step 303 has a small difference in upper and lower widths and a good morphology.
In step 304, the photoresist is removed.
To sum up, in the embodiment of the present application, the photoresist is trimmed before the hard mask layer of the metal interconnection structure is etched, so that the critical dimension of the photoresist can be reduced in the initial process of subsequent etching, the dimension of the bottom of the photoresist can be reduced, and the roughness of the sidewall of the photoresist is reduced, so that the subsequent etched structure has a better morphology, and the stability and the manufacturing yield of the device are improved.
In an alternative embodiment, after step 303 in the embodiment of fig. 3, step 304 further includes: etching to remove the second metal multilayer film 423 in the target area; etching to remove the aluminum layer 422 of the target region (this step is a Main Etching (ME) step); etching to remove the first metal multilayer film 421 in the target region (this step is a first over-etching (OE) step); the dielectric layer 410 of the target area is etched to a predetermined depth (this step is a second over-etch step).
Wherein the reaction gas for etching to remove the second metal multilayer film 423 in the target region comprises boron trichloride (BCl)3) And/or chlorine; the reaction gas for etching to remove the aluminum layer 422 in the target region comprises boron trichloride, chlorine, and nitrogen (N)2) And methane (CH)4) At least one of (1).
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. An etching method of a metal interconnection structure is characterized by comprising the following steps:
covering a photoresist in other areas except a target area of a second hard mask layer by a photoetching process, wherein the second hard mask layer is formed on a first hard mask layer, the first hard mask layer is formed on a metal layer, and the metal layer is formed on a dielectric layer and a metal connecting line formed in the dielectric layer;
trimming the light resistor to thin the light resistor;
etching and removing the second hard mask layer and the first hard mask layer of the target region until the metal layer of the target region is exposed;
and removing the photoresist.
2. The method of claim 1, wherein the metal layer comprises a first metal multilayer film, an aluminum layer and a second metal multilayer film from bottom to top.
3. The method of claim 1, wherein the first metallic multilayer film comprises a composite layer of at least one titanium layer and a titanium nitride layer.
4. The method of claim 3, wherein the second metallic multilayer film comprises a composite layer of at least one titanium layer and a titanium nitride layer.
5. The method of claim 1, wherein the first hard mask layer comprises DARC.
6. The method of claim 5, wherein the second hard mask layer comprises an oxide.
7. The method of claim 1, wherein the metal line comprises tungsten.
8. The method according to any one of claims 1 to 7, wherein the trimming of the photoresist comprises:
and trimming the light resistor through a dry etching process.
9. The method of claim 8, wherein the reactive gas of the dry etching process comprises oxygen and/or chlorine.
10. The method of any of claims 1 to 7, wherein the etching removes the reactive gas in the second hard mask layer and the first hard mask layer of the target region and comprises at least one of trifluoromethane, argon, and chlorine.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010679473.4A CN111696917A (en) | 2020-07-15 | 2020-07-15 | Etching method of metal interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010679473.4A CN111696917A (en) | 2020-07-15 | 2020-07-15 | Etching method of metal interconnection structure |
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| Publication Number | Publication Date |
|---|---|
| CN111696917A true CN111696917A (en) | 2020-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010679473.4A Pending CN111696917A (en) | 2020-07-15 | 2020-07-15 | Etching method of metal interconnection structure |
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| CN (1) | CN111696917A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670174A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN112967997A (en) * | 2021-02-02 | 2021-06-15 | 长江存储科技有限责任公司 | Back-end metal filling method, filling device, storage device and semiconductor device |
| CN117473933A (en) * | 2023-12-25 | 2024-01-30 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
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| CN101937175A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN105097648A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| CN111128770A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad and device containing aluminum pad |
-
2020
- 2020-07-15 CN CN202010679473.4A patent/CN111696917A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101937175A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Photoetching method |
| CN105097648A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| CN111128770A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad and device containing aluminum pad |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112670174A (en) * | 2020-12-23 | 2021-04-16 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN112670174B (en) * | 2020-12-23 | 2022-07-19 | 华虹半导体(无锡)有限公司 | Method for forming rear end structure |
| CN112967997A (en) * | 2021-02-02 | 2021-06-15 | 长江存储科技有限责任公司 | Back-end metal filling method, filling device, storage device and semiconductor device |
| CN117473933A (en) * | 2023-12-25 | 2024-01-30 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
| CN117473933B (en) * | 2023-12-25 | 2024-04-09 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
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Application publication date: 20200922 |