CN117473933A - Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium - Google Patents
Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
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Abstract
The application relates to a capacitor bank creation method, comprising the following steps: determining model sampling parameters corresponding to a model structure, wherein the model structure comprises a first conductor positioned on a first metal layer, a second conductor positioned on a second metal layer and at least one dielectric layer positioned between the first metal layer and the second metal layer, and the model sampling parameters are used for indicating structural information of the model structure; acquiring at least one sampling structure of the model structure based on the model sampling parameters; a capacitance bank is created based on the at least one sampling structure and the sidewall capacitance values and/or the face capacitance values and/or the coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure. The capacitor bank creation method, the capacitor acquisition method, the electronic device and the storage medium can improve the solving efficiency of the side wall capacitor and/or the surface capacitor and/or the coupling capacitor and the like, have high accuracy, can adapt to scenes of a plurality of medium layers, and have good adaptability.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a method for creating a capacitor bank, a method for obtaining a capacitor, an electronic device, and a storage medium.
Background
The integrated circuit (integrated circuit) is a microelectronic device or component. The components such as transistors, resistors, capacitors, inductors and the like required in a circuit and wiring are interconnected together by adopting a certain process, are manufactured on a small or a few small semiconductor wafers or dielectric substrates, and are then packaged in a tube shell to form a microstructure with the required circuit function; all the components are structurally integrated, so that the electronic components are greatly advanced towards microminiaturization, low power consumption, intellectualization and high reliability.
In the design flow of the integrated circuit, firstly, functional description is put forward, then, the layout describing the technological size and structure of the semiconductor is obtained through logic design and layout design, and finally, layout verification is carried out, namely, whether the design meets the requirements is verified through computer software simulation. If the requirements are met, the next production and manufacture are carried out. Otherwise, if the requirements are not met, returning to the logic design and carrying out necessary correction on the layout design. In layout verification, an important link is "extraction of interconnection parasitic parameters".
With the development of integrated circuit manufacturing technology, the scale of circuits is continuously increasing and the feature size is continuously shrinking, and the number of devices contained in many advanced chips today is over one hundred million. The parasitic effects of interconnect lines in integrated circuits have caused interconnect lines to have exceeded the effects of devices on circuit delay. Therefore, accurate calculation of the parasitic capacitance of the interconnect is required to ensure correct validity of circuit simulation and verification.
However, the existing parasitic capacitance, particularly the sidewall capacitance, has strict parameter constraint conditions, and has low adaptability and low accuracy along with the change of the manufacturing process.
Disclosure of Invention
Aiming at the technical problems, the application provides a capacitor bank creation method which can improve the efficiency and accuracy of parasitic capacitance extraction and has good adaptability.
In order to solve the technical problems, the application provides a capacitor bank creation method, which comprises the following steps: determining model sampling parameters corresponding to a model structure, wherein the model structure comprises a first conductor positioned on a first metal layer, a second conductor positioned on a second metal layer and at least one dielectric layer positioned between the first metal layer and the second metal layer, and the model sampling parameters are used for indicating structural information of the model structure; acquiring at least one sampling structure of the model structure based on the model sampling parameters; a capacitance bank is created based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure.
In an embodiment, the model sampling parameter at least includes etching effect thickness and/or thickness information of the dielectric layer.
In one embodiment, the step of determining model sampling parameters corresponding to the model structure includes: determining a reference thickness of a first dielectric layer, wherein the first dielectric layer is located between the first metal layer and the second metal layer and adjacent to the first conductor; obtaining etching effect thickness information; and determining thickness information of the first dielectric layer according to the reference thickness of the first dielectric layer and the etching effect thickness.
In an embodiment, the model structure further comprises a third conductor and/or a fourth conductor located in the first metal layer.
In an embodiment, the step of creating a capacitance bank based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure comprises: acquiring a coupling capacitance value and a surface capacitance value between the first conductor and the second conductor under the at least one sampling structure; obtaining the side wall capacitance value according to the coupling capacitance value and the surface capacitance value; a capacitance bank is created based on at least one sampling structure, sidewall capacitance values between the first conductor and the second conductor under the at least one sampling structure.
In an embodiment, acquiring the coupling capacitance value and the area capacitance value between the first conductor and the second conductor under the at least one sampling structure includes: calculating a coupling capacitance value between the first conductor and the second conductor under the at least one sampling structure based on a capacitance extraction algorithm; and/or calculating a sampling plane capacitance between the first conductor and the second conductor under the at least one sampling structure based on dielectric layer thickness information, wherein the dielectric layer thickness information comprises thickness information of a first dielectric layer.
In one embodiment, the model structure includes a plurality of dielectric layers between the first metal layer and the second metal layer;
creating a capacitance bank based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure comprises:
and acquiring the surface capacitance value based on the capacitance value corresponding to each dielectric layer arranged between the first conductor and the second conductor.
In one embodiment, the calculation formula of the face capacitance value is as follows: 1/C total ＝1/C 1 +1/C 2 +……+1/C n ；C n ＝(ε 0 ×ε n ×S)/d n The method comprises the steps of carrying out a first treatment on the surface of the Wherein C is total For the face capacitance value, C n For the surface capacitance value epsilon corresponding to the medium in the nth layer among the medium layers 0 And epsilon n The relative dielectric constants of the vacuum dielectric constant and the n-th dielectric layer are respectively represented, S represents the facing area of the first conductor and the second conductor, and d n Indicating thickness information of the n-th dielectric layer.
The application also provides a capacitance acquisition method, which comprises the following steps: acquiring the capacitor bank created by the capacitor bank creation method; determining a sampling structure matched with the target structure from the capacitor bank based on the target structure matched with the model structure; and determining a target side wall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitance library according to the matched sampling structure.
In an embodiment, the step of determining the target sidewall capacitance value and/or the target surface capacitance value and/or the target coupling capacitance value of the target structure based on the capacitor bank according to the matched sampling structure comprises: and inquiring a side wall capacitance value corresponding to the sampling structure from the capacitance library, and determining the side wall capacitance value as a target side wall capacitance value of the target structure.
In an embodiment, the capacitance acquisition method further includes: if the target structure is not matched with any sampling structure in the capacitor bank, an interpolation algorithm is adopted to obtain a target side wall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitor bank.
In an embodiment, the capacitance acquisition method further includes: and accumulating the target surface capacitance value and the target side wall capacitance value to obtain a target coupling capacitance value of the target structure.
The present application also provides an electronic device comprising a memory and a processor for enabling the method described above when executing a computer program in the memory.
The present application also provides a storage medium having stored thereon a computer program which, when executed by a processor, is capable of implementing the above-mentioned method.
The capacitor bank creation method, the capacitor acquisition method, the electronic device and the storage medium can be used for creating the capacitor bank which can correspond to the side wall capacitor and/or the surface capacitor and/or the coupling capacitor, so that the solving efficiency of the side wall capacitor and/or the surface capacitor and/or the coupling capacitor and the like can be improved, the accuracy is high, the capacitor bank can adapt to scenes of a plurality of medium layers, and the adaptability is good.
Drawings
Fig. 1 is a flow chart illustrating a capacitive library creation method according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional structure of a model structure according to a first embodiment of the present application.
Fig. 3 is a schematic cross-sectional structure of a model structure according to a second embodiment of the present application.
Fig. 4 is a schematic diagram of a sampling structure according to an embodiment of the present application.
Fig. 5 is a flow chart illustrating a capacitance acquisition method according to an embodiment of the present application.
Detailed Description
Further advantages and effects of the present application will be readily apparent to those skilled in the art from the present disclosure, by describing the embodiments of the present application with specific examples.
In the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Although the terms first, second, etc. may be used herein to describe various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.
First embodiment
Fig. 1 is a flow chart illustrating a capacitive library creation method according to a first embodiment of the present application. As shown in fig. 1, a method for creating a capacitor bank includes the following steps:
s10: determining model sampling parameters corresponding to the model structure;
in one embodiment, a model structure is located in an integrated circuit layout and includes a first conductor located on a first metal layer, a second conductor located on a second metal layer, and at least one dielectric layer located between the first metal layer and the second metal layer.
Fig. 2 is a schematic cross-sectional view of a model structure according to an embodiment, as shown in fig. 2, where the model structure includes a first conductor M, a second conductor B, and three dielectric layers disposed between the first conductor M and the second conductor B: dielectric layer 1, dielectric layer 2, dielectric layer 3. However, the relative positional relationship between the first conductor M and the second conductor B is not limited to that shown in fig. 2, and two dielectric layers, one dielectric layer, three or more dielectric layers, or the like may be disposed between the first conductor M and the second conductor B as long as the first conductor M and the second conductor B are disposed on different metal layers.
In an embodiment, the model structure may further comprise a third conductor and/or a fourth conductor. Specifically, in an embodiment, at least one of the third conductor and the fourth conductor is located in the first metal layer, that is, at least one of the third conductor and the fourth conductor is located in the same metal layer as the first conductor. The third conductor and the fourth conductor may be left and right environmental conductors of the first conductor, respectively. As shown in fig. 3, the model structure includes a first conductor M, a second conductor B, and two dielectric layers disposed between the first conductor M and the second conductor B. The model structure further includes a third conductor L and a fourth conductor R in the same metal layer as the first conductor M. However, the present application is not limited thereto, and the model structure may include only one of the third conductor L and the fourth conductor R, for example. The third conductor L and the fourth conductor R may be located in different metal layers. The relative position of at least one of the third conductor L and the fourth conductor R to the first conductor M is not limited to that shown in fig. 3.
Wherein,the model sampling parameters are used to indicate structural information of the model structure. In one embodiment, the model sampling parameters are used to uniquely determine the structural information of the model structure. In an embodiment, the model sampling parameters may be, but are not limited to being, preset by a user and/or system. Specifically, in an embodiment, the model sampling parameter may include, but is not limited to, at least one of a sampling width of the first conductor M, a sampling width of the second conductor B, a sampling offset displacement of centers of the first conductor M and the second conductor B in a horizontal direction, a thickness of each dielectric layer between the first conductor M and the second conductor B, and a change in thickness of a dielectric layer between the first conductor M and the second conductor B and adjacent to the first conductor M (i.e., a first dielectric layer) with respect to a reference thickness. As shown in fig. 2 and 3, the horizontal direction in the cross-sectional view is the width direction, and the width of the conductor is the length of the conductor in the width direction. As shown in fig. 4, the thickness of the dielectric layer (i.e., the first dielectric layer) between and adjacent to the first conductor M and the second conductor B can be varied from the reference thickness byAnd (3) representing.
In an embodiment, the model sampling parameters include at least etching effect thickness and/or thickness information of the dielectric layer. The thickness information of at least one dielectric layer is obtained based on the etching effect thickness, and specifically, the thickness information of at least one dielectric layer is obtained based on the etching effect thickness and the reference thickness of the dielectric layer.
The reference thickness refers to the theoretical thickness or standard thickness of the first dielectric layer in the reference sampling structure. In an embodiment, the variation of the thickness of the first dielectric layer from the reference thickness may be an etching effect thickness. Specifically, the thickness of the etching effect may be a variation of the thickness of the dielectric layer from the reference thickness due to a process effect, such as an etching load effect (also referred to as microloading effect). The value of the etching effect thickness may be, but is not limited to, obtained by a process file, specifically provided by a user of the parasitic parameter tool or by a wafer handling factory, the size of which is related to the width of the corresponding conductors, the spacing of the conductors.
Specifically, the thickness of the etching effect can be positive, negative or zero. Specifically, if the thickness of the first dielectric layer is greater than the reference thickness, the etching effect thickness is positive, if the thickness of the first dielectric layer is less than the reference thickness, the etching effect thickness is negative, and if the thickness of the first dielectric layer is equal to the reference thickness, the etching effect thickness is zero.
In one embodiment, the step of determining model sampling parameters corresponding to the model structure includes: determining a reference thickness of the first dielectric layer; obtaining etching effect thickness information; and determining thickness information of the first dielectric layer according to the reference thickness of the first dielectric layer and the etching effect thickness.
In other embodiments, the model sampling parameters may also, but are not limited to, include a sampling interval of the third conductor L and the first conductor M, a sampling interval of the fourth conductor R and the first conductor M, and so on.
In particular, in one embodiment, the model sampling parameters determined may be different when creating a capacitance library for different kinds of capacitance values. For example, model sampling parameters determined when creating a capacitive library for the face capacitance and a capacitive library for the side wall capacitance may be different. The surface capacitance is a capacitance that an electric field line formed by the first conductor M and the second conductor B is perpendicular to the second conductor B, and the sidewall capacitance is a capacitance that an electric field line formed by the first conductor M and the second conductor B is not perpendicular to the first conductor M and the second conductor B.
In one embodiment, the step of determining model sampling parameters corresponding to the model structure includes: at least a first conductor on the first metal layer and a second conductor on the second metal layer are defined.
In an embodiment, determining that the first conductor on the first metal layer and the second conductor on the second metal layer are model structures may include: acquiring metal layer information according to a process file, wherein the process file comprises information of multiple metal layers arranged from low to high or from high to low according to the distance from a substrate; sequentially traversing according to the sequence from low to high distance from the substrate, determining the currently traversed metal layer as a first metal layer, sequentially determining each metal layer above the currently traversed metal layer as a second metal layer, determining a first conductor from the first metal layer, determining a second conductor from the second metal layer, wherein the first metal layer and the second metal layer have distances specified in the process file. Specifically, for example, the metal layers include a metal layer 1, a metal layer 2, a metal layer 3 … …, and a metal layer n arranged from low to high or from high to low at a distance from the substrate, where n is a positive integer. If the currently traversed metal layer is the metal layer 1, determining the currently traversed metal layer 1 as a first metal layer, determining the metal layer 2 as a second metal layer, determining the metal layer 3 as a second metal layer, and the like until the metal layer n is determined as the second metal layer. If the currently traversed metal layer is the metal layer 2, determining the metal layer 2 as a first metal layer, determining the metal layer 3 as a second metal layer, determining the metal layer 4 as a second metal layer, and the like until the metal layer n is determined as the second metal layer.
In an embodiment, the process file may further include information about the structural dimensions of the conductors of each metal layer, the widths of the conductors in each metal layer, the spacing between conductors on each metal layer, the properties of the medium surrounding each metal layer, and the like.
S11: acquiring at least one sampling structure of the model structure based on the model sampling parameters;
specifically, a plurality of sampling structures of the model structure may be obtained based on different values of the above model sampling parameters. The more the number of sampling structures, the higher the accuracy of the capacitance value obtained by the interpolation algorithm, but the longer the time for creating the capacitance library.
S12: a capacitance bank is created based on the at least one sampling structure and the sidewall capacitance values and/or the face capacitance values and/or the coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure.
In an embodiment, creating the capacitance bank based on the at least one sampling structure and the sidewall capacitance value and/or the face capacitance value and/or the coupling capacitance value between the first conductor and the second conductor under the at least one sampling structure comprises: acquiring a coupling capacitance value and a surface capacitance value between a first conductor and a second conductor under at least one sampling structure; obtaining a side wall capacitance value according to the coupling capacitance value and the surface capacitance value; a capacitance bank is created based on the at least one sampling structure, the sidewall capacitance value between the first conductor and the second conductor under the at least one sampling structure. Specifically, the side wall capacitance value may be obtained by subtracting the face capacitance value from the coupling capacitance value (also called total capacitance value).
In one embodiment, obtaining the coupling capacitance value and the surface capacitance value between the first conductor and the second conductor under the at least one sampling structure includes: calculating a coupling capacitance value between the first conductor and the second conductor under at least one sampling structure based on a capacitance extraction algorithm; and/or calculating a sampling plane capacitance between the first conductor and the second conductor under at least one sampling structure based on the dielectric layer thickness information, wherein the dielectric layer thickness information comprises thickness information of the first dielectric layer. The capacitance extraction algorithm that calculates the coupling capacitance value between the first conductor and the second conductor may be a 3D field solver algorithm (e.g., finite difference algorithm, boundary element algorithm, random walk algorithm, etc.).
Specifically, in one embodiment, creating a capacitance bank based on at least one sampling structure and sidewall capacitance values between a first conductor and a second conductor under the at least one sampling structure comprises: and storing the plurality of sampling structures and the plurality of side wall capacitance values in a one-to-one correspondence mode respectively so as to establish a capacitance library under the model structure. The capacitor bank may be stored in a tabular form. In other embodiments, creating the capacitive library based on the sidewall capacitance value and/or the face capacitance value and/or the coupling capacitance value between the first conductor and the second conductor under the at least one sampling structure may further include, but is not limited to including: creating a capacitance library based on the at least one sampling structure and a face capacitance value between the first conductor and the second conductor under the at least one sampling structure; or creating a capacitance bank based on the at least one sampling structure and the sidewall capacitance and the panel capacitance between the first conductor and the second conductor under the at least one sampling structure; or based on the side wall capacitance value and the face capacitance value between the first conductor and the second conductor under at least one sampling structure, acquiring the coupling capacitance value between the first conductor and the second conductor, and creating a capacitance library based on the at least one sampling structure and the corresponding coupling capacitance value. For example, the plurality of sampling structures and the plurality of surface capacitance values are respectively stored in a one-to-one correspondence manner so as to create a capacitance library under the model structure, and for example, the plurality of sampling structures and the plurality of coupling capacitance values are respectively stored in a one-to-one correspondence manner so as to create the capacitance library under the model structure.
In an embodiment, when the model structure includes a plurality of dielectric layers between the first metal layer and the second metal layer, a principle of capacitive series connection may be used to obtain an equivalent plane capacitance value between the first conductor and the second conductor in the sampling structure. Specifically, in one embodiment, the step of obtaining the area capacitance value between the first conductor and the second conductor under at least one sampling structure includes: the surface capacitance value is obtained based on the capacitance value corresponding to each dielectric layer arranged between the first conductor and the second conductor.
Specifically, in one embodiment, the face capacitance value is calculated as follows:
1/C total ＝1/C 1 +1/C 2 +……+1/C n ；
C n ＝(ε 0 ×ε n ×S)/d n ；
wherein C is total For the face capacitance value, C n For the surface capacitance value epsilon corresponding to the medium in the nth layer among the medium layers 0 And epsilon n The relative dielectric constants of the vacuum dielectric constant and the n-th dielectric layer are respectively represented, S represents the facing area of the first conductor and the second conductor, and d n Indicating thickness information of the n-th dielectric layer.
Specifically, in one embodiment, the thickness information of the first dielectric layer (the dielectric layer between the first conductor M and the second conductor B and adjacent to the first conductor M, i.e. the dielectric layer close to the bottom of the first conductor M) can be represented by the reference thickness and the thickness variation from the reference thickness, i.e. d 1 ＝d+Wherein d is the sampling structure corresponding to the referenceThe thickness of the first dielectric layer, i.e. the reference thickness of the first dielectric layer,/>The thickness of the etching effect is the variation of the thickness of the first dielectric layer relative to the reference thickness.
The method for creating the capacitor bank can be used for creating the capacitor bank which can correspond to the side wall capacitor and/or the surface capacitor, so that the solving efficiency of the side wall capacitor and/or the surface capacitor and/or the coupling capacitor can be improved, the accuracy is high, the method can adapt to scenes of a plurality of dielectric layers, and the adaptability is good. In addition, in an embodiment, the thickness variation of the first dielectric layer, for example, the thickness of the etching effect, may be used as a model sampling parameter, so that a capacitance library for the sidewall capacitance value and/or the surface capacitance value and/or the coupling capacitance value is created based on the thickness variation of the first dielectric layer, and the efficiency of obtaining the sidewall capacitance value and/or the surface capacitance value and/or the coupling capacitance when the thickness variation of the first dielectric layer is caused by the etching load effect (also called microloading effect) can be improved.
Fig. 5 is a flow chart illustrating a capacitance acquisition method according to an embodiment of the present application. As shown in fig. 5, the capacitance acquisition method includes the steps of:
s50: acquiring a capacitor bank;
specifically, in one embodiment, the capacitor banks may be created by, but not limited to, sampling the methods described above.
S51: determining a sampling structure matched with the target structure from a capacitor bank based on the target structure matched with the model structure;
in one embodiment, if the values of the target structure corresponding to the model sampling parameters are the same as the values of the model sampling parameters in one of the sampling structures in the capacitor bank, then it is determined that the target structure matches one of the sampling structures in the capacitor bank. Specifically, the value corresponding to the model sampling parameter in the target structure may be, but not limited to, a width of the first conductor, a width of the second conductor, a thickness of the dielectric layer between the first conductor and the second conductor, a thickness variation of the first dielectric layer between the first conductor and the second conductor, such as an etching effect thickness, and the like.
S52: and determining a target side wall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitance library according to the matched sampling structure.
Specifically, in an embodiment, the step of determining, based on the capacitor bank, a target sidewall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure according to the matched sampling structure includes: and inquiring the sidewall capacitance value corresponding to the matched sampling structure from the capacitance library, and determining the sidewall capacitance value as a target sidewall capacitance value of the target structure. In other embodiments, the step of determining the target sidewall capacitance value and/or the target surface capacitance value of the target structure based on the capacitor bank may further include, but is not limited to, the following steps: inquiring a face capacitance value corresponding to the matched sampling structure from a capacitance library, and determining the face capacitance value as a target face capacitance value of a target structure; or inquiring the coupling capacitance value corresponding to the matched sampling structure from the capacitance library, and determining the coupling capacitance value as the target coupling capacitance value of the target structure.
In an embodiment, the step of determining the target sidewall capacitance value and/or the target surface capacitance value and/or the target coupling capacitance value of the target structure based on the capacitor bank according to the matched sampling structure may further include, but is not limited to, the steps of: and determining a target coupling capacitance value of the target structure based on the capacitor bank according to the matched sampling structure. Specifically, in one embodiment, the step of determining the target coupling capacitance value of the target structure based on the capacitance bank according to the matched sampling structure includes: inquiring a sidewall capacitance value corresponding to the matched sampling structure from a capacitance library, and determining the sidewall capacitance value as a target sidewall capacitance value of a target structure; acquiring a face capacitance value corresponding to a target sampling structure; and accumulating the target surface capacitance value and the target side wall capacitance value to obtain a target coupling capacitance value of the target structure. Specifically, the surface capacitance value corresponding to the target sampling structure may be obtained by, but not limited to, sampling in the foregoing manner, which is not described herein.
In an embodiment, the capacitance acquisition method further includes: and accumulating the target surface capacitance value and the target side wall capacitance value to obtain a target coupling capacitance value of the target structure.
The capacitance acquisition method can acquire the capacitance based on the capacitance library which can correspond to the side wall capacitance and/or the surface capacitance, can improve the solving efficiency of the side wall capacitance and/or the surface capacitance and/or the coupling capacitance, has high accuracy, can adapt to the scenes of a plurality of dielectric layers, and has good adaptability. In addition, in an embodiment, the thickness variation of the first dielectric layer may be used as a model sampling parameter, so that a capacitor bank for the sidewall capacitance value and/or the surface capacitance value and/or the coupling capacitance value is created based on the thickness variation of the first dielectric layer, and efficiency of acquiring the sidewall capacitance value and/or the surface capacitance value when the thickness variation of the first dielectric layer is caused by the etching load effect (also called microloading effect) can be improved.
The embodiment of the application also provides electronic equipment, which comprises a memory and a processor, wherein the processor is used for realizing the method when executing the computer program in the memory.
In particular, the processor may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), or may be configured to implement one or more integrated circuits of embodiments of the present application.
The memory may include, among other things, mass storage for data or instructions. By way of example, and not limitation, the memory may comprise a Hard Disk Drive (HDD), floppy Disk Drive, solid state Drive (Solid State Drive, SSD), flash memory, optical Disk, magneto-optical Disk, tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of the foregoing. The memory may include removable or non-removable (or fixed) media, where appropriate. The memory may be internal or external to the faulty image generation device, where appropriate. In a particular embodiment, the memory is a Non-Volatile (Non-Volatile) memory. In particular embodiments, the Memory includes Read-Only Memory (ROM) and random access Memory (Random Access Memory, RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, abbreviated PROM), an erasable PROM (Erasable Programmable Read-Only Memory, abbreviated EPROM), an electrically erasable PROM (Electrically Erasable Programmable Read-Only Memory, abbreviated EEPROM), an electrically rewritable ROM (Electrically Alterable Read-Only Memory, abbreviated EAROM), or a FLASH Memory (FLASH), or a combination of two or more of these. The RAM may be Static Random-Access Memory (SRAM) or dynamic Random-Access Memory (Dynamic Random Access Memory DRAM), where the DRAM may be a fast page mode dynamic Random-Access Memory (Fast Page Mode Dynamic Random Access Memory FPMDRAM), extended data output dynamic Random-Access Memory (Extended Date Out Dynamic Random Access Memory EDODRAM), synchronous dynamic Random-Access Memory (Synchronous Dynamic Random-Access Memory SDRAM), or the like, as appropriate.
The memory may be used to store or cache various data files that need to be processed and/or communicated, as well as possible computer program instructions for execution by the processor.
The processor implements any of the methods of the above embodiments by reading and executing computer program instructions stored in memory.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
The embodiment of the application also provides an intelligent terminal, which comprises: the device comprises a memory and a processor, wherein the memory stores an operation program, and the operation program realizes the steps of any one of the methods when being executed by the processor.
Embodiments of the present application also provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the methods described above.
The embodiments of the intelligent terminal and the computer readable storage medium provided in the present application may include all the technical features of any one of the above embodiments, and the expansion and explanation contents of the description are substantially the same as those of each embodiment of the above method, which are not repeated herein.
The present embodiments also provide a computer program product comprising computer program code which, when run on a computer, causes the computer to perform the method in the various possible implementations as above.
According to the capacitor bank creation method, the capacitor acquisition equipment and the capacitor medium, the normalization coefficient, the minimum first width of the first conductor and the minimum second width of the second conductor are adopted as the model sampling parameters for the model structure, so that independence among the model sampling parameters can be ensured, a capacitor bank can be more completely created, and the capacitor acquisition efficiency and accuracy are improved.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device of the embodiment of the application can be combined, divided and pruned according to actual needs.
In this application, the same or similar term concept, technical solution, and/or application scenario description will generally be described in detail only when first appearing, and when repeated later, for brevity, will not generally be repeated, and when understanding the content of the technical solution of the present application, etc., reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution, and/or application scenario description, etc., which are not described in detail later.
In this application, the descriptions of the embodiments are focused on, and the details or descriptions of one embodiment may be found in the related descriptions of other embodiments.
The technical features of the technical solutions of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the present application.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (14)
1. The capacitor bank creation method is characterized by comprising the following steps:
determining model sampling parameters corresponding to a model structure, wherein the model structure comprises a first conductor positioned on a first metal layer, a second conductor positioned on a second metal layer and at least one dielectric layer positioned between the first metal layer and the second metal layer, and the model sampling parameters are used for indicating structural information of the model structure;
based on the model sampling parameters, acquiring at least one sampling structure of the model structure, wherein the sampling structure takes a first conductor as a main conductor;
a capacitance bank is created based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure.
2. The method of claim 1, wherein the model sampling parameters include at least etching effect thickness and/or thickness information of the dielectric layer.
3. The method of creating a capacitive library according to claim 2, wherein the step of determining model sampling parameters corresponding to the model structure comprises:
determining a reference thickness of a first dielectric layer, wherein the first dielectric layer is located between the first metal layer and the second metal layer and adjacent to the first conductor;
obtaining etching effect thickness information;
and determining thickness information of the first dielectric layer according to the reference thickness of the first dielectric layer and the etching effect thickness.
4. The method of claim 1, wherein the model structure further comprises a third conductor and/or a fourth conductor on the first metal layer.
5. The method of creating a capacitive library according to claim 1 or 2, characterized by the step of creating a capacitive library based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure, comprising:
acquiring a coupling capacitance value and a surface capacitance value between the first conductor and the second conductor under the at least one sampling structure;
obtaining the side wall capacitance value according to the coupling capacitance value and the surface capacitance value;
a capacitance bank is created based on at least one sampling structure, sidewall capacitance values between the first conductor and the second conductor under the at least one sampling structure.
6. The method of creating a capacitive library according to claim 5, wherein acquiring the coupling capacitance value and the plane capacitance value between the first conductor and the second conductor in the at least one sampling structure comprises:
calculating a coupling capacitance value between the first conductor and the second conductor under the at least one sampling structure based on a capacitance extraction algorithm;
and/or the number of the groups of groups,
and calculating the sampling surface capacitance between the first conductor and the second conductor under the at least one sampling structure based on the thickness information of the dielectric layer, wherein the thickness information of the dielectric layer comprises the thickness information of the first dielectric layer.
7. The method of claim 1, wherein the model structure comprises a plurality of dielectric layers between the first metal layer and the second metal layer;
creating a capacitance bank based on at least one sampling structure and sidewall capacitance values and/or face capacitance values and/or coupling capacitance values between the first conductor and the second conductor under the at least one sampling structure comprises:
and acquiring the surface capacitance value based on the capacitance value corresponding to each dielectric layer arranged between the first conductor and the second conductor.
8. The method of creating a capacitive library according to claim 7, wherein the calculation formula of the face capacitance value is as follows:
1/C total ＝1/C 1 +1/C 2 +……+1/C n ；
C n ＝(ε 0 ×ε n ×S)/d n ；
wherein C is total For the face capacitance value, C n For the surface capacitance value epsilon corresponding to the medium in the nth layer among the medium layers 0 And epsilon n The relative dielectric constants of the vacuum dielectric constant and the n-th dielectric layer are respectively represented, S represents the facing area of the first conductor and the second conductor, and d n Indicating thickness information of the n-th dielectric layer.
9. A capacitance acquisition method, characterized in that the capacitance acquisition method comprises:
acquiring a capacitor bank created by the capacitor bank creation method according to claim 1;
determining a sampling structure matched with the target structure from the capacitor bank based on the target structure matched with the model structure;
and determining a target side wall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitance library according to the matched sampling structure.
10. The capacitance acquisition method according to claim 9, wherein the step of determining a target sidewall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitance library according to the matched sampling structure comprises:
and inquiring the sidewall capacitance value corresponding to the matched sampling structure from the capacitance library, and determining the sidewall capacitance value as a target sidewall capacitance value of the target structure.
11. The capacitance acquisition method according to claim 9, characterized in that the capacitance acquisition method further comprises:
if the target structure is not matched with any sampling structure in the capacitor bank, an interpolation algorithm is adopted to obtain a target side wall capacitance value and/or a target surface capacitance value and/or a target coupling capacitance value of the target structure based on the capacitor bank.
12. The capacitance acquisition method according to claim 9 or 10 or 11, characterized in that the capacitance acquisition method further comprises:
and accumulating the target surface capacitance value and the target side wall capacitance value to obtain a target coupling capacitance value of the target structure.
13. An electronic device comprising a memory and a processor for implementing the method according to any of claims 1-12 when executing a computer program in the memory.
14. A storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-12.
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