CN115310402A

CN115310402A - Adaptive parasitic capacitance lookup table generation method, device and system

Info

Publication number: CN115310402A
Application number: CN202210883317.9A
Authority: CN
Inventors: 拓晶; 刘毅; 李嵩
Original assignee: Hangzhou Xingxin Technology Co ltd
Current assignee: Hangzhou Xingxin Technology Co ltd
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2022-11-08
Anticipated expiration: 2042-07-26
Also published as: CN115310402B

Abstract

The application relates to a method, a device and a system for generating a self-adaptive parasitic capacitance lookup table, wherein the method for generating the self-adaptive parasitic capacitance lookup table comprises the following steps: acquiring a circuit template, determining first sampling points according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point; and under the condition that the first capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set. Through the method and the device, the problems of low efficiency, low precision and low process adaptation degree of extracting the parasitic capacitance to generate the parasitic capacitance lookup table by the fixed sampling point are solved, and the self-adaptive adjustment of the sampling point data according to different precisions and different process requirements is realized, so that the parasitic capacitance lookup table is manufactured efficiently and precisely.

Description

Adaptive parasitic capacitance lookup table generation method, device and system

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, and a system for generating an adaptive parasitic capacitance lookup table.

Background

In the layout verification of an integrated circuit, an important link is the extraction of the parasitic capacitance of a conductor. In current Electronic Design Automation (EDA) software, pattern matching (pattern match) is generally adopted as a parasitic capacitance extraction tool at a layout check (sign off) stage. The pattern matching refers to a process of matching the abstracted graph in the layout design with a circuit template in a parasitic capacitance lookup table to obtain the parasitic capacitance, and if the abstracted graph is different from the circuit template in the parasitic capacitance lookup table in size, an interpolation method of adjacent sampling points is adopted.

In the related art that the current pattern matching is used as a parasitic capacitance extraction tool, all the circuit templates use fixed sampling points, so that a parasitic capacitance lookup table obtained through pattern matching is manufactured when the parasitic capacitance is extracted by a specified process of a wafer factory. Because a set of fixed and same sampling points are used for all wafer factory processes, the existing technical scheme for manufacturing the parasitic capacitance lookup table by using the fixed sampling points can not generate the parasitic capacitance lookup table which is matched with the sampling points suitable for the process for use in a mode aiming at a new process when the process is changed every time, so that the capacitance extraction precision is lowered under the new process.

Aiming at the problems that in the related technology, the accuracy of extracting the parasitic capacitance to generate the parasitic capacitance lookup table at a fixed sampling point is low and the lookup table is not adaptive to a new process, an effective solution is not provided at present.

Disclosure of Invention

The application provides a self-adaptive parasitic capacitance lookup table generation method, a device and a system, and aims to solve the problems that in the related technology, the accuracy of extracting a parasitic capacitance to generate a parasitic capacitance lookup table by a fixed sampling point is low, and the parasitic capacitance lookup table is not adaptive to a new process.

In a first aspect, the present application provides an adaptive parasitic capacitance lookup table generation method, including:

acquiring a circuit template, determining first sampling points according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point;

and under the condition that the first capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the first sampling points, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

Further, after the determining a first capacitance variation between two adjacent first sampling points according to the first capacitance component corresponding to each first sampling point, the method further includes:

under the condition that the first capacitance variation is larger than the maximum capacitance variation of the capacitance variation interval, determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation to obtain a first initial sampling point, and determining a second capacitance variation between the two adjacent first initial sampling points according to a second capacitance component corresponding to the first initial sampling point; wherein the first initial sampling points comprise the first sampling points and the second sampling points;

and under the condition that the second capacitance variation is in a preset capacitance variation interval, generating the target sampling point set according to the first initial sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

Further, the determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation includes:

determining a sampling step length according to a dichotomy or a random step length method, or acquiring a preset sampling step length;

and carrying out sampling calculation on the first sampling point according to the sampling step length and the process file to generate a second sampling point.

Further, after determining a second capacitance variation between two adjacent first initial sampling points according to a second capacitance component corresponding to the first initial sampling point, the method further includes:

under the condition that the second capacitance variation is larger than the maximum capacitance variation, determining a first current sampling point according to the first sampling point, and determining a first current capacitance variation between two adjacent first current sampling points according to the first current sampling point;

and repeating the steps until all the first current capacitance variation values are positioned in the capacitance variation value interval, obtaining the target sampling point set according to the first current sampling points, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

under the condition that the two adjacent first capacitance variation values are smaller than the minimum capacitance variation value in the capacitance variation value interval, removing a middle first sampling point of three first sampling points corresponding to the two first capacitance variation values to obtain a second initial sampling point;

determining a third capacitance variation between two adjacent second initial sampling points according to a third capacitance component corresponding to each second initial sampling point;

and under the condition that the third capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the second initial sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

Further, the determining a first sampling point according to the process file and a preset capacitance component threshold includes:

acquiring a preset fixed step length, and acquiring a preset characteristic size threshold and a preset capacitance component threshold;

for the circuit template, sampling according to a process file and the characteristic size threshold value in the fixed step length to determine at least one fixed sampling point for the circuit template, and extracting a fixed capacitance component corresponding to the fixed sampling point;

and repeating the steps until the fixed capacitance component is smaller than the capacitance component threshold value, and obtaining the first sampling point according to all the fixed sampling points.

In a second aspect, the present application provides a method for generating an adaptive parasitic capacitance lookup table, including:

the method comprises the steps of obtaining a circuit template, determining at least one first sampling point according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point;

obtaining the maximum first capacitance variation according to the first capacitance variation;

and under the condition that the maximum first capacitance variation is within a preset capacitance variation interval, generating a target sampling point set according to the first sampling points, and extracting the parasitic capacitance of all target sampling points in the target sampling point set.

Further, after obtaining a maximum first capacitance variation according to the first capacitance variation, the method further includes:

under the condition that the maximum first capacitance variation is larger than the maximum capacitance variation in a preset capacitance variation interval, determining second current sampling points according to a process file and a preset capacitance component threshold, and determining a second current capacitance variation between two adjacent second current sampling points according to each second current sampling point;

obtaining a maximum second current capacitance variation according to the second current capacitance variation;

and repeating the steps until the maximum second current capacitance variation is within a preset capacitance variation interval, generating a target sampling point set according to the second current sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

In a third aspect, the present application provides an adaptive parasitic capacitance lookup table generation apparatus, including: the device comprises an acquisition module and an extraction module;

the acquisition module is used for acquiring a circuit template, determining first sampling points according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point;

the extraction module is used for generating a target sampling point set according to the first sampling point and generating a corresponding parasitic capacitance lookup table according to the target sampling point set under the condition that the first capacitance variation is in a preset capacitance variation interval.

In a fourth aspect, the present application provides an adaptive parasitic capacitance lookup table generation system, including: a terminal device, a transmission device and a server device; the terminal equipment is connected with the server equipment through the transmission equipment;

the server device is used for implementing the sampling point extraction method of the first aspect;

the transmission equipment is used for transmitting the circuit template to the server equipment;

and the terminal equipment is used for loading the circuit template.

In a fifth aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the adaptive parasitic capacitance lookup table generation method according to the first aspect or the second aspect.

Compared with the prior art, the self-adaptive parasitic capacitance lookup table generation method, device and system provided by the application have the advantages that through the acquisition of the circuit template, the first sampling points are determined according to the circuit template and the preset threshold value of the capacitance component, and the first capacitance variation between two adjacent first sampling points is determined according to the first capacitance component corresponding to each first sampling point; and under the condition that the first capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set. The self-adaptive parasitic capacitance lookup table generation method can obtain more representative sampling points, including deleting a redundant middle first sampling point, a target sampling point set is obtained according to a preset capacitance component threshold value and a preset capacitance variation interval, and meanwhile, sampling points are increased in a targeted mode, so that sampling point data and a parasitic capacitance lookup table corresponding to the finally obtained target sampling point set are more in line with process size parameters of a wafer factory, the precision requirements of different processes are better adapted, the problem of redundant and miscellaneous workload of repeatedly generating the parasitic capacitance lookup table for each process is flexibly solved, and the parasitic capacitance lookup table with higher precision is provided.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a diagram illustrating an exemplary implementation of a method for generating an adaptive parasitic capacitance lookup table;

FIG. 2 is a flow diagram illustrating a method for generating an adaptive parasitic capacitance lookup table in accordance with one embodiment;

FIG. 3 is a flowchart illustrating a method for generating a parasitic capacitance lookup table according to another embodiment;

FIG. 4 is a flowchart illustrating a method for generating a parasitic capacitance lookup table in accordance with yet another embodiment;

FIG. 5 is a flowchart illustrating a method for generating a parasitic capacitance lookup table according to yet another embodiment;

FIG. 6 is a schematic diagram of a circuit template in one embodiment;

FIG. 7 is a block diagram of an apparatus for generating an adaptive parasitic capacitance lookup table in one embodiment;

FIG. 8 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings. The terms "first," "second," "third," and the like in this application are used for distinguishing between similar items and not necessarily for describing a particular sequential or chronological order.

The adaptive parasitic capacitance lookup table generation method provided by the application can be applied to the application environment shown in fig. 1. Wherein the terminal device 102 communicates with the server device 104 over a network. The server device 104 acquires a circuit template loaded by the terminal device 102, determines first sampling points according to the circuit template and a preset capacitance component threshold, and determines a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point; the server device 104 generates a target sampling point set according to the first sampling point and generates a corresponding parasitic capacitance lookup table according to the target sampling point set when the first capacitance variation is within a preset capacitance variation interval. The terminal device 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices, and the server device 104 may be implemented by an independent server or a server cluster formed by a plurality of servers.

In this embodiment, an adaptive parasitic capacitance lookup table generation method is provided, and fig. 2 is a flowchart of the adaptive parasitic capacitance lookup table generation method of this embodiment, as shown in fig. 2, the flowchart includes the following steps:

step S202, a circuit template is obtained, first sampling points are determined according to the circuit template and a preset capacitance component threshold, and a first capacitance variation between two adjacent first sampling points is determined according to a first capacitance component corresponding to each first sampling point.

The circuit template can be obtained by acquiring different elements input by a user and the connection relation among the elements; the preset capacitance component threshold value can be obtained according to a process file corresponding to the circuit template; the process file refers to an instruction file describing the dimensions of a specific process level, each layer represents a mask design, and generally includes characteristic dimensions of each process level, especially minimum dimensions of elements and element connection relations, such as minimum width of a main conductor (min master width), minimum width of a slave conductor (min slave width), minimum distance of a master conductor and a slave conductor (min space btw master and slave) and other relevant information for pattern matching (pattern match); the first capacitance component can be extracted by solving Maxwell's equations or based on a field solver; the first capacitance variation is determined according to a first capacitance component of a first sampling point, and at least one first capacitance variation is determined.

Specifically, a circuit template and a process file are obtained, and a starting point t of a first sampling point is set according to the characteristic size of a master conductor and a slave conductor corresponding to the circuit template in the process file ¹ ₀ And solve for t ¹ ₀ Corresponding capacitance component C ¹ ₀ . Increasing the sample point, e.g. t, in equal steps ¹ ₁ ＝t ¹ ₀ +t ¹ ₀ ，t ¹ ₂ ＝t ¹ ₁ +t ¹ ₀ And calculating the capacitance component corresponding to each newly added sampling point. When the capacitance component corresponding to the newly added sampling point is smaller than the preset capacitance component threshold value C _min And stopping increasing the sampling points, and acquiring a first sampling point at the moment. The first sample point is a set of sequences T ₁ ＝{t ¹ ₀ ,t ¹ _1. t ¹ ₂ ,t ¹ ₃ ,…t ¹ _i …}，t ¹ _i >t ¹ _i-1 (ii) a According to the first capacitance component S corresponding to each first sampling point ¹ ₁ ＝{C ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., determining a first capacitance variation Δ S between two adjacent first sampling points ¹ ₁ ＝{ΔC ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … }, where Δ C ¹ _i ＝|C ¹ _i -C ¹ _i-1 |,i＝1,2,3.....。

Step S204, when the first capacitance variation is within a preset capacitance variation interval, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

In particular, if all of the first sampling points correspond toFirst capacitance variation { Delta C corresponding to two adjacent first capacitance components ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … is located in the predetermined capacitance variation interval { Δ C } _min ,ΔC _max And under the condition of the voltage, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

It will be appreciated that the predetermined capacitance component threshold value C _min The method can be obtained from the process file of the actual construction, and can also determine the range according to the actual engineering construction precision requirement, for example, the range can be 1 (+/-0.05) e-15F (farad, international standard unit of capacitance), and in the extraction of the first sampling point, when the capacitance component is less than 1 (+/-0.05) e-15F for the first time, the first sampling point is obtained according to all the extracted sampling points; the preset variation interval of capacitance component [ Delta C ] _min ,ΔC _max Can be determined according to the capacitance precision error between the mode matching algorithm and the target data specified by the user in the actual engineering, and can be set to [0,0.0001e-15F ] for example]Or [0.00005e-15F,0.0001e-15F]And the like.

The capacitance component and the parasitic capacitance in the application document have the same meaning, and extracting the parasitic capacitance of all target sampling points is equivalent to determining the capacitance component of each target sampling point.

It should be noted that, in the generation of the parasitic capacitance lookup table, multiple preset circuit templates may be performed, where the preset circuit templates may be obtained by obtaining different elements and connection relationships between the elements input by a user; the steps S202 to S204 may traverse all preset circuit templates to obtain size limit data in the process file, so as to execute the adaptive parasitic capacitance lookup table generation method, and generate a parasitic capacitance lookup table corresponding to the process file according to the size content recorded in the process file; after the target sampling point set and the corresponding parasitic capacitance lookup table are obtained in steps S202 to S204, the method may be used for each wafer factory to extract a scene of the parasitic capacitance from an actual layout file in an actual project according to a pattern matching (pattern match) rule, match a pattern (i.e., a connection relationship between an element and the like) obtained from the actual layout file with a circuit template recorded in the parasitic capacitance lookup table, and find a parasitic capacitance component corresponding to the circuit template matched with the pattern in the parasitic capacitance lookup table under different sizes according to the pattern and a pattern parameter (i.e., an element size) in the actual layout file, or perform interpolation operation on the parasitic capacitance component of the circuit template with a non-matching size, thereby finally obtaining a parasitic capacitance result extracted from the actual layout file in an actual process.

Through the steps, first sampling points of the circuit template are determined according to the process file and the preset capacitance component threshold, and first capacitance components { C corresponding to each first sampling point are extracted ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., and a first capacitance variation { Δ C ] corresponding to two adjacent first capacitance components ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … by determining a first capacitance variation { Δ C) corresponding to two adjacent first capacitance components ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … whether it is in the predetermined range of capacitance variation { Δ C } _min ,ΔC _max Within the range, the first capacitance variation is within a preset capacitance variation interval { Δ C _min ,ΔC _max Obtaining a target sampling point set and a parasitic capacitance lookup table by a corresponding first sampling point, and modifying a preset capacitance variation interval { delta C by comparing with a technical scheme that the target sampling point set is directly determined according to fixed sampling points in the related art so as to generate the parasitic capacitance lookup table according to the target sampling point set _min ,ΔC _max The size and the precision of a target sampling point set and a parasitic capacitance lookup table are adjusted in a self-adaptive mode, so that the problems of low efficiency, low precision and low process adaptation degree of extracting parasitic capacitance and generating the parasitic capacitance lookup table by using fixed sampling points are solved, the sampling point data and the size of the parasitic capacitance lookup table are adjusted in a self-adaptive mode according to different precisions, and therefore the parasitic capacitance is extracted efficiently and precisely.

In some embodiments, after determining a first capacitance variation between two adjacent first sampling points according to the first capacitance component corresponding to each first sampling point, the method further includes:

under the condition that the first capacitance variation is larger than the maximum capacitance variation of the capacitance variation interval, determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation to obtain a first initial sampling point, and determining a second capacitance variation between the two adjacent first initial sampling points according to a second capacitance component corresponding to the first initial sampling point; wherein the first initial sampling points comprise the first sampling point and the second sampling point;

and under the condition that the second capacitance variation is within a preset capacitance variation interval, generating the target sampling point set according to the first initial sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

The second sampling point is determined according to the first capacitance variation and the maximum capacitance variation, and at least one second sampling point is determined; the second sampling point is determined between two adjacent first sampling points.

Specifically, if the first capacitance variation { Δ C between two adjacent first capacitance components corresponding to the first sampling point is larger than the second sampling point ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … is larger than the predetermined capacitance variation interval { Δ C } _min ,ΔC _max Maximum capacitance variation amount Δ C of _max Then each larger than the maximum capacitance variation Δ C is obtained _max The first capacitance component of the first capacitor is correspondingly adjacent to two first sampling points, and a second sampling point between the two adjacent first sampling points is determined according to the two adjacent first sampling points; obtaining the first initial sampling points according to all the first sampling points and all the second sampling points; obtaining a corresponding capacitance component according to the first initial sampling point, thereby obtaining a second capacitance variation corresponding to the first initial sampling point; when the second capacitance variation is within a predetermined capacitance variation interval { Δ C _min ,ΔC _max Generating the set of target sampling points according to the first initial sampling point, and sampling according to the targetAnd generating a corresponding parasitic capacitance lookup table by the sampling point set.

Through the above steps, the maximum value max { Δ C of the capacitance change amount can be passed ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … and a predetermined range of capacitance variation { Δ C } _min ,ΔC _max Compared with the technical scheme that the parasitic capacitance lookup table is obtained by determining the sampling points according to the fixed sampling point step length in the related technology, the technical scheme that the new sampling points are determined according to the maximum capacitance variation can adapt to the processing technologies of wafer factories with different precision requirements, flexibly solves the problems of low efficiency, low precision and low process adaptation degree caused by the redundant workload of repeatedly generating the parasitic capacitance lookup table for each technology, and realizes the self-adaptive adjustment of the sampling point data and the size of the parasitic capacitance lookup table according to different precisions, thereby efficiently and highly accurately extracting the parasitic capacitance.

In some embodiments, determining the second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation includes:

and performing sampling calculation on the first sampling point according to the sampling step length and the process file to generate a second sampling point.

The bisection method for determining the sampling step length refers to determining the sampling step length by taking a middle step length between two adjacent first sampling points; the step length of the sampling is determined by the random step length method, namely a step length of the sampling is determined between two adjacent first sampling points by a random method; sampling and calculating the first sampling point according to the sampling step length and the process file to generate at least one second sampling point, wherein the connection distance can be adjusted according to the sampling step length and based on the size specified in the process file, for example, the adjusted connection distance cannot exceed the size specified in the process file, so that the sampling point is resampled according to the adjusted connection distance to generate at least one second sampling point; for example, taking the connection distance as the calculation basis of the sampling points, the sampling step is 2 micrometers, wherein one first sampling point is 5 micrometers, and the adjusted corresponding one second sampling point is 7 micrometers.

It should be noted that, in the step of determining the second sampling points between the first sampling points, only one new sampling point is determined between each pair of adjacent first sampling points, and when there are a plurality of pairs of adjacent first sampling points between which new sampling points need to be added, a plurality of new sampling points are available, and the second sampling points are obtained according to all the new sampling points.

Through the steps, the second sampling point is determined according to the process file, the sampling step length and the first sampling point, the capacitance variation between the adjacent first initial sampling points can be further reduced, and the requirement of a capacitance variation interval is met, so that the problems of low efficiency, low precision and low process adaptation degree of generating a parasitic capacitance lookup table by fixing the sampling points in the related technology are solved, the sampling point data and the size of the parasitic capacitance lookup table are self-adaptively adjusted according to different precisions, and the parasitic capacitance is extracted efficiently and precisely.

In some embodiments, after determining a second capacitance variation between two adjacent first initial sampling points according to the second capacitance component corresponding to the first initial sampling point, the method further includes:

under the condition that the first capacitance variation is larger than the maximum capacitance variation, determining a first current sampling point according to the second sampling point, and determining a first current capacitance variation between two adjacent first current sampling points according to the first current sampling point;

It will be appreciated that the first current sample point is all of the current sample points after the newly added sample point.

Recursively executing the step of adding the new sampling point through the stepsThe capacitance variation to all the adjacent two sampling points is less than the maximum capacitance variation delta C _max The target sampling point set and the parasitic capacitance lookup table can be obtained, whether the second capacitance variation is larger than the maximum capacitance variation exists in the second sampling points can be further judged after the second sampling points are extracted, all the sampling points meeting the process requirements can be obtained through recursive execution, the parasitic capacitance lookup table can be further obtained according to all the sampling points, the precision requirements of different processes of different wafer factories can be met, the problems of low efficiency, low precision and low process adaptation degree caused by redundant workload of repeatedly generating the parasitic capacitance lookup table aiming at each process are solved, the parasitic capacitance lookup table can be obtained by self-adaptively adjusting sampling point data according to different precisions, and the situation that the capacitance variation is larger than the maximum capacitance variation exists in newly-added sampling points is prevented.

under the condition that the two adjacent first capacitance variation values are smaller than the minimum capacitance variation value of the capacitance variation interval, removing a middle first sampling point of three first sampling points corresponding to the two first capacitance variation values to obtain a second initial sampling point;

It should be noted that, the method for determining according to the minimum capacitance variation of the capacitance variation interval in this embodiment may be combined with the method for determining according to the maximum capacitance variation of the capacitance variation interval in the above embodiment to form a progressive determination logic, for example, the method may first perform the determination with the minimum capacitance variation and then perform the determination with the maximum capacitance variation; or the maximum capacitance variation is judged first, and then the minimum capacitance variation is judged; preferably, the first capacitance variation and the minimum capacitance variation are judged to remove the redundant sampling point to obtain a third sampling point, then the third sampling point and the maximum capacitance variation are judged to newly add the sampling point, and the step of judging the newly added sampling point with the maximum capacitance variation is repeated until all the capacitance variations are located in the capacitance variation interval, because fewer sampling point sequences can be obtained in the step of removing the redundant sampling point, the resource and time occupied by the sampling point extraction are reduced, the calculation efficiency of the subsequent newly added sampling point is improved, and the efficiency of generating the parasitic capacitance lookup table is integrally improved, therefore, under the condition of the combined embodiment, the technical scheme of judging with the minimum capacitance variation firstly and judging with the maximum capacitance variation secondly is preferably adopted, and the description is omitted here.

Through the steps, the minimum value min { Delta C of the capacitance variation can be passed ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … and a predetermined range of capacitance variation { Δ C } _min ,ΔC _max Minimum capacitance variation amount Δ C in _min Whether redundant sampling points need to be removed or not is judged rapidly, compared with the technical scheme that the parasitic capacitance lookup table is obtained by determining the sampling points according to the fixed sampling point step length in the related technology, the technical scheme that the redundant sampling points are removed is determined according to the minimum capacitance variation, the redundant sampling points with the excessively small capacitance variation are removed in a self-adaptive mode, the processing technology of wafer factories with different precision requirements can be adapted, the sampling point sequence and the resource occupation are reduced, the calculation efficiency is improved, the problems of low efficiency, low precision and low process adaptability caused by the redundant workload of repeatedly generating the parasitic capacitance lookup table aiming at each technology are solved, the sampling point data are adjusted in a self-adaptive mode according to different precisions, and the parasitic capacitance lookup table is further obtained, so that the parasitic capacitance lookup table is generated efficiently and highly accurately.

In some of these embodiments, determining the first sampling point based on the circuit template and a predetermined capacitance component threshold comprises:

according to the circuit template, sampling in the fixed step length according to a process file and the characteristic size threshold value to determine at least one fixed sampling point of the circuit template, and extracting a fixed capacitance component corresponding to the fixed sampling point;

The feature size threshold may be obtained from a process file applied to actual process generation, or may be obtained by obtaining a feature size threshold input by a user.

Through the steps, the corresponding first sampling point can be extracted through the preset fixed step length and the circuit template, different fixed step lengths can obtain different first sampling point results, different circuit templates can also obtain different first sampling point results, the manufacturing requirements of the parasitic capacitance lookup table are flexibly met, the problems of low efficiency and low process adaptation degree caused by redundant workload of repeatedly generating the parasitic capacitance lookup table for each process are solved, the purpose of adjusting sampling point data according to the sampling point step length and further obtaining the parasitic capacitance lookup table is achieved, and the parasitic capacitance lookup table is efficiently generated.

It should be noted that, in some embodiments, after generating the corresponding parasitic capacitance lookup table according to the set of target sampling points, the method further includes:

extracting an actual layout file, and obtaining the parasitic capacitance of the actual layout file according to the parasitic capacitance lookup table under the condition that the actual layout file is matched with the parasitic capacitance lookup table;

and under the condition that the matching of the actual layout file and the parasitic capacitance lookup table fails, calculating the parasitic capacitance of the actual layout file according to the parasitic capacitance lookup table in an interpolation mode.

The actual layout file is used for a parasitic capacitance lookup table which is required to be generated through the steps in the parasitic capacitance lookup table generation method in the wafer factory process, and a parasitic capacitance file in the actual layout file is extracted according to mode matching; the circuit template of the actual layout file should be the same as the circuit template recorded in the parasitic capacitance lookup table, further, the connection relations of the minimum width (min master width) of the main conductors of the main and the auxiliary conductors connected with each other, the minimum width (min slave width) of the auxiliary conductors, the minimum distance (min space btw master and slave) of the main and the auxiliary conductors and the like in the actual layout file are consistent, and the characteristic size determines one of the characteristic sizes as a variable according to a control variable method.

Specifically, taking the minimum distance (min space btw master and slave) of the master conductor and the slave conductor as an example of variable quantity, there are three cases of failed matching between the actual layout file and the parasitic capacitance lookup table; firstly, the minimum distance x extracted from the actual layout file ₁ <t ₀ Wherein, t ₀ Representing the minimum sampling point with the minimum distance in the target sampling point set in the parasitic capacitance lookup table, wherein the capacitance component corresponding to the minimum sampling point is C ₁ (ii) a X is then ₁ The corresponding capacitance component calculation formula is:

C(x ₁ )＝ΔC _max /2+C ₁ equation 1

Secondly, the minimum distance x extracted from the actual layout file ₂ Satisfy t _i <x ₂ <t _i+1 A relation of, and t _i The capacitance component corresponding to the sampling point is C _i ，t _i The capacitance component corresponding to the sampling point is C _i Then x is ₂ The corresponding capacitance component calculation formula is:

C(x ₂ )＝C _i +(C _i+1 -C _i )/(t _i+1 -t _i )*x ₂ equation 2

Thirdly, extracting the minimum distance x from the actual layout file ₃ Satisfy x ₃ >t _max Wherein, t _max Representing the target sampling point in the parasitic capacitance look-up tableThe maximum sampling point with the maximum minimum distance in the set corresponds to the capacitance component C _tmax Then x ₃ The corresponding capacitance component calculation formula is:

C(x ₃ )＝C _tmax -ΔC _min equation 2 formula 3

Through the steps, in the step of generating the parasitic capacitance lookup table of the actual layout file according to the parasitic capacitance lookup table, under the condition that the matching between the actual layout file and the parasitic capacitance lookup table fails, interpolation operation can be performed according to the characteristic size extracted from the parasitic capacitance lookup table and the actual layout file, so that the most similar parasitic capacitance lookup table generation result aiming at the actual layout file is obtained, the generated high-precision parasitic capacitance lookup table is applied to the actual layout file, the scene of extracting the parasitic capacitance by adopting a mode matching mode is realized, the problems of low efficiency, low precision and low process adaptation degree in the method of extracting the parasitic capacitance according to the mode matching are solved, the sampling point data are adjusted according to different precisions in a self-adaptive mode, and the parasitic capacitance is extracted efficiently and highly.

Fig. 3 is a flowchart of another parasitic capacitance lookup table generation method according to the embodiment, and as shown in fig. 3, the flowchart includes the following steps:

in step S302, a process file (tech file) is acquired.

In step S304, it is determined whether all circuit templates have been traversed. Under the condition that all circuit templates are traversed, ending the parasitic capacitance lookup table generation method; in the case where all the circuit templates have not been traversed, step S306 is executed. The circuit template refers to a preset element and an element connection relation input by a user, the process file comprises all different feature sizes of the elements in the circuit template, and the circuit template is a matching object when pattern matching is carried out according to a parasitic capacitance lookup table.

Step S306, a first sampling point, a corresponding first capacitance component, and a first capacitance variation of the current circuit template are obtained according to the process file. The sampling point sequence of the first sampling point is T1, and the corresponding first electrodeThe capacitance component is S1, and the first capacitance variation is Δ S1. According to the characteristic size limit and the capacitance component threshold C of the master-slave conductor in the process file _min The starting point t is obtained from the minimum width (min master width) of the main conductor, the minimum width (min slave width) of the conductors, the minimum distance (minimum btw master and slave) of the main and slave conductors, and the like ₀ The starting point is taken as a fixed step. Increasing sampling point t for connecting distance space based on fixed step length _i (i =1,2,3, …); wherein, t _i Is t ₀ An integer multiple of. While increasing the sampling points, calculating the capacitance C of the corresponding sampling point _i . When C is present _i <C _min Then, the increase of the sampling point is stopped, thereby obtaining a first sampling point T ₁ ＝{t ¹ ₀ ,t ¹ _1. t ¹ ₂ ,t ¹ ₃ ,…}，t ¹ _i >t ¹ _i-1 And a first capacitance component S corresponding to the first sampling point ¹ ₁ ＝{C ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., and calculating a first capacitance variation Δ S corresponding to two adjacent first sampling points ¹ ₁ ＝{ΔC ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … }, where Δ C ¹ _i ＝|C ¹ _i -C ¹ _i-1 |,i＝1,2,3.....。

Step S308, determining whether the first capacitance variation is complete in traversal for the current circuit template. In the case where all the first capacitance variation amounts are traversed, step S316 is performed; in the case where all the first capacitance variation amounts have not been traversed, step S310 is performed.

In step S310, it is determined whether the two adjacent first capacitance variation amounts are both smaller than the minimum capacitance variation amount. Current three adjacent first sample point sequences t _i-1. t _i ，t _i+1 A corresponding first capacitance variation Δ C _i 、ΔC _i+1 If Δ C is _i <ΔC _min And is Δ C _i+1 <ΔC _min I =1,2,3 … …, perform step S312; otherwise, executing the stepS314。

In step S312, the middle first sampling point is removed. Will be Δ C _i ,ΔC _i+1 Corresponding three first sample point sequences t _i- _1. t _i ，t _i+1 The middle first sample point in _. t _i Is removed and step S314 is performed.

In step S314, two consecutive first capacitance variation amounts are continuously obtained. Reading in next group of first sampling point _. t _j-1 ,t _j ,t _j+1 }, corresponding first capacitance change amount Δ C _j J = i +2, and step S308 is performed;

and step S316, generating a third sampling point according to the traversal result. Obtaining a third sampling point sequence T according to the steps S308 to S314 ₃ And a third sequence of sampling points T ₃ Corresponding third capacitance component S ₃ And calculating a third capacitance variation Δ S between adjacent third sampling points ₃ Step S320 is performed.

In step S320, it is determined whether the third capacitance variation is complete. In the case that all the third capacitance variation amounts are traversed, step S326 is performed; in the case where all the capacitance variation amounts are not traversed, step S322 is performed.

In step S322, it is determined whether the third capacitance variation is greater than the maximum capacitance variation. Current third capacitance variation Δ C ³ _k (k =1,2,3 … …) if Δ C ³ _k >ΔC _max Step S324 is executed, otherwise step S325 is executed.

In step S324, new sampling points are added. At Δ C ³ _k Corresponding sampling point t ³ _k And t ³ _k-1 Between the two sampling points is added with a sampling point t ³ _εk ，t ³ _εk ＝(t ³ _k-1 +t ³ _k ) And/2, calculating a capacitance component C corresponding to the newly added sampling point ³ _εk And Δ C ³ _εk ＝|C ³ _εk -ΔC ³ _k -1|、ΔC ³ _k ＝|C ³ _εk -ΔC ³ _k And go to step S325. Wherein the new miningThe step length of the sampling point can be calculated by adopting a dichotomy.

In step S325, the next third capacitance variation is obtained. Reading in the next capacitance variation Δ C _t T = k +1, step S320 is executed;

in step S326, a set of target sampling points is determined. Obtaining first current sampling points according to the steps S320 to S325, and repeatedly executing the steps S320 to S325 until first current capacitance variation values corresponding to all the first current sampling points are located in a capacitance variation value interval, obtaining a target sampling point set according to all the first current sampling points, and further obtaining a parasitic capacitance lookup table according to the target sampling point set; step S304 is performed to traverse the next circuit template.

In this embodiment, a further adaptive parasitic capacitance lookup table generation method is provided, and fig. 4 is a flowchart of the adaptive parasitic capacitance lookup table generation method of this embodiment, as shown in fig. 4, the flowchart includes the following steps:

step S402, obtaining a circuit template, determining at least one first sampling point according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point.

Specifically, a circuit template and a process file are obtained, and according to the characteristic size of a master conductor and a slave conductor corresponding to the circuit template in the process file and a preset capacitance component threshold value C _min Determining a first sample point, the first sample point being a set of sequences T ₁ ＝{t ¹ ₀ ,t ¹ _1. t ¹ ₂ ,t ¹ ₃ ,…t ¹ _i …}，t ¹ _i >t ¹ _i -1; according to the first capacitance component S corresponding to each first sampling point ¹ ₁ ＝{C ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., determining a first capacitance variation Δ S between two adjacent first sampling points ¹ ₁ ＝{ΔC ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … }, where Δ C ¹ _i ＝|C ¹ _i -C ¹ _i -1|,i＝1,2,3.....。

In step S404, a maximum first capacitance variation is obtained according to the first capacitance variation. Specifically, the maximum first capacitance variation is extracted from the first capacitance variations, and corresponding two adjacent first sampling points and respective first capacitance components are recorded.

Step S406, under the condition that the maximum first capacitance variation is within the preset capacitance variation interval, generating a set of target sampling points according to the first sampling point, and extracting parasitic capacitances of all target sampling points in the set of target sampling points.

It should be noted that when the maximum first capacitance variation is located in the capacitance variation interval, the capacitance variations of all corresponding sampling points certainly satisfy the capacitance variation interval, so that a target sampling point set can be obtained according to all the first sampling points, and a parasitic capacitance lookup table is further obtained.

Through the steps, a first sampling point sequence is determined according to the process file and a preset capacitance component threshold value, and each first sampling point pair is extractedFirst capacitance component of interest { C ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., and a first capacitance variation { Δ C ] corresponding to two adjacent first capacitance components ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ …, the maximum first capacitance variation max { Δ C } corresponding to two adjacent first capacitance components is determined ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ … whether it is in the predetermined range of capacitance variation { Δ C } _min ,ΔC _max Within the range, under the condition of meeting a capacitance variation interval, obtaining a target sampling point set and a parasitic capacitance lookup table according to a first sampling point corresponding to each first capacitance variation, and comparing with the technical scheme that the target sampling point set is directly determined according to fixed sampling points in the related art, so that the parasitic capacitance lookup table is generated according to the target sampling point set, when the maximum first capacitance variation is located in the capacitance variation interval, the capacitance variations of all corresponding sampling points certainly meet the capacitance variation interval, and therefore the preset capacitance variation interval { delta C can be modified _min ,ΔC _max The method solves the problems of low efficiency, low precision and low process adaptation degree of extracting the parasitic capacitance to generate the parasitic capacitance lookup table by using fixed sampling points, and realizes the self-adaptive adjustment of the sampling point data and the parasitic capacitance lookup table according to different precisions.

In some embodiments, after obtaining the maximum first capacitance variation according to the first capacitance variation, the method further includes:

It is to be understood that the second current sampling point is determined according to the maximum first capacitance variation; when the maximum first capacitance variation is greater than the maximum capacitance variation in the capacitance variation interval, the second current sampling point may be all current sampling points after a new sampling point is added between adjacent first sampling points corresponding to the maximum first capacitance variation; before the relationship that the maximum first capacitance variation is larger than the maximum capacitance variation is judged, the minimum first capacitance variation corresponding to the first sampling point is obtained, and the middle first sampling point in the three corresponding sampling points is removed according to the two adjacent minimum first capacitance variations smaller than the minimum capacitance variation to obtain a third current sampling point, so that the sampling point sequence can be reduced, the resources are saved, the extraction time is shortened, and the extraction efficiency is improved; alternatively, the second current sampling point may be obtained after the relationship that the maximum first capacitance variation is larger than the maximum capacitance variation is determined, and the third current sampling point may be obtained according to the second current sampling point, so that the target sampling point is obtained according to the third current sampling point, which is not described herein again.

Through the steps, the step of adding the sampling points is executed recursively until the maximum first capacitance variation is in the preset capacitance variation interval { delta C _min ,ΔC _max And obtaining a target sampling point set and a parasitic capacitance lookup table, recursively executing to obtain sampling points and a parasitic capacitance lookup table meeting process requirements, meeting precision requirements of different processes of different wafer factories, solving the problems of low efficiency, low precision and low process adaptation caused by redundant workload for repeatedly generating the parasitic capacitance lookup table for each process, and realizing self-adaptive adjustment of the size of the sampling point data and the parasitic capacitance lookup table according to different precisions, thereby efficiently and highly extracting the parasitic capacitance.

Fig. 5 is a flowchart of a method for generating a parasitic capacitance lookup table according to another embodiment, and as shown in fig. 5, the flowchart includes the following steps:

in step S502, a process file (tech file) is acquired.

In step S504, it is determined whether all circuit templates have been traversed. Under the condition that all circuit templates are traversed, ending the parasitic capacitance lookup table generation method; in the case where all the circuit templates have not been traversed, step S506 is performed. The circuit template refers to a preset element and an element connection relation input by a user, the process file comprises all different feature sizes of the elements in the circuit template, and the circuit template is a matching object when pattern matching is carried out according to a parasitic capacitance lookup table.

Step S506, a first sampling point, a corresponding first capacitance component, and a first capacitance variation of the current circuit template are obtained according to the process file. The sampling point sequence of the first sampling point is T1, the corresponding first capacitance component is S1, and the first capacitance variation is Δ S1. According to the characteristic size limit and the capacitance component threshold C of the master-slave conductor in the process file _min The starting point t is obtained from the minimum width (min master width) of the main conductor, the minimum width (min slave width) of the conductors, the minimum distance (min space btw master and slave) of the main and slave conductors, and the like ₀ The starting point is taken as a fixed step size. Increasing sampling point t for connecting distance space based on fixed step length _i (i =1,2,3, …); wherein, t _i Is t ₀ An integer multiple of. While increasing the sampling points, calculating the capacitance C of the corresponding sampling point _i . When C is present _i <C _min Then, the increase of the sampling point is stopped, thereby obtaining a first sampling point T ₁ ＝{t ¹ ₀ ,t ¹ _1. t ¹ ₂ ,t ¹ ₃ ,…}，t ¹ _i >t ¹ _i-1 And a first capacitance component S corresponding to the first sampling point ¹ ₁ ＝{C ¹ ₀ ,C ¹ ₁ ,C ¹ ₂ ,C ¹ ₃ ,., and calculating first sampling points corresponding to two adjacent first sampling pointsCapacitance variation amount Δ S ¹ ₁ ＝{ΔC ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ …, where Δ C ¹ _i ＝|C ¹ _i -C ¹ _i-1 |,i＝1,2,3.....。

In step S508, the maximum first capacitance variation is extracted. Change from the first capacitance by Δ S ¹ ₁ ＝{ΔC ¹ ₁ ,ΔC ¹ ₂ ,ΔC ¹ ₃ …, and extracting a corresponding first sampling point. Alternatively, in this step, the added capacitance variation is calculated according to the added sampling points in step S512, and the maximum first capacitance variation is extracted according to the added capacitance variation and all the first capacitance variations.

In step S510, it is determined whether the maximum first capacitance variation is greater than the maximum capacitance variation. When the maximum first capacitance variation is greater than the maximum capacitance variation in the capacitance variation interval, it indicates that the first capacitance component and the first capacitance variation corresponding to the first sampling point sequence do not meet the precision requirement, and step S512 is executed; if the maximum first capacitance variation is smaller than the maximum capacitance variation in the capacitance variation interval, it is described that the upper limit of the first capacitance variation corresponding to the first sampling point sequence satisfies the accuracy requirement, and step S513 is executed.

In step S512, new sampling points are added. A new sampling point is added between two adjacent first sampling points corresponding to the maximum first capacitance variation, and step S508 is executed. Wherein, the step length of the sampling point of the newly added sampling point can be calculated by adopting a dichotomy.

In step S513, a second current sample point is obtained. And according to the step S508 to the step S512, extracting all the calculated sampling points to obtain a second current sampling point.

In step S514, the minimum second current capacitance variation corresponding to the second current sampling point is extracted.

In step S516, it is determined whether the minimum second current capacitance variation is smaller than the minimum capacitance variation. When the minimum second current capacitance variation is smaller than the minimum capacitance variation in the capacitance variation interval, it indicates that the second current capacitance component and the second current capacitance variation corresponding to the second current sampling point sequence do not meet the accuracy requirement, and step S518 is executed; when the minimum second current capacitance variation is greater than the minimum capacitance variation in the capacitance variation interval, it indicates that the lower limit of the second current capacitance variation corresponding to the second current sampling point sequence meets the accuracy requirement, and step S520 is executed.

Step S518, the middle second current sampling point corresponding to the minimum second current capacitance variation is removed.

Step S520, determining a set of target sampling points. Obtaining a target sampling point set and a parasitic capacitance lookup table according to the steps; step S504 is executed to traverse the next circuit template.

It should be understood that although the various steps in the flow charts of fig. 2-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternatingly with other steps or at least some of the sub-steps or stages of other steps. For example, in fig. 5, steps S514 to S518 may be exchanged with steps S508 to S512, and the minimum first capacitance variation is determined to obtain the second current sampling point, and then the maximum second current capacitance variation is determined, so as to obtain the target sampling point set and the parasitic capacitance lookup table.

FIG. 6 is a schematic diagram of a circuit template according to the embodiment, as shown in FIG. 6, which is a graph pattern abstracted from an actual layout file or a graph pattern abstracted from a tool of the company for extracting parasitic capacitance by EDA software companyThere is provided an adaptive parasitic capacitance lookup table generating step of generating target sampling points for the circuit template corresponding to the first aspect, and generating corresponding parasitic capacitance lookup tables according to the set of target sampling points. The circuit template is a master conductor master and a slave conductor slave, and the connection distance between the two conductors is space (corresponding to the minimum distance in the above embodiment). According to the limitation on the connection relation of the elements in the process file, obtaining an initial sampling point: the master conductor width (master width) is 0.5 microns, the slave conductor width (slave width) is 0.5 microns, and the master-slave conductor spacing space is 0.5 microns. The present embodiment relates to the following thresholds: capacitance component threshold C _min (= 0.0001) e-15F (farad, international standard unit of capacitance), capacitance variation interval { Δ C) _min ，ΔC _max }：ΔC _max ＝0.05(±0.0001)e-15F,ΔC _min e-15F of =0.007 (+/-0.0001), and the minimum spacing S with the connection distance of space is specified in the process file _min =500 nanometers =0.5 micrometers (um); wherein the minimum spacing will be used as a fixed sampling point step size to sample a fixed sampling point.

The first step is as follows: according to the minimum spacing S _min The process of sampling the fixed sampling point and obtaining the first sampling point is as follows:

master width＝{0.5}

slave width＝{0.5}

space_btw_master_and_slave＝{0.5 1.0 1.5 2.0 2.5 3.0}

the fixed sampling points and the fixed capacitance components and the fixed capacitance variation of the fixed sampling points are shown in table 1:

TABLE 1 fixed sampling points, fixed capacitance components and fixed capacitance variation for fixed sampling points

index	space	Capacitance component (e-15F)	Capacitance variation (e-15F)
				0	0.5	0.174148	—
1	1	0.110977	0.063171
				2	1.5	0.089655	0.021322
3	2	0.078677	0.010978
				4	2.5	0.071906	0.006771
5	3	0.067272	0.004634

Wherein index is the serial number of the capacitance component in the capacitance components, the firstA capacitance component value C with the capacitance component serial number of 0 and the corresponding space of 0.5 micron ₀ ，C ₀ =0.174148e-15F; the second capacitance component has a serial number of 1 and corresponds to a capacitance component value C with space of 1 micron ₁ ，C ₁ =0.110977e-15F and capacitance change amount ac of first capacitance component and second capacitance component ₁ ,ΔC _1＝ 0.063171e-15F; the third capacitance component has a serial number of 2 and corresponds to a capacitance component value C with space of 1.5 microns ₂ ，C ₂ =0.0.089655e-15F and capacitance change amount Δ C of the second capacitance component and the third capacitance component ₂ ,ΔC _2＝ 0.021322e-15F; the fourth capacitance component with the serial number of 3 corresponds to the capacitance component value C with the space of 2.0 microns ₃ ，C ₃ =0.078677e-15F and capacitance variation Δ C of third and fourth capacitance components ₃ ,ΔC _3＝ 0.010978e-15F; the fifth capacitance component has a serial number of 4, corresponding to a capacitance component value C with space of 2.5 microns ₄ ，C ₄ =0.071906e-15F and capacitance change amount Δ C of fourth capacitance component and fifth capacitance component ₄ ,ΔC ₄ =0.006771e-15F; the sixth capacitance component has a serial number of 5 and corresponds to a capacitance component value C with space of 3.0 microns ₅ ，C ₅ =0.067272e-15F and capacitance change amount Δ C of fifth capacitance component and sixth capacitance component ₅ ,ΔC ₅ ＝0.004634e-15F。

In the above fixed sampling points, when space =3.0um, the corresponding capacitance component is 0.067272-straw-woven cmin without continuously adding new sampling points, so that the first sampling point is obtained according to the fixed sampling points in table 1.

The second step is that: and under the condition that the two adjacent first capacitance variation values are smaller than the minimum capacitance variation value of the capacitance variation interval, removing a middle first sampling point of three first sampling points corresponding to the two first capacitance variation values to obtain a third sampling point. In table 1, there are two adjacent capacitance variations Δ C ₄ 、ΔC ₅ Satisfies the following conditions: delta C ₄ ＝0.006771e-15F<ΔC _min =0.007 (± 0.0001) e-15F and Δ C ₅ ＝0.004634e-15F<ΔC _min ＝0.007(±0.0001e-15F, the corresponding space = { 2.0.2.5.3.0 }, so the sample point corresponding to space =2.5 microns needs to be deleted in this embodiment. At this time, all the capacitance change amounts Δ C ₁ ,ΔC ₂ ,ΔC ₃ ,ΔC ₄ Satisfies a capacitance variable threshold value deltaC _min As shown in table 2:

TABLE 2 third sample point, third capacitance component and third capacitance variation of the third sample point

index	space	Capacitance component (e-15F)	Capacitance variation (e-15F)
				0	0.5	0.174148	—
1	1	0.110977	0.063171
				2	1.5	0.089655	0.021322
3	2	0.078677	0.010978
				4	3	0.067272	0.011405

The third step: and under the condition that the first capacitance variation is larger than the maximum capacitance variation of the capacitance variation interval, determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation. In Table 2 above, due to Δ C _1＝ 0.063171e-15F>ΔC _max =0.05 (± 0.001) e-15F, therefore, in this embodiment, a new sampling point needs to be inserted between space 0.5 micron and 1 micron, the space = (0.5 + 1)/2 =0.75 micron corresponding to the new sampling point, and the corresponding capacitance component is 0.131957e-15F, and the corresponding results are shown in table 3:

TABLE 3 second sample point, second capacitance component and second capacitance variation of the second sample point

index	space	Capacitance component (e-15F)	Capacitance variation (e-15F)
				0	0.5	0.174148	—
1	0.75	0.131957	0.042191
				2	1	0.110977	0.02098
3	1.5	0.089655	0.021322
				4	2	0.078677	0.010978
5	3	0.067272	0.011405

At this time, all the capacitance change amounts Δ C ₁ ,ΔC ₂ ,ΔC ₃ ,ΔC ₄ ,ΔC ₅ All satisfy the requirement of capacitance variation interval (delta C) _min ,ΔC _max }: Δ Cmax =0.05 (± 0.0001) e-15F, Δ Cmin =0.007 (± 0.0001) e-15F, and the sampling point extraction is terminated, so that the sampling points of space _ btw _ master _ and _ slave = { 0.5.75.1.0.5.2.0.3.0 } shown in table 3 are the target sampling point set, and the table 3 corresponding to the capacitance components and the capacitance variation amounts of the target sampling point set is the finally obtained parasitic capacitance lookup table.

It should be noted that, after the parasitic capacitance lookup table meeting the precision requirement is obtained, in the practical application of a wafer factory, under the condition that the accurate corresponding sampling point cannot be found, the parasitic capacitance lookup table can be generated by a linear interpolation method according to the capacitance lookup table. For example, in order to obtain the parasitic capacitance when the connection distance space of the circuit template is 1.8 micrometers, the parasitic capacitance of 1.8 micrometers can be obtained by linear interpolation of the parasitic capacitances of 1.5 micrometers and 2 micrometers, namely 0.089655+ (0.078677-0.089655) ((1.8-1.5)/(2-1.5) =0.0830682 e-15F).

In this embodiment, a device for generating a self-adaptive parasitic capacitance lookup table is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and details of which have been already described are omitted. The terms "module," "unit," "subunit," and the like as used below may implement a combination of software and/or hardware for a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 7 is a block diagram of a structure of an adaptive parasitic capacitance lookup table generation apparatus according to the present embodiment, as shown in fig. 7, the apparatus includes: an acquisition module 10 and an extraction module 30;

the obtaining module 10 is configured to obtain a circuit template, determine first sampling points according to the circuit template and a preset capacitance component threshold, and determine a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point;

the extracting module 30 is configured to generate a target sampling point set according to the first sampling point and generate a corresponding parasitic capacitance lookup table according to the target sampling point set when the first capacitance variation is within a preset capacitance variation interval.

For specific limitations of the adaptive parasitic capacitance lookup table generation apparatus, reference may be made to the above limitations of the adaptive parasitic capacitance lookup table generation method, and details are not repeated here. The modules in the adaptive parasitic capacitance lookup table generation apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In this embodiment, an adaptive parasitic capacitance lookup table generation system is further provided, and includes: a terminal device 102, a transmission device, and a server device 104; wherein the terminal device 102 is connected to the server device 104 through the transmission device;

the server device 104 is configured to implement the steps in any of the above method embodiments;

the transmission device is used for transmitting the circuit template to the server device;

the terminal device 102 is used to load the circuit template.

There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, a circuit template is obtained, first sampling points are determined according to the circuit template and a preset capacitance component threshold, and first capacitance variation between two adjacent first sampling points is determined according to a first capacitance component corresponding to each first sampling point.

And S2, under the condition that the first capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.

In addition, in combination with the adaptive parasitic capacitance lookup table generation method provided in the foregoing embodiment, a storage medium may also be provided in this embodiment. The storage medium having stored thereon a computer program; the computer program, when executed by a processor, implements any of the adaptive parasitic capacitance lookup table generation methods of the above embodiments.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as shown in fig. 8. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing the extracted sampling point data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an adaptive parasitic capacitance look-up table generation method.

Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without any inventive step, shall fall within the scope of protection of the present application.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. An adaptive parasitic capacitance lookup table generation method, comprising:

the method comprises the steps of obtaining a circuit template, determining first sampling points according to the circuit template and a preset capacitance component threshold, and determining a first capacitance variation between two adjacent first sampling points according to a first capacitance component corresponding to each first sampling point;

and under the condition that the first capacitance variation is in a preset capacitance variation interval, generating a target sampling point set according to the first sampling point, and generating a corresponding parasitic capacitance lookup table according to the target sampling point set.

2. The method of generating an adaptive parasitic capacitance lookup table according to claim 1, further comprising, after determining a first capacitance variation between two adjacent first sampling points according to the first capacitance component corresponding to each of the first sampling points:

when the first capacitance variation is larger than the maximum capacitance variation of the capacitance variation interval, determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation to obtain a first initial sampling point, and determining a second capacitance variation between the two adjacent first initial sampling points according to a second capacitance component corresponding to the first initial sampling point; wherein the first initial sampling points comprise the first sampling points and the second sampling points;

3. The method as claimed in claim 2, wherein the determining a second sampling point according to two adjacent first sampling points corresponding to the first capacitance variation comprises:

4. The method of claim 2, further comprising, after determining a second capacitance variation between two adjacent first initial sampling points according to the second capacitance component corresponding to the first initial sampling point, the step of:

under the condition that the second capacitance variation is larger than the maximum capacitance variation, determining a first current sampling point according to the second sampling point, and determining a first current capacitance variation between two adjacent first current sampling points according to the first current sampling point;

5. The method of generating an adaptive parasitic capacitance lookup table according to claim 1, further comprising, after determining a first capacitance variation between two adjacent first sampling points according to the first capacitance component corresponding to each of the first sampling points:

6. The adaptive parasitic capacitance lookup table generation method of any one of claims 1-5 wherein determining a first sample point based on the circuit template and a predetermined capacitance component threshold comprises:

7. An adaptive parasitic capacitance lookup table generation method, comprising:

8. The method of claim 7, further comprising, after obtaining a maximum first capacitance change amount according to the first capacitance change amount:

9. An adaptive parasitic capacitance lookup table generation apparatus, comprising: the device comprises an acquisition module and an extraction module;

10. An adaptive parasitic capacitance lookup table generation system, comprising: a terminal device, a transmission device and a server device; the terminal equipment is connected with the server equipment through the transmission equipment;

the server device is configured to perform the adaptive parasitic capacitance lookup table generation method of any one of claims 1 to 6;

and the terminal equipment is used for loading the circuit template.