CN103066015A - Manufacture method of metal interlamination capacitor - Google Patents
Manufacture method of metal interlamination capacitor Download PDFInfo
- Publication number
- CN103066015A CN103066015A CN2012105456011A CN201210545601A CN103066015A CN 103066015 A CN103066015 A CN 103066015A CN 2012105456011 A CN2012105456011 A CN 2012105456011A CN 201210545601 A CN201210545601 A CN 201210545601A CN 103066015 A CN103066015 A CN 103066015A
- Authority
- CN
- China
- Prior art keywords
- copper
- electric capacity
- manufacture method
- dielectric constant
- capacitive region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a manufacture method of a metal interlamination capacitor which comprises a deposition interlamination dielectric layer. The method comprises the steps of adopting the copper interconnection process to form a capacitor area, comprising mutually-parallel copper interconnection lines and interlamination media, in the deposition interlamination dielectric layer; etching the interlamination media between the copper interconnection lines in the capacitor area; depositing a layer of high dielectric constant media; and filling metal copper between the high dielectric constant media. According to the method, the high dielectric constant media are used as a metal interlamination film, and therefore a capacity area larger than that of a metal injection molding (MIM) capacitor is provided, a multi-layer structure is realized, capacitance density larger than that of a common mass optical memory (MOM) capacitor is provided, and therefore higher capacitance on the same area is realized.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, particularly a kind of manufacture method of metal interlevel electric capacity.
Background technology
Along with the progress of manufacturing process, integrated circuit has generally adopted copper wiring technique.In digital-to-analogue mixing/radio-frequency (RF) CMOS integrated circuit; the electric capacity device that is absolutely necessary; at present in the copper wiring technique; mainly adopted metal-insulator-metal type (Metal-Insulator-Metal; MIM) and these two kinds of capacitance structures of metal-oxide-metal (Metal-Oxide-Metal, MOM).
Wherein MIM electric capacity is a kind of capacity plate antenna, by double layer of metal respectively as upper/lower electrode, the centre is insulating medium layer, wherein metal be manufacture craft easily with metal interconnected the technique mutually copper, aluminium etc. of compatibility, dielectric then is the dielectric substance of the high-ks (k) such as silicon nitride, silica.Its main feature comprises: the processing steps such as the extra 2 step photoetching of needs; Its unit-area capacitance value is generally 1 ~ 2fF/um
2, the thickness of corresponding dielectric is about 30 ~ 60nm; Its electric capacity can only cloth one deck (generally between top-level metallic and inferior top-level metallic), and the capacitive region below can the cloth metal wire; Corresponding to the capacity plate antenna formula, Ctotal=C unit are (plane) * L*L(L is the capacitive region length of side).In actual applications, L can reach more than 100 microns.
MOM electric capacity is based on the parasitic capacitance between metal connecting line, and by the capacity plate antenna that consists of with layer parallel metal lines and intermediate medium on the vertical direction, intermediate medium is the metal interlevel film of standard technology, can be silicon dioxide or advanced low-k materials.Its main feature comprises: need not extra lithography step and make; Its unit are (on the vertical direction) electric capacity is very little, and 0.2 ~ 0.3fF/um only has an appointment
2MOM electric capacity can cloth in multilayer, but cannot connect up in the capacitive region below; Corresponding to the capacity plate antenna formula, Ctotal=C unit are (vertically) * L*H*L/ (2d) * N(L is the capacitive region length of side, and H is height of line, and d is the intermetallic distance, and N is the electric capacity number of plies).In integrated circuit technology, H approximates 2d, so Ctotal=C unit are (vertically) * L*L*N.Because the metal interlevel film of standard technology mostly is silicon dioxide or other low dielectric constant insulation media, so that the unit are of MOM electric capacity (vertically) capacitance is than MIM capacitance difference manyfold, usually only has 1/6 of MIM unit are (plane) capacitance, therefore, the MOM electric capacity that takies same area needs 6 layers of metal just can reach the capacitance same with MIM.
Summary of the invention
Main purpose of the present invention is to overcome the defective of prior art, for reaching above-mentioned purpose, the invention provides a kind of manufacture method of high performance metal interlevel electric capacity, and step comprises:
The deposition interlayer dielectric layer;
Adopt copper wiring technique to form capacitive region in described interlayer dielectric layer, described capacitive region comprises the copper interconnecting line that is parallel to each other, and the inter-level dielectric between the described copper interconnecting line;
Inter-level dielectric in the described capacitive region of etching between copper interconnecting line;
Deposition one deck high dielectric constant;
Between described high dielectric constant, fill metallic copper.
Preferably, the etching step of removing the inter-level dielectric in the described capacitive region comprises: apply photoresist layer outside described capacitive region; Inter-level dielectric in the described capacitive region of etching; And remove described photoresist layer.
Preferably, after filling the step of metallic copper between the described high dielectric constant, remove unnecessary metallic copper and high dielectric constant by cmp.
Preferably, the copper interconnecting line spacing is 100nm to 250nm in the described capacitive region, and copper interconnecting line thickness is 200nm to 500nm.
Preferably, the inter-level dielectric thickness in the described capacitive region of etching is more than or equal to the thickness of described copper interconnecting line.
Preferably, described high dielectric constant is silicon nitride, and the described silicon nitride thickness of deposit is 30nm to 60nm.
Preferably, described inter-level dielectric is medium with low dielectric constant.
Preferably, described medium with low dielectric constant is that carbon mixes up silica or fluorine doped silicon oxide.
Preferably, the step of filling metallic copper comprises deposit and spread barrier layer, copper seed layer and electro-coppering.
The invention has the advantages that, adopt high dielectric constant as the metal interlevel film of metal interlevel capacitance structure, not only provide than the large capacity area of MIM electric capacity and realized sandwich construction, and provide than the high capacitance density of common MOM electric capacity, thereby realized capacitance higher on equal area.
Description of drawings
Fig. 1 ~ Figure 3 shows that each step structural profile schematic diagram of metal interlevel method for producing capacitor of the present invention.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
The below is with reference to the preferred embodiment of Fig. 1 ~ 3 descriptions according to metal interlevel method for producing capacitor of the present invention.
Please refer to Fig. 1 left side schematic diagram, at first deposit interlayer dielectric layer, finish copper-connection to form capacitive region 3 by standard technology, copper wiring technique comprises that photoetching employing etching technics forms through hole at interlayer dielectric layer, deposit diffusion impervious layer and copper seed layer in through hole, plated metal copper grinds steps such as removing surperficial excess metal copper, it is well known to those skilled in the art, and therefore not to repeat here.As shown in Figure 1, capacitive region 3 comprises the inter-level dielectric 2 between parallel copper interconnecting line 1 and the copper interconnecting line, wherein copper interconnecting line 1 is parallel to each other, its spacing can be 100nm to 250nm, thickness can be 200nm to 500nm, inter-level dielectric 2 is medium with low dielectric constant, mixes up silica such as carbon, fluorine doped silicon oxide etc.Then, the inter-level dielectric 2 between the etching capacitive region 3 interior copper interconnecting lines 1.Better, in order to prevent from etching into other parts outside the capacitive region 3, the step of the inter-level dielectric 2 between the etching capacitive region 3 interior copper interconnecting lines 1 comprises: utilize mask plate to apply photoresist layer outside capacitive region 3, the zone beyond the capacitive region 3 is protected with photoresist; Pass through afterwards dry etching, will be without the inter-level dielectric etching between the copper interconnecting line 1 in the capacitive region 3 of photoresist masking, be depicted as copper interconnection structure profile behind the etching inter-level dielectric such as Fig. 1 right side view, the degree of depth of inter-level dielectric 2 etchings of low-k is more than or equal to the thickness of copper interconnecting line 1; And then the removal photoresist, thereby finish etching to inter-level dielectric 2.Then, deposit one deck high dielectric constant 4, high dielectric constant 4 for example are silicon nitride, and deposition process for example is plasma enhanced chemical vapor deposition, and deposition thickness for example is 30nm to 60nm.Afterwards, as shown in Figure 3, according to the Damascus technics flow process of routine, between this floor height dielectric constant dielectric 4, fill metallic copper 5 again.The concrete technology step comprises copper blocking layer, copper seed layer and electro-coppering, and these processing steps are well known to the skilled person, and therefore not to repeat here.Thus, realized the filling of metallic copper 51 of copper interconnecting line.Remove with grinding technics metallic copper 5 and high dielectric constant 4 that the surface is unnecessary at last.At this moment, comprise parallel metallic copper 5 in the capacitive region 3, the high dielectric constant 4 between parallel copper interconnecting line 1 and metallic copper 5 and the interconnection line 1, and metallic copper 5 and the slotting finger of copper interconnecting line 1 formation structure, thus formed metal interlevel electric capacity.That is to say that parallel metallic copper 5 and copper interconnecting line 1 be respectively as the upper/lower electrode of metal interlevel electric capacity, the 4 metal interlevel films as metal interlevel electric capacity of high dielectric constant in the middle of metallic copper 5 and the copper interconnecting line 1.Because metal interlevel electric capacity has adopted high dielectric constant 4 as the metal interlevel film, has significantly promoted unit are (vertically) capacitance.
By the invention described above preferred embodiment as can be known, the manufacture method of metal interlevel electric capacity of the present invention is compared with traditional MIM method for producing capacitor, reduced lithography step one, but on same area, can realize larger capacitance (about 50%), but and layout in multilayer interconnection.And compare with traditional MOM method for producing capacitor, although the present invention needs to increase a lithography step, the capacitance on equal area can be large 10 times, and can realize sandwich construction equally.Therefore, compare with existing copper interconnecting metal interlayer electric capacity, the formed metal interlevel electric capacity of the present invention can be realized larger capacitance in equal area, thereby can satisfy better the demand of product.
Although the present invention discloses as above with preferred embodiment; right described many embodiment only give an example for convenience of explanation; be not to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion so that claims are described.
Claims (9)
1. the manufacture method of a metal interlevel electric capacity is characterized in that, comprising:
The deposition interlayer dielectric layer;
Adopt copper wiring technique to form capacitive region in described interlayer dielectric layer, described capacitive region comprises the copper interconnecting line that is parallel to each other, and the inter-level dielectric between the described copper interconnecting line;
Inter-level dielectric in the described capacitive region of etching between copper interconnecting line;
Deposition one deck high dielectric constant;
Between described high dielectric constant, fill metallic copper.
2. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, the step that etching is removed the inter-level dielectric in the described capacitive region comprises:
Outside described capacitive region, apply photoresist layer;
Inter-level dielectric in the described capacitive region of etching; And
Remove described photoresist layer.
3. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, after filling the step of metallic copper between the described high dielectric constant, removes unnecessary metallic copper and high dielectric constant by cmp.
4. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, the copper interconnecting line spacing is 100nm to 250nm in the described capacitive region, and copper interconnecting line thickness is 200nm to 500nm.
5. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, the inter-level dielectric thickness in the described capacitive region of etching is more than or equal to the thickness of described copper interconnecting line.
6. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, described high dielectric constant is silicon nitride, and the described silicon nitride thickness of deposit is 30nm to 60nm.
7. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, described inter-level dielectric is medium with low dielectric constant.
8. the manufacture method of metal interlevel electric capacity according to claim 7 is characterized in that, described medium with low dielectric constant is that carbon mixes up silica or fluorine doped silicon oxide.
9. the manufacture method of metal interlevel electric capacity according to claim 1 is characterized in that, the step of filling metallic copper comprises deposit and spread barrier layer, copper seed layer and electro-coppering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105456011A CN103066015A (en) | 2012-12-14 | 2012-12-14 | Manufacture method of metal interlamination capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105456011A CN103066015A (en) | 2012-12-14 | 2012-12-14 | Manufacture method of metal interlamination capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103066015A true CN103066015A (en) | 2013-04-24 |
Family
ID=48108581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105456011A Pending CN103066015A (en) | 2012-12-14 | 2012-12-14 | Manufacture method of metal interlamination capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103066015A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117473933A (en) * | 2023-12-25 | 2024-01-30 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160559A1 (en) * | 2001-04-30 | 2002-10-31 | Lee Kee Jeung | Capacitor for semiconductor devices and a method of fabrication |
| US20080158771A1 (en) * | 2006-12-28 | 2008-07-03 | International Business Machines Corporation | Structure and method for self aligned vertical plate capacitor |
| CN102394217A (en) * | 2011-11-30 | 2012-03-28 | 上海华力微电子有限公司 | Manufacturing method of metal- silicon nitride-metal capacitor |
| CN102446981A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Multi-layer metal-silicon nitride-metal capacitor and manufacturing method thereof |
| CN102446709A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Method for manufacturing metal-silicon nitride-metal capacitor |
-
2012
- 2012-12-14 CN CN2012105456011A patent/CN103066015A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160559A1 (en) * | 2001-04-30 | 2002-10-31 | Lee Kee Jeung | Capacitor for semiconductor devices and a method of fabrication |
| US20080158771A1 (en) * | 2006-12-28 | 2008-07-03 | International Business Machines Corporation | Structure and method for self aligned vertical plate capacitor |
| CN102446981A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Multi-layer metal-silicon nitride-metal capacitor and manufacturing method thereof |
| CN102446709A (en) * | 2011-11-15 | 2012-05-09 | 上海华力微电子有限公司 | Method for manufacturing metal-silicon nitride-metal capacitor |
| CN102394217A (en) * | 2011-11-30 | 2012-03-28 | 上海华力微电子有限公司 | Manufacturing method of metal- silicon nitride-metal capacitor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117473933A (en) * | 2023-12-25 | 2024-01-30 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
| CN117473933B (en) * | 2023-12-25 | 2024-04-09 | 杭州行芯科技有限公司 | Capacitor bank creation method, capacitor acquisition method, electronic device and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI579998B (en) | Semiconductor device and method for manufacturing the same | |
| US7301218B2 (en) | Parallel capacitor of semiconductor device | |
| US9660016B2 (en) | Method of manufacturing a capacitor | |
| CN1751367B (en) | Capacitor and method of manufacturing a capacitor | |
| US6624040B1 (en) | Self-integrated vertical MIM capacitor in the dual damascene process | |
| US9524963B2 (en) | Semiconductor device | |
| US8105944B2 (en) | Method of designing semiconductor device and method of manufacturing the same | |
| CN101819922A (en) | Metal-insulator-metal capacitor and preparation method thereof | |
| KR100652298B1 (en) | Method for fabricating mim capacitor in a semiconductor device | |
| CN202905470U (en) | Multilayer silicon-based capacitor electrode connection structure | |
| JP2004214649A (en) | Method for forming mimcap (metal, insulator, metal capacitor) and resistor to same level | |
| US20230369199A1 (en) | Metal plate corner structure on metal insulator metal | |
| CN113809041B (en) | Metal-insulator-metal capacitor, integrated semiconductor device and method of manufacturing the same | |
| US20140017872A1 (en) | Method for fabricating a metal-insulator-metal capacitor | |
| CN104465608A (en) | Mim capacitor and manufacturing method thereof | |
| CN113594365B (en) | Semiconductor structure and forming method thereof | |
| CN102800568B (en) | Improve the method for MOM capacitor density | |
| CN102779782A (en) | Preparation process of dual damascene shallow dummy metal | |
| US20090057828A1 (en) | Metal-insulator-metal capacitor and method for manufacturing the same | |
| CN103066015A (en) | Manufacture method of metal interlamination capacitor | |
| CN102420101A (en) | Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process | |
| US7916449B2 (en) | Creation of capacitors equipped with means to reduce the stresses in the metal material of their lower structures | |
| US20140035099A1 (en) | Integrated circuits with metal-insulator-metal (mim) capacitors and methods for fabricating same | |
| CN108122894B (en) | Method for improving arc discharge defect of MIM capacitor | |
| CN1490869A (en) | Method for producing high-density capacitors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130424 |
|
| WD01 | Invention patent application deemed withdrawn after publication |