JP3196847B2 - Wiring structure and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional wiring forming process, a through hole is formed in a first interlayer insulating film, tungsten (W) is buried in the through hole, and TiN / T
A barrier metal film such as i, a wiring metal film such as aluminum (Al), and an antireflection film such as TiN are continuously formed. Further, using a photoresist pattern formed by exposure and development as a mask, wiring is formed by dry etching using a chlorine-based plasma gas. Further, a second interlayer insulating film is grown on the wiring by a CVD method, and the interlayer insulating film is formed by a chemical mechanical polishing method (C
MP: Chemical Mechanical Po
and flattening.

In this method, (1) the wiring metal film having high corrosivity must be dry-etched;
(2) Due to the necessity of growing an interlayer insulating film on a narrow pitch metal wiring, technical difficulty due to miniaturization of wiring is increasing.

[0004] In addition, due to the multi-layered fine wiring, disconnection frequently occurs at a vertical connection portion between a lower wiring / W plug / upper wiring. This is because metal atoms are easily moved by electron flow, that is, electromigration resistance (hereinafter, referred to as “electromigration resistance”).
Wiring metal (Al) and EM with relatively low EM resistance
This is because voids are generated on the wiring metal side at the connection interface of the plug embedded metal (W) having high resistance. In addition, the probability of failure due to misalignment of the connection portion composed of the lower layer wiring / W plug / upper layer wiring due to miniaturization of the wiring is increasing.

[0005] Further, the narrowing of the pitch tends to increase the wiring signal transmission delay due to an increase in the capacitance between wirings, and the wiring performance is a factor that governs the LSI performance. Therefore, there is an urgent need to lower the dielectric constant of the interlayer insulating film.

In order to solve these technical problems of the LSI wiring, a wiring forming method for embedding wiring metal in a wiring groove and a through hole from a bottom portion thereof to a lower layer wiring collectively without using dry etching of a wiring metal film. A method has been proposed. FIG. 5 shows Canta et al. (CW Kaant).
a, 1991 VMIC Conference, p.
144) shows a conventional example of forming a buried wiring in an interlayer insulating film proposed by (144).

First, an interlayer insulating film 62 made of a silicon oxide film is directly grown on a lower wiring 61, and a first step is performed in a series of steps including application of a first photoresist 63, exposure and development of a vertical connection hole pattern. A vertical connection hole pattern 64 is formed in the photoresist (FIG. 5A). Further, the second photoresist pattern 65 having the wiring groove pattern 66 is formed on the first photoresist 64 by a series of steps including the application of the second photoresist 65, the exposure and the development of the wiring groove pattern (see FIG. 1). FIG. 5 (b)). Thereafter, dry etching using a fluorine-based gas is performed using the first and second photoresist patterns as masks to form the interlayer insulating film 62.
A vertical connection hole 67 (through hole) is formed in the substrate. At this time,
By controlling the etching time, the etching is completed only when the bottom of the vertical connection hole 67 is located at the middle of the interlayer insulating film (FIG. 5).
(C)). Next, the etching gas is switched to O ₂ gas, and the wiring groove pattern 66 formed in the second photoresist is transferred to the first photoresist 63 (FIG. 5D). At the end of the etching, the second photoresist has been removed. The etching gas is switched again to the fluorine gas, and the wiring groove 68 is formed in the interlayer insulating film 62 using the first photoresist 63 to which the wiring groove pattern 66 has been transferred as a mask. At this time, by controlling the etching time, the bottom of the vertical connection hole 67 (through hole) formed in advance in the interlayer insulating film 62 reaches the lower wiring 61 (FIG. 5E). The first photoresist 63 on the interlayer insulating film 62 is removed by O ₂ plasma gas (FIG. 5).
(F)) A metal film 70 of aluminum or the like is grown while filling the wiring groove 68 and the vertical connection hole 67 formed in the interlayer insulating film 62 by the CVD method (FIG. 5G). Finally, the metal film on the interlayer insulating film is selectively removed by a chemical mechanical polishing method to obtain a wiring structure in which the metal is embedded in the wiring groove and the vertical connection hole (FIG. 5H).

In the case of this method, (1) a fine processing step of a metal film and a step of growing an interlayer insulating film on a fine wiring are not required; and (2) at least a metal buried in the wiring groove and the vertical connection hole is used. There are advantages such as the same and no connection interface. However, the depths of the vertical connection holes and the wiring grooves are controlled by changing the etching time. Also,
Since the interlayer insulating film is an inorganic material and the etching mask material is an organic material (photoresist), at least two types of etching gases (here, a fluorine-based plasma gas and an oxygen plasma gas) are switched and used.

On the other hand, for the purpose of suppressing the capacitance between wirings, Japanese Patent Application No. 2-235359 proposes a multilayer wiring forming process using an organic film. That is, as described above, a silicon oxide film formed by a plasma CVD method is generally used for an interlayer insulating film, but its relative dielectric constant (ε)
Is about 3.9 to 4.5. Fluorine (F) in oxide film
Can be reduced to about 3.1 by adding
Since it is difficult to reduce the dielectric constant of the interlayer insulating film made of an inorganic thin film material to 3.0 or less, polyimide (ε = 2.
An organic film represented by 5-3.5) is applied.

FIG. 6 shows a multilayer wiring forming process using polyimide and a silicon oxide film. First, an inorganic interlayer insulating film 7 made of a silicon oxide film is formed on the first aluminum wiring 72.
3 is grown, and a polyimide 74 is further formed by a spin coating method (FIG. 6A). Next, a first photoresist 75 is formed on the polyimide 74 to form a vertical connection hole pattern 76 (FIG. 6B). Thereafter, vertical connection holes 77 are formed in the polyimide 74 by dry etching using O ₂ as a reaction gas (FIG. 6C). At this time, the polyimide 74 is controlled by controlling the O ₂ plasma etching time.
The upper resist 75 is also ashed and removed at the same time. Here, O
_{2. Since the} plasma gas is used, the etching stops when the inorganic interlayer insulating film 73 under the polyimide 74 appears. Next, the etching gas is switched to CF ₄ to form a vertical connection hole 77 (through hole) in the inorganic interlayer insulating film 73 (FIG. 6D). Subsequently, an aluminum film is formed, and the second photoresist 78 having a wiring pattern is used as a mask,
The second aluminum wiring 79 is formed by dry etching with Cl ₂ gas (FIG. 6E). Finally, the second photoresist 78 is removed with an O ₂ plasma gas (FIG. 6).
(F)).

Although the above two conventional examples do not provide a detailed description of dry etching, there is a problem from the viewpoint of process stability in controlling the etching depth by controlling the etching time. Therefore, generally, the end point of the etching is detected by examining the intensity change of the emission spectrum in the dry etching gas. As the most common conventional example, a method of etching TiN with a chlorine-based gas using a photoresist mask is disclosed in Japanese Patent Application Laid-Open No. 3-12927. Here, a spectrum (410 nm to 420 n) corresponding to a reaction product gas of TiN to be etched and an etching gas is used.
m) The light emission intensity in the region is monitored, and a change in intensity at which the light emission decreases when the etching of the object to be etched is completed is detected.

In the conventional example disclosed in Japanese Patent Application Laid-Open No. 3-12927, a method of directly detecting light emission of a reaction product gas between an object to be etched and an etching gas is used, but the etching gas is not directly involved in the etching. There is also disclosed a method of detecting an etching end point by adding a gas and monitoring the emission intensity of the added gas by utilizing the interaction between the added gas and an etching reaction product gas.

That is, Japanese Patent Application Laid-Open No. 4-287919 discloses a conventional example in which an organic film such as a photoresist is patterned. Here, instead of using an oxygen plasma gas containing a nitrogen gas as an etching gas to detect the emission intensity of carbon monoxide, which is a reaction product gas between the organic film to be etched and oxygen, the presence of carbon monoxide The end point is detected by utilizing the phenomenon that the emission intensity of the nitrogen molecule decreases. As described above, there is a method in which a gas used for end point detection is added to the etching gas.

Japanese Patent Application Laid-Open No. 6-232090 discloses that, as in the case of forming a contact hole in an oxide film, the area to be etched is small, the amount of reaction gas generated between an etching gas and an object to be etched is small, A conventional example in which it is difficult to detect a decrease in the intensity of the emission spectrum is described.

FIG. 7 shows a conventional example in which a contact hole is formed in a silicon oxide film using a multilayer resist including two types of photoresists. First, the silicon substrate 8
1, a silicon oxide film 82 is formed, a lowermost resist (first resist) 83, an SOG layer (second resist)
A multi-layer resist composed of a resist 84 and an outermost layer resist (third resist) 85 is formed. At this time, the etching rate ratio between the silicon oxide film 82 and the outermost layer resist 85 is measured in advance, and the outermost layer resist 85 is etched away at the same time as the oxide film etching is completed, so that the SOG layer 84 appears. Adjust the thickness of 85. When an opening 86 is formed in such a multilayer resist (FIG. 7A) and dry etching is started using a plasma gas such as CF ₄ , a portion of the silicon oxide film 82 exposed in the opening 86 of the multilayer resist is formed. At the same time, the outermost layer resist 85 of the multilayer resist is also etched. At this time, since almost no oxygen is present in the reaction product gas released in accordance with the etching of the organic outermost layer resist 85, light emission (437n) caused by oxygen in the plasma gas is generated.
m) has a low emission intensity. When the silicon oxide film 82 under the multilayer resist opening 86 is entirely etched, the outermost surface resist 85 is also entirely etched at the same time (FIG. 7).
(B)). Then, the SOG layer 84 as the second resist
Etching starts. When the etching of the SOG layer 84 composed of oxygen atoms and silicon atoms is started,
The emission intensity due to oxygen in the plasma gas increases.
The time when the light emission intensity increases is defined as the end point of the etching.

That is, in this conventional example, two types of resists having different specific emission spectra are formed on the silicon oxide film 82 which is a material to be etched to form a pattern, and the specific emission spectra when these resists are etched. The pattern 87 is formed on the silicon oxide film 82 by detecting the end point of the etching using the difference between the two.

The method of forming an end point detection film on the silicon oxide film 82 is also used in an etch-back method for planarizing an insulating film surface.

The method described in Japanese Patent Application Laid-Open No. 2-310921 is a method of detecting the end point of the etch-back when the surface of the material to be etched is etched back by etching back the flatness sacrificial film. First, a silicon nitride film 92 as an end point detecting insulating film is grown on a field oxide film (material to be etched) 91 having an uneven surface (FIG. 8).
(A)). Next, an SOG film (silicon oxide film) 93, which is a sacrificial film having a flat surface, is formed on the insulating film 92 for detecting the end point (FIG. 8B). When such a substrate is placed in an RIE apparatus and etched back using CHF ₃ gas, the SOG film 93 serving as a sacrificial film and the CHF 3
CO and CO ₂ which are etching reaction product gases with ₃ are generated. Further, when the etching proceeds and the silicon nitride film 92 serving as the end point detecting insulating film appears, the amount of CO generated as a reaction product gas between the SOG film 93 and CHF ₃ decreases (FIG. 8C). Therefore, by monitoring the change in the intensity of the wavelength corresponding to the emission spectrum of CO through the spectroscope provided in the RIE apparatus, the insulating film 9 for detecting the end point can be obtained.
2 is detected, and the end point of the etch back is detected.

This method is also characterized in that an insulating film for detecting an end point is grown on a field oxide film to be planarized.

[0020]

However, each of the above conventional examples has the following problems.

First, according to the first conventional method, a metal film is formed at once on a wiring groove and a vertical connection hole, so that a dry etching step for forming a fine pattern of a wiring metal film and a fine wiring pattern are formed. This eliminates the need for an interlayer insulating film forming step. However, in the first conventional example, the vertical connection hole pattern made of the first photoresist and the wiring groove pattern made of the second photoresist are transferred to the interlayer insulating film by dry etching. Since the silicon oxide film is used, the number of switching of the etching gas is large, and the amount of etching is controlled by the etching time.

Here, first, the vertical connection hole pattern of the first photoresist is transferred to the interlayer insulating film using a Cl-based gas.
Next, the wiring groove pattern of the second photoresist is transferred to the first photoresist with an O ₂ plasma gas, and then switched to a Cl-based gas again, and the wiring groove pattern transferred to the first photoresist is used as a mask. The wiring groove pattern is transferred to the insulating film, and finally, the first photoresist pattern is removed again by O ₂ plasma gas. That is, Cl
Etching gas switching system → O ₂ system → Cl system → O ₂ system is required.

In this method, when forming the second photoresist on the first photoresist on which the vertical connection hole pattern is formed, the first photoresist must be baked at a high temperature for a long time. In some cases, the vertical connection hole pattern was deformed due to partial melting. Further, it is necessary to form a wiring groove pattern wider than the diameter of the vertical connection hole pattern in the second photoresist on the vertical connection hole pattern formed in the first photoresist. Therefore, when designing the wiring, it is necessary to design the pattern so that at least the width of the wiring groove on the vertical connection hole is widened. Was.

Further, generally, the lower wiring and the upper wiring located on the lower wiring have a lattice shape orthogonal to each other. For example, if the lower wirings are arranged at regular intervals in the north-south direction, the upper wirings are arranged at regular intervals in the east-west direction with the interlayer insulating film interposed therebetween. The upper wiring is three-dimensionally separated by an interlayer insulating film, but is provided so as to cross at least the lower wiring. In a normal process of forming a wiring metal film such as aluminum on the interlayer insulating film, forming a desired photoresist pattern on the wiring metal film in the exposure and development steps, and forming wiring by dry etching, the resist pattern formation by exposure is Since it is on the wiring metal film, reflection from the lower wiring can be ignored. In the case of normal wiring, an exposure process is performed after forming an antireflection film such as titanium nitride on a wiring metal film. On the other hand, in the first conventional example, since a wiring metal is formed after forming a wiring groove and a vertical connection hole (through hole) in an interlayer insulating film, the lower wiring is formed when a photoresist formed on the interlayer insulating film is exposed. The reflection from the light must be taken into account. However, the first conventional example does not consider the reflection from the lower wiring at the time of this exposure.

An object of the present invention is to use a local reflection from a through-hole plug at the time of exposure to increase the width of a wiring groove on the through-hole in a self-aligning manner, thereby increasing a connection margin between the through-hole and the wiring groove. An object of the present invention is to improve the reliability and productivity of a multilayer wiring by providing a wiring structure and a method of manufacturing the wiring structure, which ensure the reliability of vertical connection between the multilayer wirings.

[0026]

According to the present invention, there is provided a step of forming a first insulating film on an antireflection film of a base wiring, and forming a metal plug by embedding a metal in a hole formed in the first insulating film. Forming, forming a second insulating film, forming a photoresist, exposing the wiring groove resist pattern width locally from the exposed region using reflection from the metal plug surface, and forming the wiring groove resist. Forming a wiring groove in the second insulating film using the pattern as a mask, growing a metal film in the second insulating film while filling the wiring groove, and selectively removing the metal on the second insulating film. A first insulating film and a second insulating film are formed on the anti-reflection film of the underlying wiring,
The first metal is buried in the hole formed in the first insulating film to form a metal plug, and the wiring in which the second metal is buried is formed in the wiring groove of the second insulating film.
The wiring width is the same as the diameter of the metal plug in the region other than the metal plug formation region, and is approximately 20% wider than the metal plug diameter in the region passing over the metal plug. %, And at the same time, about 20% longer in the length direction.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, when a metal plug is buried in a first interlayer insulating film and then a wiring in which a second metal is buried in a wiring groove of a second interlayer insulating film is formed, a metal plug is formed. In the area passing above, the wiring width is 2
The wiring width and the wiring length are 20% longer on the metal plug located 0% wider and at the end of the wiring. The reliability of the multilayer wiring is improved by increasing the connection margin between the metal plug and the groove-buried wiring.

This is the case even if a metal plug is buried in the first interlayer insulating film and then a wiring in which the second metal is buried in the wiring groove of the second interlayer insulating film is formed. The width and length of the trench-embedded wiring on the metal plug are increased in a self-aligning manner by utilizing reflection from light. Therefore, when designing the wiring mask pattern, there is no need to take measures such as increasing the width of the wiring groove on the metal plug. Also, it is not necessary to increase the design pitch of the wiring.

An embodiment of the present invention is a method of forming a wiring groove and embedding a metal in the wiring groove after forming a metal plug in which a metal is embedded in a through hole. This is a method in which the width of the wiring groove on the metal plug is increased in a self-aligned manner by utilizing it. An embodiment of the present invention will be described in detail with reference to FIGS. First, the anti-reflection film 28 is formed on the underlying wiring layer 39, and metal plugs 41a and 41b in which the first metal is embedded in the first openings formed in the first interlayer insulating film 40 are formed. Further, a second interlayer insulating film 42 is grown on the first interlayer insulating film. Thereafter, a positive photoresist 23 is applied. FIG.
1A is a top view of the positive photoresist 23 after exposure and development, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. ) Is a cross-sectional view taken along line BB ′. Even when a wiring groove pattern having the same width as one side of the metal plug is exposed on the positive photoresist, the positive photoresist around the metal plug is locally exposed by the reflected light 43 from the metal plugs 41a and 41b. Then, the wiring width of the positive photoresist around the metal plug is locally increased. As shown in FIGS. 2A and 2B, the positive photoresist 23 and the second interlayer insulating film 42 are etched back at a constant speed to form wiring grooves 44 reaching the metal plugs 41a and 41b. I do. Next, as shown in FIGS. 3A and 3B, by embedding the second metal 45 in the wiring groove 44, the wiring width on the metal plug is increased in a self-aligned manner. Have been obtained. In addition, on the metal plug 41a located at the end of the wiring, it extends not only in the width direction of the wiring but also in the length direction in a self-aligned manner. Therefore, a multilayer wiring in which the wiring and the metal plug are securely connected is formed without locally increasing the wiring width and increasing the pitch when designing the wiring.

[0030]

EXAMPLES Hereinafter, the present invention will be described specifically with reference to examples, but the present invention is not limited to these examples.

Example 1 An example belonging to the embodiment of the present invention will be described in detail with reference to FIG.

First, as shown in FIG.
The tungsten plug 21 is formed on the BPSG film 19 on the ET, and the underlying substrate 47 in which aluminum is embedded in the plasma oxide film 46 is formed on the semiconductor substrate 14.
An antireflection film 28 made of a silicon nitride film having a thickness of 50 nm is formed. 500 nm to 100 nm as a first interlayer insulating film
After forming a 0-nm-thick plasma CVD silicon oxide film 40, a through-hole pattern 29 is formed in the positive photoresist 23 (FIG. 4B). Next, through holes 30 reaching the underlying wiring 47 are formed by dry etching using CHF ₃ gas using a positive photoresist as a mask. 10 nm Ti and 50 by collimated sputtering
After forming a TiN film having a thickness of 400 nm, a tungsten film having a thickness of 400 nm is formed by a W-CVD method. Furthermore, W using silica slurry
A W plug (metal plug) 41 is formed by selectively removing tungsten on the first interlayer insulating film 40 by -CMP (FIG. 4C).

Next, as shown in FIG. 4D, a silicon oxide film 42 is formed to a thickness of 600 nm as a second interlayer insulating film, and a 600 nm positive photoresist 23 having the same thickness as the silicon oxide film is applied. The wiring groove pattern is exposed. At this time, the wiring groove pattern formed in the photoresist by the reflection from the W plug 41 is locally widened. For example, when the width of the wiring groove formed in the photoresist in a region where there is no reflection from the W plug is 0.3 μm, the width of the wiring groove pattern on the 0.3 μm diameter W plug is 0.35 μm.

Next, as shown in FIG. 4E, a mixed gas of 90% CHF ₃ and 10% O ₂ is used in an ECR plasma chamber with an etching gas pressure of 2.5 mTorr and an RF power of 200 W. Then, the silicon oxide film 42 as the second interlayer insulating film and the photoresist 23 are etched back at a constant speed. At this time, the emission of Si-F in the plasma gas is monitored. Si-F is a reaction product of the silicon oxide film 42 and CHF _{3 in} the etching gas, and is not generated by the reaction between the etching gas and the photoresist. That is, since most of the surface of the silicon oxide film 42 is covered with the photoresist 23 in the initial stage of the etching, the emission intensity corresponding to Si-F is low. As the etching further proceeds, the photoresist is completely removed, the entire surface of the silicon oxide film appears, and the luminous intensity of Si-F sharply increases. The point at which the emission intensity of Si-F sharply increases is defined as the end of etching. As a result, a wiring groove reaching the first interlayer insulating film 40 is formed in the second interlayer insulating film 42. On the W plug 41, the width of the wiring groove is locally increased (FIG. 4E).

Finally, as shown in FIG. 4F, 10 nm of Ti is formed in the wiring groove 44 by a collimated sputtering method, and a 1 μm aluminum film is continuously formed by a high temperature sputtering method. By setting the substrate temperature to 380 ° C. to 480 ° C., aluminum could be embedded in the wiring groove 44 having a depth of 0.6 μm and a width of 0.3 μm. Further, the aluminum on the second interlayer insulating film 42 is selectively polished with a silica slurry to which hydrogen peroxide solution is added, so that the aluminum is embedded in the wiring groove formed in the silicon oxide film as the second interlayer insulating film. An interconnect 45 is formed. Since the width of the wiring 45 is locally widened on the W plug 41, a structure in which the wiring 45 is connected to the wiring 45 on the entire upper surface of the W plug is made possible.

Although a silicon oxide film is used here as the interlayer insulating film, it is obvious that an organic insulating film containing silicon may be used. Further, it is obvious that an organic insulating film containing an element not included in the photoresist may be used. Further, although the metal plug 41 is formed of tungsten, the type of metal is not limited, and may be aluminum, copper, silver or gold.

[0037]

The effect of the present invention is that when a metal plug is buried in a first interlayer insulating film and then a wiring in which a second metal is buried in a wiring groove of the second interlayer insulating film is formed.
The width and length of the trench-embedded wiring on the metal plug are increased in a self-aligning manner by utilizing reflection from the surface of the metal plug. Therefore, when designing the wiring mask pattern, there is no need to take measures such as increasing the width of the wiring groove on the metal plug. Further, it is no longer necessary to increase the design pitch of the wiring.
As a result, the reliability of the vertical connection of the multilayer wiring was able to be greatly improved.

[Brief description of the drawings]

1A and 1B are diagrams illustrating an embodiment of the present invention, wherein FIG. 1A is a plan view, and FIGS. 1B and 1C are AA ′ and B-, respectively.
It is sectional drawing in B '.

FIG. 2 is a view for explaining the next step of FIG. 1;
(B) is sectional drawing corresponding to (b) and (c) of FIG. 1, respectively.

FIG. 3 is a view for explaining the next step of FIG. 2;
(B) is sectional drawing corresponding to (b) and (c) of FIG. 1, respectively.

FIG. 4 is a sectional process view for explaining the embodiment of the present invention.

FIG. 5 is a process cross-sectional view for explaining a first conventional example.

FIG. 6 is a process sectional view for describing a second conventional example.

FIG. 7 is a process cross-sectional view for explaining a fifth conventional example.

FIG. 8 is a process sectional view for describing a sixth conventional example.

[Explanation of symbols]

 Reference Signs List 14 silicon semiconductor substrate 15 trench element isolation film 21 tungsten plug 23 positive photoresist 28 antireflection film 29 resist pattern of through hole 30 through hole 39 underlying wiring layer 40 first interlayer insulating film 41 metal plug 42 second interlayer insulation Film 43 reflected light 44 wiring groove 45 second metal 46 plasma oxide film 47 aluminum wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (2)

(57) [Claims] A step of forming a first insulating film on the anti-reflection film of the underlying wiring; a step of forming a metal plug by embedding a metal in a hole formed in the first insulating film; a second insulating film Forming a photoresist, forming a photoresist, exposing the wiring groove resist pattern width locally from the exposed region by using reflection from the metal plug surface, and using the wiring groove resist pattern as a mask to perform the second insulation. Forming a wiring groove in the film, growing a metal film in the second insulating film while filling the wiring groove, and selectively removing metal on the second insulating film. Method of forming wiring. 2. A first insulating film and a second insulating film are formed on an anti-reflection film of a base wiring, and a first metal is buried in a hole formed in the first insulating film to form a metal plug. A wiring in which a second metal is buried in the wiring groove of the second insulating film is formed, and a region which has the same wiring width as the metal plug diameter and passes over the metal plug in a region other than the metal plug formation region. Is larger than the diameter of the metal plug by 20% or less, and the width and the length of the wiring on the metal plug located at the end of the wiring are increased by 20% or less. Wiring structure.