KR100442852B1 - Method for forming trench isolation region to embody isolation region proper for high integrated semiconductor device - Google Patents
Method for forming trench isolation region to embody isolation region proper for high integrated semiconductor device Download PDFInfo
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- KR100442852B1 KR100442852B1 KR1019970047199A KR19970047199A KR100442852B1 KR 100442852 B1 KR100442852 B1 KR 100442852B1 KR 1019970047199 A KR1019970047199 A KR 1019970047199A KR 19970047199 A KR19970047199 A KR 19970047199A KR 100442852 B1 KR100442852 B1 KR 100442852B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 트렌치 소자분리 영역 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a trench isolation region.
반도체소자를 제조하는 데 있어서, 서로 이웃한 트랜지스터를 격리시키기 위한 소자분리 영역은 필수적으로 요구된다. 이러한 소자분리 영역을 형성하는 방법으로 로코스(LOCOS; local oxidation of silicon) 공정이 널리 사용되어 왔다. 로코스 공정은 반도체기판 상에 200Å 내지 300Å의 얇은 패드산화막을 형성하는 단계와, 상기 패드산화막 상에 1000Å 내지 2000Å의 두꺼운 패드질화막을 형성하는 단계와, 상기 패드질화막을 패터닝하여 소자분리막이 형성되는 영역을 개구시키는 패드질화막 패턴을 형성하는 단계와, 상기 패드질화막이 형성된 결과물을 열산화시키어 상기 패드질화막에 의하여 개구된 영역에 3000Å 내지 5000Å의 두꺼운 소자분리막을 선택적으로 형성하는 단계와, 상기 패드질화막을 제거하는 단계를 포함한다.In the manufacture of semiconductor devices, device isolation regions for isolating neighboring transistors are indispensable. As a method of forming the device isolation region, a LOCOS (local oxidation of silicon) process has been widely used. The LOCOS process includes forming a thin pad oxide film having a thickness of 200 mV to 300 mW on a semiconductor substrate, forming a thick pad nitride film of 1000 mW to 2000 mW on the pad oxide film, and patterning the pad nitride film to form a device isolation film. Forming a pad nitride film pattern for opening an area, thermally oxidizing the resultant product on which the pad nitride film is formed, and selectively forming a 3000 nm to 5000 mm thick device isolation film in an area opened by the pad nitride film; Removing the step.
상술한 종래의 로코스 공정에 의하면, 소자분리막 형성시 패드질화막 패턴의 가장자리 아래에 버즈비크(bird's beak)가 형성되어 서로 이웃한 소자분리막 사이의 활성영역 폭을 감소시킨다. 따라서, 0.5 마이크론 이하의 디자인 룰을 갖는 고집적 반도체소자의 소자분리막으로 적합하지 않은 문제점이 있다.According to the conventional LOCOS process described above, a bird's beak is formed under the edge of the pad nitride layer pattern when the device isolation layer is formed to reduce the active region width between adjacent device isolation layers. Therefore, there is a problem that is not suitable as a device isolation film of a highly integrated semiconductor device having a design rule of 0.5 microns or less.
본 발명의 목적은 고집적 반도체소자에 적합하도록 버즈비크가 형성되는 것을 방지할 수 있는 트렌치 소자분리 영역 형성방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a trench isolation region capable of preventing the formation of a buzz beak so as to be suitable for a highly integrated semiconductor device.
도 1 내지 도 4는 본 발명에 따른 트렌치 소자분리 영역 형성방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of forming a trench isolation region according to the present invention.
상기 목적을 달성하기 위하여 본 발명에 따른 트렌치 소자분리 영역 형성방법은 반도체기판 상에 상기 반도체기판의 소정영역을 노출시키면서 차례로 적층된 패드산화막 패턴, 패드질화막 패턴, 및 트렌치 식각저지막 패턴을 형성한다. 그리고, 상기 노출된 반도체기판을 식각하여 소정의 깊이를 갖는 트렌치 영역을 형성한다. 다음에, 상기 트렌치 영역의 측벽 및 바닥에 희생산화막을 형성한다. 이어서, 상기 희생산화막 및 상기 트렌치 식각저지막 패턴을 제거함으로써 상기 트렌치 영역의 측벽 및 바닥을 노출시킨다. 계속해서, 상기 노출된 트렌치 영역의 측벽 및 바닥에 건식 열산화막을 형성하고, 상기 건식 열산화막이 형성된 결과물 전면에 상기 트렌치 영역을 채우는 CVD 산화막을 형성한다.In order to achieve the above object, the trench isolation region forming method according to the present invention forms a pad oxide layer pattern, a pad nitride layer pattern, and a trench etch stop layer pattern that are sequentially stacked while exposing a predetermined region of the semiconductor substrate on the semiconductor substrate. . The exposed semiconductor substrate is etched to form a trench region having a predetermined depth. Next, a sacrificial oxide film is formed on the sidewalls and the bottom of the trench region. Next, the sidewalls and the bottom of the trench region are exposed by removing the sacrificial oxide layer and the trench etch stop layer pattern. Subsequently, a dry thermal oxide film is formed on sidewalls and bottoms of the exposed trench regions, and a CVD oxide film is formed on the entire surface of the resultant product on which the dry thermal oxide film is formed.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 소자분리막이 형성되는 영역을 한정하기 위한 포토레지스트 패턴(9)을 형성하는 단계를 설명하기 위한 단면도이다. 먼저, 반도체기판(1), 예컨대 실리콘기판 상에 200Å 내지 300Å의 얇은 패드산화막(3)을 형성한다. 여기서, 상기 반도체기판(1)은 N웰 또는 P웰 영역일 수도 있다. 다음에, 상기 패드산화막(3) 상에 패드질화막(5) 및 트렌치 식각 저지막(7)을 순차적으로 형성한다. 여기서, 상기 패드질화막(5)은 1000Å 내지 3000Å, 바람직하게는 약 2000Å의 CVD 질화막으로 형성하는 것이 바람직하고, 상기 트렌치 식각 저지막(7)은 1000Å 내지 3000Å, 바람직하게는 약 2000Å의 고온산화막(HTO; high temperature oxide)으로 형성하는 것이 바람직하다. 이어서, 상기 트렌치 식각 저지막(7) 상에 통상의 사진공정으로 트렌치 식각 저지막(7)의 소정영역을 노출시키는 포토레지스트 패턴(9)을 형성한다.FIG. 1 is a cross-sectional view for explaining a step of forming a photoresist pattern 9 for defining a region where an isolation layer is formed. First, a thin pad oxide film 3 of 200 Å to 300 Å is formed on the semiconductor substrate 1, for example, a silicon substrate. The semiconductor substrate 1 may be an N well or a P well region. Next, the pad nitride film 5 and the trench etch stop film 7 are sequentially formed on the pad oxide film 3. Here, the pad nitride film 5 is preferably formed of a CVD nitride film of 1000 kPa to 3000 kPa, preferably about 2000 kPa, and the trench etch stop film 7 is 1000 kPa to 3000 kPa, preferably about 2000 kPa of high temperature oxide film ( It is preferable to form with high temperature oxide (HTO). Subsequently, a photoresist pattern 9 is formed on the trench etch stop layer 7 to expose a predetermined region of the trench etch stop layer 7 by a normal photolithography process.
도 2는 패드산화막 패턴(3a), 패드질화막 패턴(5a), 및 트렌치 식각저지막 패턴(7a)을 형성하는 단계를 설명하기 위한 단면도이다. 상세히 설명하면, 상기 포토레지스트 패턴(9)을 식각 마스크로하여 상기 노출된 트렌치 식각저지막(7), 상기 패드질화막(5), 및 상기 패드산화막(3)을 연속적으로 건식 식각함으로써, 반도체기판(1)의 소정영역을 노출시키는 패드산화막 패턴(3a), 패드질화막 패턴(5a), 및 트렌치 식각저지막 패턴(7a)을 형성한다. 이때, 상기 건식 식각공정은 불소가 함유된 가스를 사용하는 플라즈마 식각공정으로 진행함으로써, 상기 트렌치 식각저지막(7), 즉 고온산화막과 상기 패드질화막(5) 사이의 식각 선택비가 낮다. 따라서, 트렌치 식각저지막(7), 패드질화막(5) 및 패드산화막(3)이 연속적으로 용이하게 식각된다. 다음에, 상기 포토레지스트 패턴(9)을 산소 플라즈마 공정으로 제거하고, 황산용액으로 잔존하는 포토레지스트 패턴(9)을 완전히 제거한다.2 is a cross-sectional view for explaining a step of forming the pad oxide film pattern 3a, the pad nitride film pattern 5a, and the trench etch stop film pattern 7a. In detail, the semiconductor substrate is formed by continuously dry etching the exposed trench etch stop layer 7, the pad nitride layer 5, and the pad oxide layer 3 using the photoresist pattern 9 as an etching mask. The pad oxide film pattern 3a, the pad nitride film pattern 5a, and the trench etch stop film pattern 7a exposing the predetermined region of (1) are formed. In this case, the dry etching process proceeds to a plasma etching process using a gas containing fluorine, whereby the etching selectivity between the trench etch stop layer 7, that is, the high temperature oxide layer and the pad nitride layer 5 is low. Therefore, the trench etch stop film 7, the pad nitride film 5 and the pad oxide film 3 are easily etched continuously. Next, the photoresist pattern 9 is removed by an oxygen plasma process, and the photoresist pattern 9 remaining in the sulfuric acid solution is completely removed.
도 3은 트렌치 영역(T) 및 희생산화막(11)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 상기 트렌치 식각저지막 패턴(7a)을 식각 마스크로하여 상기 노출된 반도체기판(1), 즉 실리콘기판을 건식 식각하여 소정의 깊이, 예컨대 2000Å 내지 9000Å, 바람직하게는 대략 6000Å의 깊이를 갖는 트렌치 영역(T)을 형성한다. 이때, 상기 트렌치 영역(T)을 형성하기 위한 건식 식각공정은 염소 가스, HBr 가스 및 산소 가스를 사용하여 실시하는 것이 바람직하다. 이와 같이 트렌치 영역(T)을 형성하기 위한 건식 식각공정을 실시하면, 트렌치 영역(T)의 측벽 및 바닥에 식각 손상이 가해진다. 이러한 식각 손상은 차후에 소자분리 특성, 예컨대 서로 이웃한 활성영역 사이의 누설전류 특성을 저하시키는 원인이 된다. 따라서, 상기 트렌치 영역(T)이 형성된 결과물을 800℃ 내지 1000℃, 바람직하게는 약 950℃의 온도에서 습식 산화시키어 트렌치 영역(T)의 측벽 및 바닥에 200Å 내지 500Å, 바람직하게는 약 400Å의 두께를 갖는 희생산화막(11)을 형성한다. 이와 같이 트렌치 영역(T)의 측벽 및 바닥에 습식 산화공정으로 희생산화막(11)을 형성하면, 트렌치 영역(T)을 형성할 때 가해진 식각손상이 치유됨은 물론, 트렌치 영역(T)의 하부 코너가 둥글게 형성된다. 따라서, 후속공정에 의하여 상기 트렌치 영역(T) 내에 형성되는 소자분리막을 가로질러 반도체기판(1)에 인가되는 전계가 트렌치 영역(T)의 하부코너에 집중되는 현상을 완화시킬 수 있음은 물론, 트렌치 영역(T)의 측벽 및 바닥을 통하여 흐르는 누설전류 특성을 개선시킬 수 있다.3 is a cross-sectional view for describing a step of forming the trench region T and the sacrificial oxide film 11. Specifically, dry etching the exposed semiconductor substrate 1, ie, the silicon substrate, using the trench etch stop layer pattern 7a as an etch mask, may be performed at a predetermined depth, for example, 2000 Å to 9000 Å, preferably about 6000 Å. A trench region T having a depth is formed. In this case, the dry etching process for forming the trench region T may be performed using chlorine gas, HBr gas, and oxygen gas. When the dry etching process for forming the trench region T is performed as described above, etching damage is applied to the sidewalls and the bottom of the trench region T. FIG. Such etching damage may later cause deterioration of device isolation characteristics, such as leakage current characteristics between adjacent active regions. Therefore, the resultant in which the trench region T is formed is wet oxidized at a temperature of 800 ° C. to 1000 ° C., preferably about 950 ° C., so that the sidewalls and the bottom of the trench area T are 200 to 500 mW, preferably about 400 mW. A sacrificial oxide film 11 having a thickness is formed. As such, when the sacrificial oxide film 11 is formed on the sidewalls and the bottom of the trench region T by a wet oxidation process, the etching damage applied when the trench region T is formed is healed, and the lower corner of the trench region T is formed. Is rounded. Therefore, the phenomenon that the electric field applied to the semiconductor substrate 1 across the device isolation film formed in the trench region T may be concentrated in the lower corner of the trench region T may be alleviated by a subsequent process. The leakage current characteristic flowing through the sidewalls and the bottom of the trench region T may be improved.
도 4는 건식 열산화막(13) 및 소자분리용 산화막(15)을 형성하는 단계를 설명하기 위한 단면도이다. 좀 더 구체적으로 설명하면, 상기 희생산화막(11)을 습식 식각용액, 예컨대 불산용액 또는 완충산화막 식각용액(BOE; buffered oxide etchant)으로 제거하여 식각손상이 치유된 트렌치 영역(T)의 측벽 및 바닥을 노출시킨다. 이때, 상기 트렌치 식각저지막 패턴(7a) 역시 산화막이므로 제거되어 패드질화막 패턴(5a) 또한 노출된다. 다음에, 상기 결과물을 건식 산화시키어 상기 노출된 트렌치 영역(T)의 측벽 및 바닥에 막질이 치밀한 건식 열산화막(13)을 형성한다. 상기 건식 열산화막(13)은 1000℃ 내지 1200℃, 바람직하게는 약 1150℃의 고온에서 200Å 내지 500Å, 바람직하게는 약 400Å의 두께로 형성하는 것이 바람직하다. 이어서, 상기 건식 열산화막(13)이 형성된 결과물 전면에 상기 트렌치 영역(T)을 채우기 위하여 단차도포성이 우수한 CVD 산화막(15)을 형성한다. 상기 CVD 산화막(15)은 언도우프트 산화막(USG; undoped silicate glass)으로 형성하는 것이 바람직하다.4 is a cross-sectional view for explaining a step of forming a dry thermal oxide film 13 and an oxide film 15 for device isolation. In more detail, the sacrificial oxide layer 11 is removed by a wet etching solution, such as hydrofluoric acid solution or a buffered oxide etchant (BOE), and the sidewalls and bottom of the trench region T where the etch damage is healed. Expose In this case, since the trench etch stop layer pattern 7a is also an oxide layer, the trench etch stop layer pattern 7a is also removed to expose the pad nitride layer pattern 5a. Next, the resultant is dry oxidized to form a dry thermal oxide film 13 having a dense film quality on the sidewalls and the bottom of the exposed trench region T. The dry thermal oxide film 13 is preferably formed at a thickness of 200 kPa to 500 kPa, preferably about 400 kPa at a high temperature of 1000 ° C to 1200 ° C, preferably about 1150 ° C. Subsequently, a CVD oxide film 15 having excellent step coverage is formed in order to fill the trench region T on the entire surface of the resultant product on which the dry thermal oxide film 13 is formed. The CVD oxide film 15 may be formed of undoped silicate glass (USG).
계속해서, 도시하지는 않았지만 상기 패드질화막 패턴(5a)이 노출될 때까지 CVD 산화막(15)을 평탄화시키어 트렌치 영역(T) 내에 소자분리막을 형성함으로써 소자분리 영역을 완성한다.Subsequently, although not shown, the device isolation region is completed by forming the device isolation film in the trench region T by planarizing the CVD oxide film 15 until the pad nitride film pattern 5a is exposed.
본 발명은 상기 실시예에 한정되지 않고 당업자의 수준에서 그 변형 및 개량이 가능하다.The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.
상술한 바와 같이 본 발명에 따르면, 트렌치 영역의 측벽 및 바닥에 가해지는 식각 손상을 치유함은 물론, 버즈비크가 존재하지 않는 트렌치 소자분리 영역을 형성할 수 있다. 이에 따라, 고집적 반도체소자에 적합한 소자분리 영역을 구현하는 것이 가능하다.As described above, according to the present invention, it is possible to cure the etching damages applied to the sidewalls and the bottom of the trench region, as well as to form a trench isolation region in which the burj beak is not present. Accordingly, it is possible to implement a device isolation region suitable for highly integrated semiconductor devices.
Claims (5)
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| KR100564423B1 (en) * | 1999-07-02 | 2006-03-28 | 주식회사 하이닉스반도체 | Formation method for isolation layer of semiconductor device |
| KR100400301B1 (en) * | 1999-12-30 | 2003-10-01 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100429678B1 (en) * | 1999-12-30 | 2004-05-03 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100419754B1 (en) * | 1999-12-31 | 2004-02-21 | 주식회사 하이닉스반도체 | A method for forming a field oxide of a semiconductor device |
| KR100533381B1 (en) * | 2001-06-29 | 2005-12-06 | 주식회사 하이닉스반도체 | Method for forming the Isolation Layer of Semiconductor Device |
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| JPH05275528A (en) * | 1992-03-27 | 1993-10-22 | Sharp Corp | Forming method of element isolating region |
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| KR102262228B1 (en) | 2013-05-16 | 2021-06-09 | 오스람 옵토 세미컨덕터스 게엠베하 | Method for producing an optoelectronic semiconductor chip |
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